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| author | Du Huanpeng <u74147@gmail.com> | 2016-04-21 19:30:28 +0800 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-04-21 15:17:52 +0200 |
| commit | fe03b34fbefab504ec352488e12b6d39413a1f32 (patch) | |
| tree | 2855d128a0b60ece156ced7b7958888e89b2e858 /arch/blackfin/cpu-bf561/start.S | |
| parent | 484a088f78a57b7341c190c78ef62df6a632754d (diff) | |
| download | barebox-fe03b34fbefab504ec352488e12b6d39413a1f32.tar.gz barebox-fe03b34fbefab504ec352488e12b6d39413a1f32.tar.xz | |
whole tree: remove trailing whitespaces
Signed-off-by: Du Huanpeng <u74147@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/blackfin/cpu-bf561/start.S')
| -rw-r--r-- | arch/blackfin/cpu-bf561/start.S | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/blackfin/cpu-bf561/start.S b/arch/blackfin/cpu-bf561/start.S index 96da6b5dda..56c5e8455d 100644 --- a/arch/blackfin/cpu-bf561/start.S +++ b/arch/blackfin/cpu-bf561/start.S @@ -56,7 +56,7 @@ _stext: SSYNC; /* As per HW reference manual DAG registers, - * DATA and Address resgister shall be zero'd + * DATA and Address resgister shall be zero'd * in initialization, after a reset state */ r1 = 0; /* Data registers zero'd */ @@ -73,7 +73,7 @@ _stext: p3 = 0; p4 = 0; p5 = 0; - + i0 = 0; /* DAG Registers zero'd */ i1 = 0; i2 = 0; @@ -124,7 +124,7 @@ no_soft_reset: r1 = 0; LSETUP(4,4) lc0 = p1; [ p0 ++ ] = r1; - + p0.h = hi(SIC_IWR); p0.l = lo(SIC_IWR); r0.l = 0x1; @@ -217,8 +217,8 @@ _real_start: #ifdef CONFIG_BF537 -/* Initialise General-Purpose I/O Modules on BF537 - * Rev 0.0 Anomaly 05000212 - PORTx_FER, +/* Initialise General-Purpose I/O Modules on BF537 + * Rev 0.0 Anomaly 05000212 - PORTx_FER, * PORT_MUX Registers Do Not accept "writes" correctly */ p0.h = hi(PORTF_FER); @@ -292,8 +292,8 @@ DMA: /* Set Destination DMAConfig = DMA Enable, Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; - -WAIT_DMA_DONE: + +WAIT_DMA_DONE: p0.h = hi(MDMA_D0_IRQ_STATUS); p0.l = lo(MDMA_D0_IRQ_STATUS); R0 = W[P0](Z); |