move boards to arch/<architecure>/boards

this will allow each arch to handle the boards more simply and depending on
there need

the env var BOARD will refer to the current board dirent

for sandbox as we have only one board the board dirent is arch/sandbox/board

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

31 files changed, 1424 insertions, 3 deletions

diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index f377325add..ec70028a16 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -63,7 +63,7 @@ PHONY += maketools
 
 
 ifneq ($(board-y),)
-BOARD  := board/$(board-y)/
+BOARD  := arch/m68k/boards/$(board-y)/
 else
 BOARD  :=
 endif
diff --git a/arch/m68k/boards/kp_ukd_r1_num/Makefile b/arch/m68k/boards/kp_ukd_r1_num/Makefile
new file mode 100644
index 0000000000..65f2a02fca
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/Makefile
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net>
+# See file CREDITS for list of people who contributed to this project.
+#
+# This file is part of barebox.
+#
+# barebox is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# barebox is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+# The build system allows to split everything into distinct files covering an
+# separate issue. Use that!
+
+# Board specific callbacks and initialisations
+
+obj-y += lowlevel_init.o
+obj-y += highlevel_init.o
+obj-y += kp_ukd_r1_num.o
+
+obj-y += pci-stubs.o
+
diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update b/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update
new file mode 100644
index 0000000000..014bce3512
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z "$part" -o -z "$image" ]; then
+	echo "define \$part and \$image"
+	exit 1
+fi
+
+if [ ! -e "$part" ]; then
+	echo "Partition $part does not exist"
+	exit 1
+fi
+
+if [ $# = 1 ]; then
+	image=$1
+fi
+
+if [ x$ip = xdhcp ]; then
+	dhcp
+fi
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; then
+	echo "update aborted"
+	exit 1
+fi
+
+unprotect $part
+
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing $image to $part"
+echo
+tftp $image $part
diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot b/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot
new file mode 100644
index 0000000000..c9fcbac620
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xflash ]; then
+	root=flash
+	kernel=flash
+fi
+
+if [ x$1 = xnet ]; then
+	root=net
+	kernel=net
+fi
+
+if [ x$ip = xdhcp ]; then
+	bootargs="$bootargs ip=dhcp"
+else
+	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+fi
+
+if [ x$root = xflash ]; then
+	bootargs="$bootargs root=$rootpart rootfstype=jffs2"
+else
+	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot"
+fi
+
+bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts"
+
+if [ $kernel = net ]; then
+	if [ x$ip = xdhcp ]; then
+		dhcp
+	fi
+	tftp $uimage uImage || exit 1
+	bootm uImage
+else
+	bootm /dev/nor0.kernel
+fi
+
diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/init b/arch/m68k/boards/kp_ukd_r1_num/env/bin/init
new file mode 100644
index 0000000000..48e2139f7d
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/init
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+addpart /dev/nor0 $mtdparts
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+	echo
+	echo "type update_kernel [<imagename>] to update kernel into flash"
+	echo "type udate_root [<imagename>] to update rootfs into flash"
+	echo
+	exit
+fi
+
+boot
\ No newline at end of file
diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop
new file mode 100644
index 0000000000..24e76cbed7
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop
@@ -0,0 +1,14 @@
+pci stat
+pci stat -c
+while true; do 
+        pci readm 32 0xA1000000 32 -s
+        pci readm 32 0xA2000000 256 -s
+        pci dmatx 2000 a2000100 128 -s
+        pci writem 32 0xa2000100 0x12345678 4 -s
+        pci readm 32 0xA3000000 256 -s
+        pci dmatx 2000 a3000040 128 -s
+        pci writem 32 0xa3000100 0x12345678 4 -s
+        pci readm 32 0xA4000000 16 -s
+        pci dmatx 2000 a4000080 4 -s
+        pci writem 32 0xa4000080 0x12345678 4 -s
+done
diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop
new file mode 100644
index 0000000000..4a804f9f31
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop
@@ -0,0 +1,13 @@
+pci stat
+pci stat -c
+while true; do 
+        pci readm 32 0xA1000000 32 -s
+        pci readm 32 0xA2000000 256 -s
+        pci writem 32 0xa2000100 0x12345678 4 -s
+        pci readm 32 0xA3000000 256 -s
+        pci writem 32 0xa3000100 0x12345678 4 -s
+        pci readm 32 0xA4000000 16 -s
+        pci writem 32 0xa4000080 0x12345678 4 -s
+
+#       pci dmatx 2000 a3000040 128 -s
+done
diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel
new file mode 100644
index 0000000000..1ad95fc5d6
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+part=/dev/nor0.kernel
+
+. /env/bin/_update $1
diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root
new file mode 100644
index 0000000000..b757a5b922
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+. /env/config
+
+image=$jffs2
+part=/dev/nor0.root
+
+. /env/bin/_update $1
diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/config b/arch/m68k/boards/kp_ukd_r1_num/env/config
new file mode 100644
index 0000000000..14958ba1df
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/env/config
@@ -0,0 +1,32 @@
+#!/bin/sh
+
+# can be either 'net' or 'flash'
+kernel=net
+root=net
+
+# use 'dhcp' todo dhcp in barebox and in kernel
+ip=dhcp
+
+#
+# setup default ethernet address
+#
+eth0.ipaddr=192.168.0.99
+eth0.netmask=255.255.255.0
+eth0.gateway=192.168.0.110
+eth0.serverip=192.168.0.110
+
+uimage=uImage-mcf5475
+jffs2=root-mcf5475-ptx.jffs2
+
+autoboot_timeout=3
+
+#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs"
+nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3"
+bootargs="console=ttyS0 rw initcall_debug debug"
+
+#
+# setup the partitions in the main flash
+#
+mtdparts=512k(self),256k(env),3M(kernel),-(root)
+rootpart="/dev/mtdblock3"
+
diff --git a/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c b/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c
new file mode 100644
index 0000000000..3a88cd68c7
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c
@@ -0,0 +1,124 @@
+/*
+ * (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This file is part of barebox.
+ *
+ * barebox is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * barebox is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *  @brief This file contains high-level init functions.
+ *
+ */
+#include <common.h>
+#include <reloc.h>
+#include <config.h>
+#include <mach/mcf54xx-regs.h>
+
+static void board_gpio_init(void)
+{
+	/*
+	 * Enable Ethernet signals so that, if a cable is plugged into
+	 * the ports, the lines won't be floating and potentially cause
+	 * erroneous transmissions
+	 */
+	MCF_GPIO_PAR_FECI2CIRQ = 0
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07;
+}
+
+
+static void board_psc_init(void)
+{
+#if (CFG_EARLY_UART_PORT == 0)
+	MCF_GPIO_PAR_PSC0 = (0
+#ifdef HARDWARE_FLOW_CONTROL
+	                     | MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS
+	                     | MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS
+#endif
+	                     | MCF_GPIO_PAR_PSC0_PAR_TXD0
+	                     | MCF_GPIO_PAR_PSC0_PAR_RXD0);
+#elif (CFG_EARLY_UART_PORT == 1)
+	MCF_GPIO_PAR_PSC1 = (0
+#ifdef HARDWARE_FLOW_CONTROL
+	                     | MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS
+	                     | MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS
+#endif
+	                     | MCF_GPIO_PAR_PSC1_PAR_TXD1
+	                     | MCF_GPIO_PAR_PSC1_PAR_RXD1);
+#elif (CFG_EARLY_UART_PORT == 2)
+	MCF_GPIO_PAR_PSC2 = (0
+#ifdef HARDWARE_FLOW_CONTROL
+	                     | MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS
+	                     | MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS
+#endif
+	                     | MCF_GPIO_PAR_PSC2_PAR_TXD2
+	                     | MCF_GPIO_PAR_PSC2_PAR_RXD2);
+#elif (CFG_EARLY_UART_PORT == 3)
+	MCF_GPIO_PAR_PSC3 = (0
+#ifdef HARDWARE_FLOW_CONTROL
+	                     | MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS
+	                     | MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS
+#endif
+	                     | MCF_GPIO_PAR_PSC3_PAR_TXD3
+	                     | MCF_GPIO_PAR_PSC3_PAR_RXD3);
+#else
+#error "Invalid CFG_EARLY_UART_PORT setting"
+#endif
+
+	/* Put PSC in UART mode */
+	MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART;
+
+	/* Call generic UART initialization */
+//    mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud());
+}
+
+
+/** Do board specific early init
+ *
+ * @note We run at link address now, you can now call other code
+ */
+void board_init_highlevel(void)
+{
+	/* Initialize platform specific GPIOs */
+	board_gpio_init();
+
+	/* Init UART GPIOs and Modes */
+	board_psc_init();
+
+	/* Setup the early init data */
+#ifdef CONFIG_HAS_EARLY_INIT
+	early_init();
+#endif
+	/* Configure the early debug output facility */
+#ifdef CONFIG_DEBUG_LL
+	early_debug_init();
+#endif
+}
+
+/** Provide address of early debug low-level output
+ *
+ * @todo Should return real address for UART register map.
+ */
+void *get_early_console_base(const char *name)
+{
+	return (void*)1 + CFG_EARLY_UART_PORT;
+}
diff --git a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c
new file mode 100644
index 0000000000..9bf1713cc4
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c
@@ -0,0 +1,153 @@
+/*
+ * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This file is part of barebox.
+ *
+ * barebox is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * barebox is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <fec.h>
+#include <environment.h>
+#include <mach/mcf54xx-regs.h>
+//#include <mach/gpio.h>
+#include <mach/clocks.h>
+#include <asm/io.h>
+#include <partition.h>
+
+/*
+ *  Return board clock in MHz    FIXME move to clocks file
+ */
+ulong mcfv4e_get_bus_clk(void)
+{
+	return CFG_SYSTEM_CORE_CLOCK;
+}
+/*
+ * Up to 64MiB NOR type flash, connected to
+ * CS line 0, data width is 32 bit
+ */
+static struct device_d cfi_dev = {
+	.name     = "cfi_flash",
+	.map_base = CFG_FLASH_ADDRESS,
+	.size     = CFG_FLASH_SIZE,
+};
+
+/*
+ * up to 2MiB static RAM type memory, connected
+ * to CS4, data width is 16 bit
+ */
+//static struct device_d sram_dev = {
+//	.name     = "sram",
+//FIXME	.map_base = IMX_CS4_BASE,
+//FIXME	.size     = IMX_CS4_RANGE,	/* area size */
+//};
+
+/*
+ * ?MiB NAND type flash, data width 8 bit
+ */
+//static struct device_d nand_dev = {
+//	.name     = "cfi_flash_nand",
+//	.map_base = 0xfc000000,	/* FIXME */
+//	.size     = 32 * 1024 * 1024,	/* FIXME */
+//};
+
+
+/*
+ * Build in FastEthernetControllers (FECs)
+ */
+static struct fec_platform_data fec_info = {
+	.xcv_type = MII100,
+};
+
+static struct device_d network_dev0 = {
+	.name     = "fec_mcf54xx",
+	.map_base = MCF_FEC_ADDR(0),
+	.size     = MCF_FEC_SIZE(0),	   /* area size */
+	.platform_data	= &fec_info,
+};
+static struct device_d network_dev1 = {
+	.name     = "fec_mcf54xx",
+	.map_base = MCF_FEC_ADDR(1),
+	.size     = MCF_FEC_SIZE(1),	   /* area size */
+	.platform_data	= &fec_info,
+};
+
+/*
+ * 128MiB of SDRAM, data width is 32 bit
+ */
+static struct memory_platform_data ram_pdata = {
+	.name = "ram0",
+	.flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev = {
+	.name     = "mem",
+	.map_base = CFG_SDRAM_ADDRESS,
+	.size     = CFG_SDRAM_SIZE,
+	.platform_data = &ram_pdata,
+};
+
+static int mcfv4e_devices_init(void)
+{
+	printf("Setting up board devices...\n");
+
+	/* setup pins for I2C2 (for EEPROM, RTC) */
+//FIXME	imx_gpio_mode(MUX_CSPI2_MOSI_I2C2_SCL);
+//FIXME	imx_gpio_mode(MUX_CSPI2_MISO_I2C2_SCL);
+
+	register_device(&cfi_dev);
+
+	/*
+	 * Create partitions that should be
+	 * not touched by any regular user
+	 */
+	devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0");	/* ourself */
+	devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0");	/* environment */
+	protect_file("/dev/env0", 1);
+
+	//register_device(&sram_dev);
+	//register_device(&nand_dev);
+
+	register_device(&network_dev0);
+	//register_device(&network_dev1);
+
+	register_device(&sdram_dev);
+
+	return 0;
+}
+
+device_initcall(mcfv4e_devices_init);
+
+static struct device_d mcfv4e_serial_device = {
+	.name     = "mcfv4e_serial",
+	.map_base = 1+CFG_EARLY_UART_PORT,
+	.size     = 16 * 1024,
+};
+
+static int mcfv4e_console_init(void)
+{
+	/* init gpios for serial port */
+
+	/* Already set in lowlevel_init.c */
+
+	register_device(&mcfv4e_serial_device);
+	return 0;
+}
+
+console_initcall(mcfv4e_console_init);
+
diff --git a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox
new file mode 100644
index 0000000000..ca0fcbcf39
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox
@@ -0,0 +1,13 @@
+/** @page kp_ukd_r1 konzeptpark MCB2 Prototype Board
+
+This target is based on a PhyTec PhyCore MCF54x5 NUM CPU. The card is shipped with:
+
+- up to 64MiB NOR type Flash Memory
+- 128MiB synchronous dynamic RAM
+- PCI USB 2.0 Host
+- PCCard Controller
+- MiniPCI Parallel
+- MiniPCIe (USB lane only)
+- ...
+
+*/
diff --git a/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c b/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c
new file mode 100644
index 0000000000..b3de505c24
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c
@@ -0,0 +1,183 @@
+/*
+ * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This file is part of barebox.
+ *
+ * barebox is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * barebox is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *  @brief This file contains ...
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <mach/mcf54xx-regs.h>
+
+/** Initialize board specific very early inits
+ *
+ * @note This code is not allowed to call other code - just init
+ * your Chipselects and SDRAM stuff here!
+ */
+void board_init_lowlevel(void)
+{
+	/*
+	 * The phyCORE-MCF548x has a 32MB or 64MB boot flash.
+	 * The is a CF Card and ControlRegs on CS1 and CS2
+	 */
+
+	/* Setup SysGlue Chip-Select */
+	MCF_FBCS_CSAR5 = MCF_FBCS_CSAR_BA(CFG_SYSGLUE_ADDRESS);
+
+	MCF_FBCS_CSCR5 = (MCF_FBCS_CSCR_PS_32
+			  | MCF_FBCS_CSCR_AA
+			  | MCF_FBCS_CSCR_ASET(1)
+			  | MCF_FBCS_CSCR_WS(CFG_SYSGLUE_WAIT_STATES));
+
+	MCF_FBCS_CSMR5 = (MCF_FBCS_CSMR_BAM_16M
+			  | MCF_FBCS_CSMR_V);
+
+	/* Setup boot flash chip-select */
+	MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS);
+
+	MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32
+			  | MCF_FBCS_CSCR_AA
+			  | MCF_FBCS_CSCR_ASET(1)
+			  | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES));
+
+	MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M
+			  | MCF_FBCS_CSMR_V);
+
+	/*
+	* Check to see if the SDRAM has already been initialized
+	* by a run control tool
+	*/
+	if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
+	{
+		/*
+		* Basic configuration and initialization
+		*/
+		// 0x000002AA
+		MCF_SDRAMC_SDRAMDS = (0
+				      | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+				      | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+				      | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+				      | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+				      | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+				     );
+
+		// 0x0000001A
+		MCF_SDRAMC_CS0CFG = (0
+				     | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS)
+				     | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE)
+				    );
+
+		MCF_SDRAMC_CS1CFG = 0;
+		MCF_SDRAMC_CS2CFG = 0;
+		MCF_SDRAMC_CS3CFG = 0;
+
+		// 0x73611730
+		MCF_SDRAMC_SDCFG1 = (0
+				     | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5))
+				     | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1))
+				     | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2))
+				     | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
+				     | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
+				     | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
+				     | MCF_SDRAMC_SDCFG1_WTLAT(3)
+				    );
+
+		// 0x46770000
+		MCF_SDRAMC_SDCFG2 = (0
+				     | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2)
+				     | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR)
+				     | MCF_SDRAMC_SDCFG2_BRD2WT(7)
+				     | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1)
+				    );
+
+		/*
+		* Precharge and enable write to SDMR
+		*/
+		// 0xE10B0002
+		MCF_SDRAMC_SDCR = (0
+				   | MCF_SDRAMC_SDCR_MODE_EN
+				   | MCF_SDRAMC_SDCR_CKE
+				   | MCF_SDRAMC_SDCR_DDR
+				   | MCF_SDRAMC_SDCR_MUX(1)    // 13 x 10 x 2 ==> MUX=1
+				   | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5))
+				   | MCF_SDRAMC_SDCR_IPALL
+				  );
+
+		/*
+		* Write extended mode register
+		*/
+		// 0x40010000
+		MCF_SDRAMC_SDMR = (0
+				   | MCF_SDRAMC_SDMR_BNKAD_LEMR
+				   | MCF_SDRAMC_SDMR_AD(0x0)
+				   | MCF_SDRAMC_SDMR_CMD
+				  );
+
+		/*
+		* Write mode register and reset DLL
+		*/
+		// 0x048d0000
+		MCF_SDRAMC_SDMR = (0
+				   | MCF_SDRAMC_SDMR_BNKAD_LMR
+				   | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD)
+				   | MCF_SDRAMC_SDMR_CMD
+				  );
+
+		/*
+		* Execute a PALL command
+		*/
+		// 0xE10B0002
+		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
+
+		/*
+		* Perform two REF cycles
+		*/
+		// 0xE10B0004
+		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+
+		/*
+		* Write mode register and clear reset DLL
+		*/
+		// 0x008D0000
+		MCF_SDRAMC_SDMR = (0
+				   | MCF_SDRAMC_SDMR_BNKAD_LMR
+				   | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD)
+				   | MCF_SDRAMC_SDMR_CMD
+				  );
+
+		/*
+		* Enable auto refresh and lock SDMR
+		*/
+		// 0x610B0000
+		MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
+
+		// 0x710B0F00
+		MCF_SDRAMC_SDCR |= (0
+				    | MCF_SDRAMC_SDCR_REF
+				    | MCF_SDRAMC_SDCR_DQS_OE(0xF)
+				   );
+	}
+}
+
+/** @file
+ *
+ * Target specific early chipselect and SDRAM init.
+ */
diff --git a/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c b/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c
new file mode 100644
index 0000000000..b7ab7c7d72
--- /dev/null
+++ b/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c
@@ -0,0 +1,41 @@
+/*
+ * (C) 2007,2008 Carsten Schlote <schlote@vahanus.net>
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This file is part of barebox.
+ *
+ * barebox is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * barebox is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *  @brief This file contains callbacks for the PCI subsystem
+ *
+ */
+#include <common.h>
+#include <config.h>
+
+
+/** Returns mapping from PCI slot to CPU irq for the target board
+ * @return Coldfire IRQ vector number, or -1 for no irq
+ */
+int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin)
+{
+	int rc = -1;
+	switch (slot)
+	{
+	case 16        :  break;
+	case 17 ... 21 :  rc = 64 + 7; break;    // Eport IRQ7
+	}
+	return rc;
+}
diff --git a/arch/m68k/boards/phycore_mcf54xx/Makefile b/arch/m68k/boards/phycore_mcf54xx/Makefile
new file mode 100644
index 0000000000..054123fe75
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/Makefile
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net>
+# See file CREDITS for list of people who contributed to this project.
+#
+# This file is part of barebox.
+#
+# barebox is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# barebox is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+# The build system allows to split everything into distinct files covering an
+# separate issue. Use that!
+
+# Board specific callbacks and initialisations
+
+obj-y += lowlevel_init.o
+obj-y += highlevel_init.o
+obj-y += phyCore_MCF54xx.o
+
+obj-y += pci-stubs.o
+
diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/_update b/arch/m68k/boards/phycore_mcf54xx/env/bin/_update
new file mode 100644
index 0000000000..014bce3512
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/_update
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+if [ -z "$part" -o -z "$image" ]; then
+	echo "define \$part and \$image"
+	exit 1
+fi
+
+if [ ! -e "$part" ]; then
+	echo "Partition $part does not exist"
+	exit 1
+fi
+
+if [ $# = 1 ]; then
+	image=$1
+fi
+
+if [ x$ip = xdhcp ]; then
+	dhcp
+fi
+
+ping $eth0.serverip
+if [ $? -ne 0 ] ; then
+	echo "update aborted"
+	exit 1
+fi
+
+unprotect $part
+
+echo
+echo "erasing partition $part"
+erase $part
+
+echo
+echo "flashing $image to $part"
+echo
+tftp $image $part
diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/boot b/arch/m68k/boards/phycore_mcf54xx/env/bin/boot
new file mode 100644
index 0000000000..c9fcbac620
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/boot
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xflash ]; then
+	root=flash
+	kernel=flash
+fi
+
+if [ x$1 = xnet ]; then
+	root=net
+	kernel=net
+fi
+
+if [ x$ip = xdhcp ]; then
+	bootargs="$bootargs ip=dhcp"
+else
+	bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+fi
+
+if [ x$root = xflash ]; then
+	bootargs="$bootargs root=$rootpart rootfstype=jffs2"
+else
+	bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot"
+fi
+
+bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts"
+
+if [ $kernel = net ]; then
+	if [ x$ip = xdhcp ]; then
+		dhcp
+	fi
+	tftp $uimage uImage || exit 1
+	bootm uImage
+else
+	bootm /dev/nor0.kernel
+fi
+
diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/init b/arch/m68k/boards/phycore_mcf54xx/env/bin/init
new file mode 100644
index 0000000000..48e2139f7d
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/init
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+addpart /dev/nor0 $mtdparts
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+	echo
+	echo "type update_kernel [<imagename>] to update kernel into flash"
+	echo "type udate_root [<imagename>] to update rootfs into flash"
+	echo
+	exit
+fi
+
+boot
\ No newline at end of file
diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop b/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop
new file mode 100644
index 0000000000..24e76cbed7
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop
@@ -0,0 +1,14 @@
+pci stat
+pci stat -c
+while true; do 
+        pci readm 32 0xA1000000 32 -s
+        pci readm 32 0xA2000000 256 -s
+        pci dmatx 2000 a2000100 128 -s
+        pci writem 32 0xa2000100 0x12345678 4 -s
+        pci readm 32 0xA3000000 256 -s
+        pci dmatx 2000 a3000040 128 -s
+        pci writem 32 0xa3000100 0x12345678 4 -s
+        pci readm 32 0xA4000000 16 -s
+        pci dmatx 2000 a4000080 4 -s
+        pci writem 32 0xa4000080 0x12345678 4 -s
+done
diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop b/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop
new file mode 100644
index 0000000000..4a804f9f31
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop
@@ -0,0 +1,13 @@
+pci stat
+pci stat -c
+while true; do 
+        pci readm 32 0xA1000000 32 -s
+        pci readm 32 0xA2000000 256 -s
+        pci writem 32 0xa2000100 0x12345678 4 -s
+        pci readm 32 0xA3000000 256 -s
+        pci writem 32 0xa3000100 0x12345678 4 -s
+        pci readm 32 0xA4000000 16 -s
+        pci writem 32 0xa4000080 0x12345678 4 -s
+
+#       pci dmatx 2000 a3000040 128 -s
+done
diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel
new file mode 100644
index 0000000000..1ad95fc5d6
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+. /env/config
+
+image=$uimage
+part=/dev/nor0.kernel
+
+. /env/bin/_update $1
diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root
new file mode 100644
index 0000000000..b757a5b922
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root
@@ -0,0 +1,8 @@
+#!/bin/sh
+
+. /env/config
+
+image=$jffs2
+part=/dev/nor0.root
+
+. /env/bin/_update $1
diff --git a/arch/m68k/boards/phycore_mcf54xx/env/config b/arch/m68k/boards/phycore_mcf54xx/env/config
new file mode 100644
index 0000000000..58550625d2
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/env/config
@@ -0,0 +1,32 @@
+#!/bin/sh
+
+# can be either 'net' or 'flash'
+kernel=net
+root=net
+
+# use 'dhcp' todo dhcp in barebox and in kernel
+ip=dhcp
+
+#
+# setup default ethernet address
+#
+eth0.ipaddr=192.168.0.99
+eth0.netmask=255.255.255.0
+eth0.gateway=192.168.0.110
+eth0.serverip=192.168.0.110
+
+uimage=uImage-mcf5485
+jffs2=root-mcf5485-ptx.jffs2
+
+autoboot_timeout=3
+
+#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs"
+nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3"
+bootargs="console=ttyS0 rw initcall_debug debug"
+
+#
+# setup the partitions in the main flash
+#
+mtdparts=512k(self),256k(env),3M(kernel),-(root)
+rootpart="/dev/mtdblock3"
+
diff --git a/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c b/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c
new file mode 100644
index 0000000000..3a88cd68c7
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c
@@ -0,0 +1,124 @@
+/*
+ * (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This file is part of barebox.
+ *
+ * barebox is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * barebox is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *  @brief This file contains high-level init functions.
+ *
+ */
+#include <common.h>
+#include <reloc.h>
+#include <config.h>
+#include <mach/mcf54xx-regs.h>
+
+static void board_gpio_init(void)
+{
+	/*
+	 * Enable Ethernet signals so that, if a cable is plugged into
+	 * the ports, the lines won't be floating and potentially cause
+	 * erroneous transmissions
+	 */
+	MCF_GPIO_PAR_FECI2CIRQ = 0
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII
+	                         | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07;
+}
+
+
+static void board_psc_init(void)
+{
+#if (CFG_EARLY_UART_PORT == 0)
+	MCF_GPIO_PAR_PSC0 = (0
+#ifdef HARDWARE_FLOW_CONTROL
+	                     | MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS
+	                     | MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS
+#endif
+	                     | MCF_GPIO_PAR_PSC0_PAR_TXD0
+	                     | MCF_GPIO_PAR_PSC0_PAR_RXD0);
+#elif (CFG_EARLY_UART_PORT == 1)
+	MCF_GPIO_PAR_PSC1 = (0
+#ifdef HARDWARE_FLOW_CONTROL
+	                     | MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS
+	                     | MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS
+#endif
+	                     | MCF_GPIO_PAR_PSC1_PAR_TXD1
+	                     | MCF_GPIO_PAR_PSC1_PAR_RXD1);
+#elif (CFG_EARLY_UART_PORT == 2)
+	MCF_GPIO_PAR_PSC2 = (0
+#ifdef HARDWARE_FLOW_CONTROL
+	                     | MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS
+	                     | MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS
+#endif
+	                     | MCF_GPIO_PAR_PSC2_PAR_TXD2
+	                     | MCF_GPIO_PAR_PSC2_PAR_RXD2);
+#elif (CFG_EARLY_UART_PORT == 3)
+	MCF_GPIO_PAR_PSC3 = (0
+#ifdef HARDWARE_FLOW_CONTROL
+	                     | MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS
+	                     | MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS
+#endif
+	                     | MCF_GPIO_PAR_PSC3_PAR_TXD3
+	                     | MCF_GPIO_PAR_PSC3_PAR_RXD3);
+#else
+#error "Invalid CFG_EARLY_UART_PORT setting"
+#endif
+
+	/* Put PSC in UART mode */
+	MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART;
+
+	/* Call generic UART initialization */
+//    mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud());
+}
+
+
+/** Do board specific early init
+ *
+ * @note We run at link address now, you can now call other code
+ */
+void board_init_highlevel(void)
+{
+	/* Initialize platform specific GPIOs */
+	board_gpio_init();
+
+	/* Init UART GPIOs and Modes */
+	board_psc_init();
+
+	/* Setup the early init data */
+#ifdef CONFIG_HAS_EARLY_INIT
+	early_init();
+#endif
+	/* Configure the early debug output facility */
+#ifdef CONFIG_DEBUG_LL
+	early_debug_init();
+#endif
+}
+
+/** Provide address of early debug low-level output
+ *
+ * @todo Should return real address for UART register map.
+ */
+void *get_early_console_base(const char *name)
+{
+	return (void*)1 + CFG_EARLY_UART_PORT;
+}
diff --git a/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c b/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c
new file mode 100644
index 0000000000..2837e3ed67
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c
@@ -0,0 +1,194 @@
+/*
+ * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This file is part of barebox.
+ *
+ * barebox is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * barebox is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *  @brief This file contains ...
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <mach/mcf54xx-regs.h>
+
+/** Initialize board specific very early inits
+ *
+ * @note This code is not allowed to call other code - just init
+ * your Chipselects and SDRAM stuff here!
+ */
+void board_init_lowlevel(void)
+{
+	/*
+	 * The phyCORE-MCF548x has a 32MB or 64MB boot flash.
+	 * The is a CF Card and ControlRegs on CS1 and CS2
+	 */
+
+	/* Setup SysGlue Chip-Select for user IOs */
+	MCF_FBCS_CSAR2 = MCF_FBCS_CSAR_BA(CFG_XPLD_ADDRESS);
+
+	MCF_FBCS_CSCR2 = (MCF_FBCS_CSCR_PS_16
+	                  | MCF_FBCS_CSCR_AA
+	                  | MCF_FBCS_CSCR_ASET(1)
+	                  | MCF_FBCS_CSCR_WS(CFG_XPLD_WAIT_STATES));
+
+	MCF_FBCS_CSMR2 = (MCF_FBCS_CSMR_BAM_16M
+	                  | MCF_FBCS_CSMR_V);
+
+	/* Setup SysGlue Chip-Select for CFCARD */
+	MCF_FBCS_CSAR1 = MCF_FBCS_CSAR_BA(CFG_CFCARD_ADDRESS);
+
+	MCF_FBCS_CSCR1 = (MCF_FBCS_CSCR_PS_16
+	                  | MCF_FBCS_CSCR_AA
+	                  | MCF_FBCS_CSCR_ASET(1)
+	                  | MCF_FBCS_CSCR_WS(CFG_CFCARD_WAIT_STATES));
+
+	MCF_FBCS_CSMR1 = (MCF_FBCS_CSMR_BAM_16M
+	                  | MCF_FBCS_CSMR_V);
+
+	/* Setup boot flash chip-select */
+	MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS);
+
+	MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32
+	                  | MCF_FBCS_CSCR_AA
+	                  | MCF_FBCS_CSCR_ASET(1)
+	                  | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES));
+
+	MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M
+	                  | MCF_FBCS_CSMR_V);
+
+	/*
+	* Check to see if the SDRAM has already been initialized
+	* by a run control tool
+	*/
+	if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
+	{
+		/*
+		* Basic configuration and initialization
+		*/
+		// 0x000002AA
+		MCF_SDRAMC_SDRAMDS = (0
+		                      | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+		                      | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+		                      | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+		                      | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+		                      | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA)
+		                     );
+
+		// 0x0000001A
+		MCF_SDRAMC_CS0CFG = (0
+		                     | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS)
+		                     | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE)
+		                    );
+
+		MCF_SDRAMC_CS1CFG = 0;
+		MCF_SDRAMC_CS2CFG = 0;
+		MCF_SDRAMC_CS3CFG = 0;
+
+		// 0x73611730
+		MCF_SDRAMC_SDCFG1 = (0
+		                     | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5))
+		                     | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1))
+		                     | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2))
+		                     | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
+		                     | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
+		                     | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5))
+		                     | MCF_SDRAMC_SDCFG1_WTLAT(3)
+		                    );
+
+		// 0x46770000
+		MCF_SDRAMC_SDCFG2 = (0
+		                     | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2)
+		                     | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR)
+		                     | MCF_SDRAMC_SDCFG2_BRD2WT(7)
+		                     | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1)
+		                    );
+
+		/*
+		* Precharge and enable write to SDMR
+		*/
+		// 0xE10B0002
+		MCF_SDRAMC_SDCR = (0
+		                   | MCF_SDRAMC_SDCR_MODE_EN
+		                   | MCF_SDRAMC_SDCR_CKE
+		                   | MCF_SDRAMC_SDCR_DDR
+		                   | MCF_SDRAMC_SDCR_MUX(1)    // 13 x 10 x 2 ==> MUX=1
+		                   | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5))
+		                   | MCF_SDRAMC_SDCR_IPALL
+		                  );
+
+		/*
+		* Write extended mode register
+		*/
+		// 0x40010000
+		MCF_SDRAMC_SDMR = (0
+		                   | MCF_SDRAMC_SDMR_BNKAD_LEMR
+		                   | MCF_SDRAMC_SDMR_AD(0x0)
+		                   | MCF_SDRAMC_SDMR_CMD
+		                  );
+
+		/*
+		* Write mode register and reset DLL
+		*/
+		// 0x048d0000
+		MCF_SDRAMC_SDMR = (0
+		                   | MCF_SDRAMC_SDMR_BNKAD_LMR
+		                   | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD)
+		                   | MCF_SDRAMC_SDMR_CMD
+		                  );
+
+		/*
+		* Execute a PALL command
+		*/
+		// 0xE10B0002
+		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
+
+		/*
+		* Perform two REF cycles
+		*/
+		// 0xE10B0004
+		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
+
+		/*
+		* Write mode register and clear reset DLL
+		*/
+		// 0x008D0000
+		MCF_SDRAMC_SDMR = (0
+		                   | MCF_SDRAMC_SDMR_BNKAD_LMR
+		                   | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD)
+		                   | MCF_SDRAMC_SDMR_CMD
+		                  );
+
+		/*
+		* Enable auto refresh and lock SDMR
+		*/
+		// 0x610B0000
+		MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
+
+		// 0x710B0F00
+		MCF_SDRAMC_SDCR |= (0
+		                    | MCF_SDRAMC_SDCR_REF
+		                    | MCF_SDRAMC_SDCR_DQS_OE(0xF)
+		                   );
+	}
+}
+
+/** @file
+ *
+ * Target specific early chipselect and SDRAM init.
+ */
\ No newline at end of file
diff --git a/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c b/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c
new file mode 100644
index 0000000000..b7ab7c7d72
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c
@@ -0,0 +1,41 @@
+/*
+ * (C) 2007,2008 Carsten Schlote <schlote@vahanus.net>
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This file is part of barebox.
+ *
+ * barebox is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * barebox is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with barebox.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *  @brief This file contains callbacks for the PCI subsystem
+ *
+ */
+#include <common.h>
+#include <config.h>
+
+
+/** Returns mapping from PCI slot to CPU irq for the target board
+ * @return Coldfire IRQ vector number, or -1 for no irq
+ */
+int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin)
+{
+	int rc = -1;
+	switch (slot)
+	{
+	case 16        :  break;
+	case 17 ... 21 :  rc = 64 + 7; break;    // Eport IRQ7
+	}
+	return rc;
+}
diff --git a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c
new file mode 100644
index 0000000000..3bc2d12a42
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c
@@ -0,0 +1,134 @@
+/*
+ * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de>
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This file is part of barebox.
+ *
+ * barebox is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * barebox is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with barebox. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/** @file
+ *  @brief This file contains ...
+ *
+ */
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <fec.h>
+#include <environment.h>
+#include <mach/mcf54xx-regs.h>
+#include <mach/clocks.h>
+#include <asm/io.h>
+#include <partition.h>
+
+/*
+ *  Return board clock in MHz    FIXME move to clocks file
+ */
+ulong mcfv4e_get_bus_clk(void)
+{
+	return CFG_SYSTEM_CORE_CLOCK;
+}
+
+/*
+ * Up to 64MiB NOR type flash, connected to
+ * CS line 0, data width is 32 bit
+ */
+static struct device_d cfi_dev =
+{
+	.name     = "cfi_flash",
+	.map_base = CFG_FLASH_ADDRESS,
+	.size     = CFG_FLASH_SIZE,
+};
+
+/*
+ * Build in FastEthernetControllers (FECs)
+ */
+static struct fec_platform_data fec_info =
+{
+	.xcv_type = MII100,
+};
+
+static struct device_d network_dev0 =
+{
+	.name     = "fec_mcf54xx",
+	.map_base = MCF_FEC_ADDR(0),
+	.size     = MCF_FEC_SIZE(0),	   /* area size */
+	.platform_data	= &fec_info,
+};
+static struct device_d network_dev1 =
+{
+	.name     = "fec_mcf54xx",
+	.map_base = MCF_FEC_ADDR(1),
+	.size     = MCF_FEC_SIZE(1),	   /* area size */
+	.platform_data	= &fec_info,
+};
+
+/*
+ * 128MiB of SDRAM, data width is 32 bit
+ */
+static struct memory_platform_data ram_pdata = {
+	.name = "ram0",
+	.flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev =
+{
+	.name     = "mem",
+	.map_base = CFG_SDRAM_ADDRESS,
+	.size     = CFG_SDRAM_SIZE,
+	.platform_data = &ram_pdata,
+};
+
+static int mcfv4e_devices_init(void)
+{
+	printf("FIXME - setup board devices...\n");
+
+	register_device(&cfi_dev);
+
+	/*
+	 * Create partitions that should be
+	 * not touched by any regular user
+	 */
+	devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0");	/* ourself */
+	devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0");	/* environment */
+	protect_file("/dev/env0", 1);
+
+	register_device(&network_dev0);
+	//register_device(&network_dev1);
+
+	register_device(&sdram_dev);
+
+	return 0;
+}
+
+device_initcall(mcfv4e_devices_init);
+
+static struct device_d mcfv4e_serial_device =
+{
+	.name     = "mcfv4e_serial",
+	.map_base = 1 + CFG_EARLY_UART_PORT,
+	.size     = 16 * 1024,
+};
+
+static int mcfv4e_console_init(void)
+{
+	/* init gpios for serial port */
+
+	/* Already set in lowlevel_init.c */
+
+	register_device(&mcfv4e_serial_device);
+	return 0;
+}
+
+console_initcall(mcfv4e_console_init);
diff --git a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox
new file mode 100644
index 0000000000..36dd0ad195
--- /dev/null
+++ b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox
@@ -0,0 +1,14 @@
+
+/** @page phycore_mcf54xx Phytec's phyCORE-MCF54x5
+
+This target is based on a PhyTec PhyCore MCF54x5 CPU module. The card is shipped with:
+
+- up to 64MiB NOR type Flash Memory
+- 128MiB synchronous dynamic RAM
+- PCI USB 2.0 Host
+- PCCard Controller
+- MiniPCI Parallel
+- MiniPCIe (USB lane only)
+- ...
+
+*/
diff --git a/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig b/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig
index ba21a008d3..bb91152210 100644
--- a/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig
+++ b/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig
@@ -71,7 +71,7 @@ CONFIG_EARLY_CONSOLE_PORT="psc0"
 CONFIG_EARLY_CONSOLE_BAUDRATE=115200
 # CONFIG_OF_FLAT_TREE is not set
 CONFIG_DEFAULT_ENVIRONMENT=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="board/kp_ukd_r1_num/env/"
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/kp_ukd_r1_num/env/"
 
 #
 # Debugging
diff --git a/arch/m68k/configs/phycore_mcf54xx_defconfig b/arch/m68k/configs/phycore_mcf54xx_defconfig
index 34ca73ffc7..f64ca8b022 100644
--- a/arch/m68k/configs/phycore_mcf54xx_defconfig
+++ b/arch/m68k/configs/phycore_mcf54xx_defconfig
@@ -71,7 +71,7 @@ CONFIG_EARLY_CONSOLE_PORT="psc0"
 CONFIG_EARLY_CONSOLE_BAUDRATE=115200
 # CONFIG_OF_FLAT_TREE is not set
 CONFIG_DEFAULT_ENVIRONMENT=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="board/phycore_mcf54xx/env"
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/phycore_mcf54xx/env"
 
 #
 # Debugging