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| author | Antony Pavlov <antonynpavlov@gmail.com> | 2013-10-26 13:15:06 +0400 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-10-28 09:01:48 +0100 |
| commit | 7b29868f3e4d5dbea8dfe2a2ab417301859a8f9a (patch) | |
| tree | 4b1f440f22e36f8817628734a890c3d2fea66e2f /arch/mips/boards | |
| parent | 0ac73f13265ae1f04b58b8e4eab10fbbfb3f30b4 (diff) | |
| download | barebox-7b29868f3e4d5dbea8dfe2a2ab417301859a8f9a.tar.gz barebox-7b29868f3e4d5dbea8dfe2a2ab417301859a8f9a.tar.xz | |
MIPS: qemu-malta: use YAMON-style GT64120 memory map
There are some reasons for using YAMON-style memory map:
* we can run Linux kernel from barebox;
* we can use GXemul for running barebox.
YAMON-style GT64120 memory map make move UART to the new position.
The files gt64120.h and mach-gt64120.h are imported from Linux.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/boards')
| -rw-r--r-- | arch/mips/boards/qemu-malta/include/board/board_pbl_start.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h b/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h index a5f29e54a1..5c1537262e 100644 --- a/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h +++ b/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h @@ -20,6 +20,25 @@ #include <asm/pbl_macros.h> #include <asm/pbl_nmon.h> +#include <asm/addrspace.h> +#include <asm/gt64120.h> +#include <mach/mach-gt64120.h> + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define GT_CPU_TO_LE32(x) (x) +#elif defined CONFIG_CPU_BIG_ENDIAN +#define GT_CPU_TO_LE32(x) ( \ + (((x) & 0x000000ff) << 24) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0xff000000) >> 24)) +#else +#error "could not determine byte order" +#endif + +#define GT_LD(x) (GT_CPU_TO_LE32(((x) >> 21) & 0x7fff)) +#define GT_HD(x) (GT_CPU_TO_LE32(((x) >> 21) & 0x7f)) + .macro board_pbl_start .set push .set noreorder @@ -41,6 +60,40 @@ __start: /* cpu specific setup ... */ /* ... absent */ + /* + * Load BAR registers of GT64120 as done by YAMON + * + * based on write_bootloader() in qemu.git/hw/mips/mips_malta.c + * see GT64120 manual and qemu.git/hw/mips/gt64xxx_pci.c for details + */ + + /* move GT64120 registers to 0x1be00000 */ + li t1, KSEG1ADDR(GT_DEF_BASE) + li t0, GT_LD(MIPS_GT_BASE) + sw t0, GT_ISD_OFS(t1) + + /* + * setup MEM-to-PCI0 mapping + */ + li t1, KSEG1ADDR(MIPS_GT_BASE) + + /* setup PCI0 io window */ + li t0, GT_LD(0x18000000) + sw t0, GT_PCI0IOLD_OFS(t1) + li t0, GT_HD(0x181fffff) + sw t0, GT_PCI0IOHD_OFS(t1) + + /* setup PCI0 mem windows */ + li t0, GT_LD(0x10000000) + sw t0, GT_PCI0M0LD_OFS(t1) + li t0, GT_HD(0x17efffff) + sw t0, GT_PCI0M0HD_OFS(t1) + + li t0, GT_LD(0x18200000) + sw t0, GT_PCI0M1LD_OFS(t1) + li t0, GT_LD(0x1bdfffff) + sw t0, GT_PCI0M1HD_OFS(t1) + mips_nmon copy_to_link_location pbl_start |