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authorAntony Pavlov <antonynpavlov@gmail.com>2015-11-10 10:27:14 +0300
committerSascha Hauer <s.hauer@pengutronix.de>2015-11-11 08:38:24 +0100
commit643c5d87dd8b3f66ee133486a75bdd25d9f34ce1 (patch)
tree4491cd4765c48441de0224c715b04d8361b49e6a /arch/mips/include
parentb6e9c2ae14275d48a854488ed69ba763ee021459 (diff)
downloadbarebox-643c5d87dd8b3f66ee133486a75bdd25d9f34ce1.tar.gz
barebox-643c5d87dd8b3f66ee133486a75bdd25d9f34ce1.tar.xz
MIPS: avoid excessive exception
This commit clears ERL (ERror Level) flag on start. If this flag is set then we get 'TLB miss on load or ifetch' just after return from exception. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/include')
-rw-r--r--arch/mips/include/asm/pbl_macros.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index 681b40a305..c4ae6a2417 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -145,7 +145,7 @@ copy_loop_exit:
.set push
.set noreorder
mfc0 k0, CP0_STATUS
- li k1, ~ST0_IE
+ li k1, ~(ST0_ERL | ST0_IE)
and k0, k1
mtc0 k0, CP0_STATUS
.set pop