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| author | Antony Pavlov <antonynpavlov@gmail.com> | 2016-03-07 16:30:16 +0300 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-03-09 19:58:50 +0100 |
| commit | e3fbe5e85d24a63f8c46d486b60ebb15cfcad541 (patch) | |
| tree | a3fd0a4f40e0aafa6138cda5aeb3d489467b3c28 /arch/mips/lib/c-r4k.c | |
| parent | 6d352cacb8dca98a9afefc42d4e0fec7e8aa2509 (diff) | |
| download | barebox-e3fbe5e85d24a63f8c46d486b60ebb15cfcad541.tar.gz barebox-e3fbe5e85d24a63f8c46d486b60ebb15cfcad541.tar.xz | |
MIPS: add initial R4000-style cache support
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/lib/c-r4k.c')
| -rw-r--r-- | arch/mips/lib/c-r4k.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c index ff686770e1..ba77d18e7c 100644 --- a/arch/mips/lib/c-r4k.c +++ b/arch/mips/lib/c-r4k.c @@ -10,10 +10,57 @@ #include <common.h> #include <asm/io.h> #include <asm/mipsregs.h> +#include <asm/cacheops.h> #include <asm/cpu.h> #include <asm/cpu-info.h> #include <asm/bitops.h> +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop) \ +static inline void blast_##pfx##cache##_range(unsigned long start, \ + unsigned long end) \ +{ \ + unsigned long lsize = current_cpu_data.desc.linesz; \ + unsigned long addr = start & ~(lsize - 1); \ + unsigned long aend = (end - 1) & ~(lsize - 1); \ + \ + if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT) \ + return; \ + \ + while (1) { \ + cache_op(hitop, addr); \ + if (addr == aend) \ + break; \ + addr += lsize; \ + } \ +} + +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D) +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D) + +void dma_flush_range(unsigned long start, unsigned long end) +{ + blast_dcache_range(start, end); + + /* secondatory cache skipped */ +} + +void dma_inv_range(unsigned long start, unsigned long end) +{ + blast_inv_dcache_range(start, end); + + /* secondatory cache skipped */ +} + void r4k_cache_init(void); static void probe_pcache(void) |