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author | Antony Pavlov <antonynpavlov@gmail.com> | 2014-07-31 19:11:31 +0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-08-01 07:35:51 +0200 |
commit | b549a26fc3088b85602caf412bebd16f9e3e8ae9 (patch) | |
tree | a666349865908ca96ec3665266155f759f53a7dc /arch/mips/mach-xburst | |
parent | 03a2269509e5107f88c04c6bdde4ec692ba97a9a (diff) | |
download | barebox-b549a26fc3088b85602caf412bebd16f9e3e8ae9.tar.gz barebox-b549a26fc3088b85602caf412bebd16f9e3e8ae9.tar.xz |
watchdog: add minimal jz4740 driver
Also move reset_cpu() for jz4755 SoC from platform code
into the new driver code.
At the moment mach-xburst lacks clk support so jz4740 watchdog
driver looks like a template. We can improve jz4740 watchdog
driver later after adding clk support.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/mach-xburst')
-rw-r--r-- | arch/mips/mach-xburst/Kconfig | 2 | ||||
-rw-r--r-- | arch/mips/mach-xburst/include/mach/jz4750d_regs.h | 22 | ||||
-rw-r--r-- | arch/mips/mach-xburst/reset-jz4750.c | 18 |
3 files changed, 2 insertions, 40 deletions
diff --git a/arch/mips/mach-xburst/Kconfig b/arch/mips/mach-xburst/Kconfig index 706d59249b..f7b8470cb8 100644 --- a/arch/mips/mach-xburst/Kconfig +++ b/arch/mips/mach-xburst/Kconfig @@ -6,6 +6,8 @@ config ARCH_TEXT_BASE config CPU_JZ4755 bool + select WATCHDOG + select WATCHDOG_JZ4740 choice prompt "Board type" diff --git a/arch/mips/mach-xburst/include/mach/jz4750d_regs.h b/arch/mips/mach-xburst/include/mach/jz4750d_regs.h index 7a3daadb18..396c823a1f 100644 --- a/arch/mips/mach-xburst/include/mach/jz4750d_regs.h +++ b/arch/mips/mach-xburst/include/mach/jz4750d_regs.h @@ -59,28 +59,6 @@ #define TCU_OSTCSR_PCK_EN (1 << 0) /* select pclk as the timer clock input */ /************************************************************************* - * WDT (WatchDog Timer) - *************************************************************************/ -#define WDT_TDR (WDT_BASE + 0x00) -#define WDT_TCER (WDT_BASE + 0x04) -#define WDT_TCNT (WDT_BASE + 0x08) -#define WDT_TCSR (WDT_BASE + 0x0c) - -#define WDT_TCSR_PRESCALE_BIT 3 -#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) - #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) -#define WDT_TCSR_EXT_EN (1 << 2) -#define WDT_TCSR_RTC_EN (1 << 1) -#define WDT_TCSR_PCK_EN (1 << 0) - -#define WDT_TCER_TCEN (1 << 0) - -/************************************************************************* * RTC *************************************************************************/ #define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ diff --git a/arch/mips/mach-xburst/reset-jz4750.c b/arch/mips/mach-xburst/reset-jz4750.c index 8f33672280..25830f130e 100644 --- a/arch/mips/mach-xburst/reset-jz4750.c +++ b/arch/mips/mach-xburst/reset-jz4750.c @@ -24,8 +24,6 @@ #include <io.h> #include <mach/jz4750d_regs.h> -#define JZ_EXTAL 24000000 - static void __noreturn jz4750d_halt(void) { while (1) { @@ -39,22 +37,6 @@ static void __noreturn jz4750d_halt(void) unreachable(); } -void __noreturn reset_cpu(ulong addr) -{ - __raw_writew(WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN, (u16 *)WDT_TCSR); - __raw_writew(0, (u16 *)WDT_TCNT); - - /* reset after 4ms */ - __raw_writew(JZ_EXTAL / 1000, (u16 *)WDT_TDR); - /* enable wdt clock */ - __raw_writel(TCU_TSCR_WDTSC, (u32 *)TCU_TSCR); - /* start wdt */ - __raw_writeb(WDT_TCER_TCEN, (u8 *)WDT_TCER); - - unreachable(); -} -EXPORT_SYMBOL(reset_cpu); - void __noreturn poweroff() { u32 ctrl; |