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author | Antony Pavlov <antonynpavlov@gmail.com> | 2011-08-05 14:58:35 +0400 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-08-05 18:20:17 +0200 |
commit | 645d26aca3348c8e0fd3c764ce17dab29bd22584 (patch) | |
tree | 06691e75a089b11abfeed5fd6030ff88e2cfb75f /arch/mips | |
parent | d3f66272bf53ae33123e9af0b809e425b932d5f9 (diff) | |
download | barebox-645d26aca3348c8e0fd3c764ce17dab29bd22584.tar.gz barebox-645d26aca3348c8e0fd3c764ce17dab29bd22584.tar.xz |
MIPS: add documentation
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/mach-mips.dox | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/arch/mips/mach-mips.dox b/arch/mips/mach-mips.dox new file mode 100644 index 0000000000..018fc4483c --- /dev/null +++ b/arch/mips/mach-mips.dox @@ -0,0 +1,54 @@ +/* This document is intended to provide the developer with information + * how to integrate a new CPU (MACH) into this part of the barebox tree + */ + +/** @page dev_mips_mach MIPS based CPU (MACH) into the tree + +@section mach_mips_reset What's happens when the reset signal is gone + +Barebox normally must be linked to RAM region, cached region KSEG0 is preferred. +This make possible to run fast (because cache used) and skip MMU support. + +After reset MIPS CPU starting to fetch instructions from 0xBFC00000. + +@note Code running immediately after reset runs at an address it is not linked + to: "runtime address != link address". You should only use branches and + do not refer to fixed data. This implies the use of assembler code only. + After MIPS CPU reset cache and MMU are in random state. They are unusable. + +barebox MIPS initialisation sequence: + + * set the CP0 STATUS register to some known and sensible state. +Now you can load and store reliably in uncached space. + + * call a function \<mach_init_lowlevel\> (if not disabled). +do some special things required only on specific CPU + (e. g. init RAM controller, disable watchdog) + + * call a function \<board_init_lowlevel\> (if not disable). +do some special things required only on specific board + (e. g. setup GPIO to required state). + + ** It is desirable to have some debug code to make some contact + with the outside world from assembler code +(e.g. debug_ll-like functions to write to rs232 console). + + * check integrity of barebox RAM execute location; + * copy barebox to RAM execute location; + + * configure cache; + + * setup stack; + + ** after this point you can call a standard C routine. + + * setup exception vectors in RAM; + * setup CP0 STATUS to switch exception vector address to RAM; + + * call start_barebox() + +Further reading: + * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006 +ISBN-13: 978-0120884216 + +*/ |