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author | Denis Orlov <denorl2009@gmail.com> | 2023-03-13 13:53:07 +0300 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-03-14 09:51:31 +0100 |
commit | b5117dbfc62ebdcb07036d52bd7227801f6f5aa1 (patch) | |
tree | c7cb868314ab79b1c45cd66705553f6e5d3145d7 /arch/mips | |
parent | d13d870986eeecc58d8652268557e4a159b9d4c4 (diff) | |
download | barebox-b5117dbfc62ebdcb07036d52bd7227801f6f5aa1.tar.gz barebox-b5117dbfc62ebdcb07036d52bd7227801f6f5aa1.tar.xz |
MIPS: dma-default: use virtual addresses when flushing caches
Cache flushing functions expect virtual addresses, so make sure those
are properly converted from the physical ones in dma_sync_single_for_*.
QEMU doesn't care as it ignores cache instructions, but without such
change this code would result in TLB exceptions on real hardware.
Signed-off-by: Denis Orlov <denorl2009@gmail.com>
Link: https://lore.barebox.org/20230313105308.3108127-3-denorl2009@gmail.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/lib/dma-default.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c index 48176e5d28..f6c750b8ac 100644 --- a/arch/mips/lib/dma-default.c +++ b/arch/mips/lib/dma-default.c @@ -30,11 +30,15 @@ static inline void __dma_sync_mips(unsigned long addr, size_t size, void dma_sync_single_for_cpu(dma_addr_t address, size_t size, enum dma_data_direction dir) { - __dma_sync_mips(address, size, dir); + unsigned long virt = (unsigned long)phys_to_virt(address); + + __dma_sync_mips(virt, size, dir); } void dma_sync_single_for_device(dma_addr_t address, size_t size, enum dma_data_direction dir) { - __dma_sync_mips(address, size, dir); + unsigned long virt = (unsigned long)phys_to_virt(address); + + __dma_sync_mips(virt, size, dir); } |