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| author | Antony Pavlov <antonynpavlov@gmail.com> | 2014-09-10 11:42:21 +0400 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-09-11 07:59:45 +0200 |
| commit | c36205f4ba027c8b801d07140adf5ea8cb34da08 (patch) | |
| tree | 8ab71fce606551501d775687f7510b6b346461cf /arch/mips | |
| parent | 29158c114b47d51061319bcf251dac938dbff51d (diff) | |
| download | barebox-c36205f4ba027c8b801d07140adf5ea8cb34da08.tar.gz barebox-c36205f4ba027c8b801d07140adf5ea8cb34da08.tar.xz | |
MIPS: add (another) Ingenic vendor ID
The latest Ingenic CPUs (e.g. JZ4780) use new vendor ID.
Based on commit from https://github.com/MIPS/CI20_linux/tree/ci20-v3.16
commit 00b672aa52f299f1d67ab18274c3f5e5d5a15767
Author: Paul Burton <paul.burton@imgtec.com>
Date: Mon Jul 8 12:14:28 2013 +0100
MIPS: add (another) Ingenic vendor ID
Ingenic have switched to a new vendor ID for the Xburst core used in
their current SoCs such as the jz4780. Add this vendor ID and handle it
in addition to their former vendor ID.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/cpu.h | 1 | ||||
| -rw-r--r-- | arch/mips/lib/cpu-probe.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index dcc2a27a97..572cabba34 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -27,6 +27,7 @@ #define PRID_COMP_MIPS 0x010000 #define PRID_COMP_BROADCOM 0x020000 #define PRID_COMP_INGENIC 0xd00000 +#define PRID_COMP_INGENIC2 0xe10000 /* * Assigned Processor ID (implementation) values for bits 15:8 of the PRId diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c index 8235a54ae7..4622bcdd61 100644 --- a/arch/mips/lib/cpu-probe.c +++ b/arch/mips/lib/cpu-probe.c @@ -158,6 +158,7 @@ void cpu_probe(void) cpu_probe_broadcom(c); break; case PRID_COMP_INGENIC: + case PRID_COMP_INGENIC2: cpu_probe_ingenic(c); break; } |