x86: add DMA support

Both interconnect and PCI are cache coherent on x86, so we shouldn't
need any special CPU barriers for DMA. Indeed, Linux defined neither
ARCH_HAS_SYNC_DMA_FOR_CPU nor ARCH_HAS_SYNC_DMA_FOR_DEVICE on x86.

It thus seems that the only reordering we need to take care of is
compiler-induced reordering. The Linux memory model that barebox adheres
to as well demands that all accesses to shared data are volatile.

volatile accesses are already guarnateed to not be reordered against
each other, so we don't even need an explicit barrier(), which is
already the case on other architectures that have a disabled MMU.

Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
Link: https://lore.barebox.org/20210416062436.332665-2-ahmad@a3f.at
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

0 files changed, 0 insertions, 0 deletions