Add OpenRISC arch

OpenRISC is the original flagship project of the OpenCores community.
This project aims to develop a series of general purpose open source
RISC CPU architectures.

A team from OpenCores provided the first implementation, the OpenRISC
1200, written in the Verilog hardware description language.

Even though I should have created an mach-or1200 directory, it is not
necessary for now. The OpenRISC 1200 CPU is the only one available and
it will be for some time.

Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

7 files changed, 394 insertions, 0 deletions

diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
new file mode 100644
index 0000000000..aaf93cbd20
--- /dev/null
+++ b/arch/openrisc/lib/Makefile
@@ -0,0 +1,6 @@
+obj-y                 += clock.o
+obj-y                 += board.o
+obj-y                 += cpuinfo.o
+obj-y                 += muldi3.o
+obj-y                 += lshrdi3.o
+obj-y                 += ashldi3.o
diff --git a/arch/openrisc/lib/ashldi3.S b/arch/openrisc/lib/ashldi3.S
new file mode 100644
index 0000000000..3e422fadc4
--- /dev/null
+++ b/arch/openrisc/lib/ashldi3.S
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2011 - Franck JULLIEN <elec4fun@gmail.com>
+ *
+ * Extracted from gcc generated assembly.
+ *
+ * Extended precision shifts.
+ *
+ * R3/R4 (MSW, LSW) has 64 bit value
+ * R5    has shift count
+ * result in R11/R12
+ *
+ */
+
+.globl __ashldi3
+
+__ashldi3:
+	l.sfeqi r5,0x0
+	l.bf out		/* if count = 0, go out                   */
+
+	l.addi r6,r0,0x20	/* r6 = 32                                */
+	l.sub r6,r6,r5		/* r6 = 32 - count                        */
+	l.sfgtsi r6,0x0		/* if count >= 32                         */
+	l.bnf more_than_32	/* branch to more_than_32                 */
+	l.nop 0x0
+
+less_than_32:
+	l.srl r6,r4,r6		/* r6 gets the bits moved from LSW to MSW */
+	l.sll r3,r3,r5		/* shift MSW                              */
+	l.sll r4,r4,r5		/* shift LSW                              */
+	l.or r3,r6,r3		/* MSW gets bits shifted from LSW         */
+
+out:
+	l.ori r11,r3,0x0
+	l.jr r9
+	l.ori r12,r4,0x0
+
+more_than_32:
+	l.sub r3,r0,r6		/* r3 = -r6, the number of bits above 32  */
+	l.sll r3,r4,r3		/* MSW = LSW << r3                        */
+	l.j out			/* go out                                 */
+	l.addi r4,r0,0x0	/* LSW = 0                                */
diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c
new file mode 100644
index 0000000000..a2158cb0c0
--- /dev/null
+++ b/arch/openrisc/lib/board.c
@@ -0,0 +1,42 @@
+/*
+ * (C) Copyright 2011 - Franck JULLIEN <elec4fun@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <init.h>
+#include <memory.h>
+#include <asm-generic/memory_layout.h>
+
+int openrisc_mem_malloc_init(void)
+{
+
+	mem_malloc_init((void *)(OPENRISC_SOPC_TEXT_BASE - MALLOC_SIZE),
+			(void *)(OPENRISC_SOPC_TEXT_BASE - 1));
+
+	return 0;
+}
+
+core_initcall(openrisc_mem_malloc_init);
+
+void arch_shutdown(void)
+{
+}
diff --git a/arch/openrisc/lib/clock.c b/arch/openrisc/lib/clock.c
new file mode 100644
index 0000000000..ab0a90d4dc
--- /dev/null
+++ b/arch/openrisc/lib/clock.c
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2011 - Franck JULLIEN <elec4fun@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <init.h>
+#include <asm/system.h>
+#include <asm/openrisc_exc.h>
+
+static uint64_t openrisc_clocksource_read(void)
+{
+	return (uint64_t)(mfspr(SPR_TTCR));
+}
+
+static struct clocksource cs = {
+	.read	= openrisc_clocksource_read,
+	.mask	= 0xffffffff,
+	.shift	= 12,
+};
+
+static int clocksource_init(void)
+{
+	mtspr(SPR_TTMR, SPR_TTMR_CR | 0xFFFFFF);
+	cs.mult = clocksource_hz2mult(OPENRISC_TIMER_FREQ, cs.shift);
+
+	init_clock(&cs);
+
+	return 0;
+}
+
+core_initcall(clocksource_init);
diff --git a/arch/openrisc/lib/cpuinfo.c b/arch/openrisc/lib/cpuinfo.c
new file mode 100644
index 0000000000..3ec44c1b9b
--- /dev/null
+++ b/arch/openrisc/lib/cpuinfo.c
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <asm/openrisc_exc.h>
+
+static volatile int illegal_instruction;
+
+static void illegal_instruction_handler(void)
+{
+	ulong *epcr = (ulong *)mfspr(SPR_EPCR_BASE);
+
+	/* skip over the illegal instruction */
+	mtspr(SPR_EPCR_BASE, (ulong)(++epcr));
+	illegal_instruction = 1;
+}
+
+static int checkinstructions(void)
+{
+	ulong ra = 1, rb = 1, rc;
+
+	exception_install_handler(EXC_ILLEGAL_INSTR,
+				illegal_instruction_handler);
+
+	illegal_instruction = 0;
+	asm volatile("l.mul %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
+	printf("           Hardware multiplier: %s\n",
+		illegal_instruction ? "no" : "yes");
+
+	illegal_instruction = 0;
+	asm volatile("l.div %0,%1,%2" : "=r" (rc) : "r" (ra), "r" (rb));
+	printf("           Hardware divider: %s\n",
+		illegal_instruction ? "no" : "yes");
+
+	exception_free_handler(EXC_ILLEGAL_INSTR);
+
+	return 0;
+}
+
+int checkcpu(void)
+{
+	ulong upr = mfspr(SPR_UPR);
+	ulong vr = mfspr(SPR_VR);
+	ulong iccfgr = mfspr(SPR_ICCFGR);
+	ulong dccfgr = mfspr(SPR_DCCFGR);
+	ulong immucfgr = mfspr(SPR_IMMUCFGR);
+	ulong dmmucfgr = mfspr(SPR_DMMUCFGR);
+	ulong cpucfgr = mfspr(SPR_CPUCFGR);
+	uint ver = (vr & SPR_VR_VER) >> 24;
+	uint rev = vr & SPR_VR_REV;
+	uint block_size;
+	uint ways;
+	uint sets;
+
+	printf("CPU:   OpenRISC-%x00 (rev %d) @ %d MHz\n",
+		ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000));
+
+	if (upr & SPR_UPR_DCP) {
+		block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
+		ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+		printf("       D-Cache: %d bytes, %d bytes/line, %d way(s)\n",
+		       checkdcache(), block_size, ways);
+	} else {
+		printf("       D-Cache: no\n");
+	}
+
+	if (upr & SPR_UPR_ICP) {
+		block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
+		ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+		printf("       I-Cache: %d bytes, %d bytes/line, %d way(s)\n",
+		       checkicache(), block_size, ways);
+	} else {
+		printf("       I-Cache: no\n");
+	}
+
+	if (upr & SPR_UPR_DMP) {
+		sets = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2);
+		ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1;
+		printf("       DMMU: %d sets, %d way(s)\n",
+		       sets, ways);
+	} else {
+		printf("       DMMU: no\n");
+	}
+
+	if (upr & SPR_UPR_IMP) {
+		sets = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2);
+		ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1;
+		printf("       IMMU: %d sets, %d way(s)\n",
+		       sets, ways);
+	} else {
+		printf("       IMMU: no\n");
+	}
+
+	printf("       MAC unit: %s\n",
+		(upr & SPR_UPR_MP) ? "yes" : "no");
+	printf("       Debug unit: %s\n",
+		(upr & SPR_UPR_DUP) ? "yes" : "no");
+	printf("       Performance counters: %s\n",
+		(upr & SPR_UPR_PCUP) ? "yes" : "no");
+	printf("       Power management: %s\n",
+		(upr & SPR_UPR_PMP) ? "yes" : "no");
+	printf("       Interrupt controller: %s\n",
+		(upr & SPR_UPR_PICP) ? "yes" : "no");
+	printf("       Timer: %s\n",
+		(upr & SPR_UPR_TTP) ? "yes" : "no");
+	printf("       Custom unit(s): %s\n",
+		(upr & SPR_UPR_CUP) ? "yes" : "no");
+
+	printf("       Supported instructions:\n");
+	printf("           ORBIS32: %s\n",
+		(cpucfgr & SPR_CPUCFGR_OB32S) ? "yes" : "no");
+	printf("           ORBIS64: %s\n",
+		(cpucfgr & SPR_CPUCFGR_OB64S) ? "yes" : "no");
+	printf("           ORFPX32: %s\n",
+		(cpucfgr & SPR_CPUCFGR_OF32S) ? "yes" : "no");
+	printf("           ORFPX64: %s\n",
+		(cpucfgr & SPR_CPUCFGR_OF64S) ? "yes" : "no");
+
+	checkinstructions();
+
+	return 0;
+}
+
+static int do_cpuinfo(struct command *cmdtp, int argc, char *argv[])
+{
+	checkcpu();
+	return 0;
+}
+
+BAREBOX_CMD_START(cpuinfo)
+	.cmd            = do_cpuinfo,
+	.usage          = "Show info about CPU",
+BAREBOX_CMD_END
diff --git a/arch/openrisc/lib/lshrdi3.S b/arch/openrisc/lib/lshrdi3.S
new file mode 100644
index 0000000000..de30445f4e
--- /dev/null
+++ b/arch/openrisc/lib/lshrdi3.S
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2011 - Franck JULLIEN <elec4fun@gmail.com>
+ *
+ * Extracted from gcc generated assembly.
+ *
+ * Extended precision shifts.
+ *
+ * R3/R4 (MSW, LSW) has 64 bit value
+ * R5    has shift count
+ * result in R11/R12
+ *
+ */
+
+.globl __lshrdi3
+
+__lshrdi3:
+	l.sfeqi r5,0x0
+	l.bf out		/* if count = 0, go out                   */
+
+	l.addi r6,r0,0x20	/* r6 = 32                                */
+	l.sub r6,r6,r5		/* r6 = 32 - count                        */
+	l.sfgtsi r6,0x0		/* if count >= 32                         */
+	l.bnf more_than_32	/* branch to more_than_32                 */
+	l.nop 0x0
+
+less_than_32:
+	l.sll r6,r3,r6		/* r6 gets the bits moved from MSW to LSW */
+	l.srl r4,r4,r5		/* shift LSW                              */
+	l.srl r3,r3,r5		/* shift MSW                              */
+	l.or r4,r6,r4		/* LSW gets bits shifted from MSW         */
+
+ out:
+	l.ori r11,r3,0x0
+	l.jr r9
+	l.ori r12,r4,0x0
+
+more_than_32:
+	l.sub r4,r0,r6		/* r4 = -r6, the number of bits above 32  */
+	l.srl r4,r3,r4		/* LSW = MSW >> r4                        */
+	l.j out			/* go out                                 */
+	l.addi r3,r0,0x0	/* MSW = 0                                */
diff --git a/arch/openrisc/lib/muldi3.S b/arch/openrisc/lib/muldi3.S
new file mode 100644
index 0000000000..902338a242
--- /dev/null
+++ b/arch/openrisc/lib/muldi3.S
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2011 - Franck JULLIEN <elec4fun@gmail.com>
+ *
+ * Extracted from gcc generated assembly.
+ *
+ * Multiply two quads. Hereafter, the illustration of what is going on :
+ *
+ *                        |    r3    |    r4    |
+ *                        |    r5    |    r6    |
+ *                         --------------------
+ *                        |       r4 * r6       |
+ *             |       r3 * r6       |          | +
+ *             |       r5 * r4       |          | +
+ *  |       r3 * r5       |          |          | +
+ *   -------------------------------------------  =
+ *                        |    64 bits result   |
+ *
+ */
+
+.globl __muldi3
+
+__muldi3:
+	/* starts with the full 64 bits mul (r4 * r6) */
+	l.andi r7,r4,0xffff
+	l.srli r8,r4,0x10
+
+	l.andi r11,r6,0xffff
+	l.srli r12,r6,0x10
+
+	l.mul r13,r11,r7
+	l.mul r11,r11,r8
+	l.mul r7,r12,r7
+
+	l.srli r15,r13,0x10
+	l.add r7,r7,r15
+	l.add r7,r11,r7
+	l.sfleu r11,r7
+	l.bf no_carry
+	l.mul r8,r12,r8
+
+	l.movhi r15,0x1
+	l.add r8,r8,r15
+
+no_carry:
+	/* Now compute r3 * r6  */
+	l.mul r6,r6,r3
+	/* and r4 * r5          */
+	l.mul r4,r4,r5
+	/* finaly previous results and put the result in r11:r12 */
+	l.srli r3,r7,0x10
+	l.slli r7,r7,0x10
+	l.andi r13,r13,0xffff
+	l.add r8,r8,r3
+	l.add r11,r4,r6
+	l.add r12,r7,r13
+	l.add r11,r11,r8
+	l.jr r9
+	l.nop