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| author | Franck Jullien <franck.jullien@gmail.com> | 2014-05-21 23:32:29 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-05-22 08:07:21 +0200 |
| commit | cf7b7603468e672fc81b327466dc6fd9cb1295e2 (patch) | |
| tree | 98989a004366b0145a7666911f7fc5169b08901d /arch/openrisc | |
| parent | 7911f5efdd039ac79902a636811b1cc1693a0941 (diff) | |
| download | barebox-cf7b7603468e672fc81b327466dc6fd9cb1295e2.tar.gz barebox-cf7b7603468e672fc81b327466dc6fd9cb1295e2.tar.xz | |
openrisc: update cpuinfo
Update cpuinfo to display the current CPU implementation
using the VR2 register defined in the architecture specification
v1.0
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/openrisc')
| -rw-r--r-- | arch/openrisc/lib/cpuinfo.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/openrisc/lib/cpuinfo.c b/arch/openrisc/lib/cpuinfo.c index 1f137f0cd4..9434b5ee8b 100644 --- a/arch/openrisc/lib/cpuinfo.c +++ b/arch/openrisc/lib/cpuinfo.c @@ -23,6 +23,13 @@ #include <asm/cache.h> #include <asm/openrisc_exc.h> +/* CPUID */ +#define OR1KSIM 0x00 +#define OR1200 0x12 +#define MOR1KX 0x01 +#define ALTOR32 0x32 +#define OR10 0x10 + static volatile int illegal_instruction; static void illegal_instruction_handler(void) @@ -56,10 +63,46 @@ static int checkinstructions(void) return 0; } +static void cpu_implementation(ulong vr2, char *string) +{ + switch (vr2 >> 24) { + + case OR1KSIM: + sprintf(string, "or1ksim"); + break; + case OR1200: + sprintf(string, "OR1200"); + break; + case MOR1KX: + sprintf(string, "mor1kx v%u.%u - ", (uint)((vr2 >> 16) & 0xff), + (uint)((vr2 >> 8) & 0xff)); + + if ((uint)(vr2 & 0xff) == 1) + strcat(string, "cappuccino"); + else if ((uint)(vr2 & 0xff) == 2) + strcat(string, "espresso"); + else if ((uint)(vr2 & 0xff) == 3) + strcat(string, "prontoespresso"); + else + strcat(string, "unknwown"); + + break; + case ALTOR32: + sprintf(string, "AltOr32"); + break; + case OR10: + sprintf(string, "OR10"); + break; + default: + sprintf(string, "unknown"); + } +} + int checkcpu(void) { ulong upr = mfspr(SPR_UPR); ulong vr = mfspr(SPR_VR); + ulong vr2 = mfspr(SPR_VR2); ulong iccfgr = mfspr(SPR_ICCFGR); ulong dccfgr = mfspr(SPR_DCCFGR); ulong immucfgr = mfspr(SPR_IMMUCFGR); @@ -71,9 +114,16 @@ int checkcpu(void) uint ways; uint sets; + char impl_str[50]; + printf("CPU: OpenRISC-%x00 (rev %d) @ %d MHz\n", ver, rev, (CONFIG_SYS_CLK_FREQ / 1000000)); + if (vr2) { + cpu_implementation(vr2, impl_str); + printf(" Implementation: %s\n", impl_str); + } + if (upr & SPR_UPR_DCP) { block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16; ways = 1 << (dccfgr & SPR_DCCFGR_NCW); |