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| author | Stafford Horne <shorne@gmail.com> | 2021-03-03 22:50:23 +0900 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-17 11:55:30 +0100 |
| commit | 5dd045f2756e2a3e097a4c722e6a91b008378503 (patch) | |
| tree | f85f43329944e29c4824d9d7d6d2833cbfa77d79 /arch/openrisc | |
| parent | 3a2611819a83c0cefb371a018bfa59aff608e319 (diff) | |
| download | barebox-5dd045f2756e2a3e097a4c722e6a91b008378503.tar.gz barebox-5dd045f2756e2a3e097a4c722e6a91b008378503.tar.xz | |
openrisc: Use movhi to zero registers
This is needed when running on FPGA as registers are not guaranteed
to be initialized to 0. Using movhi allows to explicitly set 0.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/openrisc')
| -rw-r--r-- | arch/openrisc/cpu/start.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/openrisc/cpu/start.S b/arch/openrisc/cpu/start.S index 7ac790b055..c448d3775f 100644 --- a/arch/openrisc/cpu/start.S +++ b/arch/openrisc/cpu/start.S @@ -37,10 +37,10 @@ .org 0x100 __reset: /* there is no guarantee r0 is hardwired to zero, clear it here */ - l.andi r0, r0, 0 + l.movhi r0, 0x0 /* reset stack and frame pointers */ - l.andi r1, r0, 0 - l.andi r2, r0, 0 + l.movhi r1, 0x0 + l.movhi r2, 0x0 /* set supervisor mode */ l.ori r3,r0,SPR_SR_SM |