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| author | Franck Jullien <franck.jullien@gmail.com> | 2014-05-21 23:32:27 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-05-22 08:07:21 +0200 |
| commit | 9ac710c31df33aa5fbcaeb0c08c2427a1d56c5e3 (patch) | |
| tree | c75aed5e1d21574298d8533d56854e8193e520bf /arch/openrisc | |
| parent | d4d9fc125f51996824c1e8d1a446a8801aef5b05 (diff) | |
| download | barebox-9ac710c31df33aa5fbcaeb0c08c2427a1d56c5e3.tar.gz barebox-9ac710c31df33aa5fbcaeb0c08c2427a1d56c5e3.tar.xz | |
openrisc: update SPR registers definition
The OpenRISC architecture specification v1.0 defines
new SPR registers. This patch adds registers definition
for group 0 and update bit definitions for the CPU
configuration register.
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/openrisc')
| -rw-r--r-- | arch/openrisc/include/asm/spr-defs.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h index cb0cdfa7fe..b3b08db4d0 100644 --- a/arch/openrisc/include/asm/spr-defs.h +++ b/arch/openrisc/include/asm/spr-defs.h @@ -49,6 +49,11 @@ #define SPR_ICCFGR (SPRGROUP_SYS + 6) #define SPR_DCFGR (SPRGROUP_SYS + 7) #define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_VR2 (SPRGROUP_SYS + 9) +#define SPR_AVR (SPRGROUP_SYS + 10) +#define SPR_EVBAR (SPRGROUP_SYS + 11) +#define SPR_AECR (SPRGROUP_SYS + 12) +#define SPR_AESR (SPRGROUP_SYS + 13) #define SPR_NPC (SPRGROUP_SYS + 16) #define SPR_SR (SPRGROUP_SYS + 17) #define SPR_PPC (SPRGROUP_SYS + 18) @@ -164,7 +169,13 @@ #define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ #define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ #define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ -#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ +#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */ +#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */ +#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */ +#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */ +#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */ + /* Arithmetic Exception Status Register (AESR) presents */ +#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */ /* * Bit definitions for the Debug configuration register and other |