move boards to arch/<architecure>/boards

this will allow each arch to handle the boards more simply and depending on
there need

the env var BOARD will refer to the current board dirent

for sandbox as we have only one board the board dirent is arch/sandbox/board

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

7 files changed, 541 insertions, 1 deletions

diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile
index c24d3c3685..46d64e5bc6 100644
--- a/arch/ppc/Makefile
+++ b/arch/ppc/Makefile
@@ -35,7 +35,7 @@ PHONY += maketools
 
 
 ifneq ($(board-y),)
-BOARD  := board/$(board-y)/
+BOARD  := arch/ppc/boards/$(board-y)/
 else
 BOARD  :=
 endif
diff --git a/arch/ppc/boards/pcm030/Makefile b/arch/ppc/boards/pcm030/Makefile
new file mode 100644
index 0000000000..e7d744bfb4
--- /dev/null
+++ b/arch/ppc/boards/pcm030/Makefile
@@ -0,0 +1,2 @@
+obj-y += pcm030.o
+extra-y += barebox.lds
diff --git a/arch/ppc/boards/pcm030/barebox.lds.S b/arch/ppc/boards/pcm030/barebox.lds.S
new file mode 100644
index 0000000000..ab99335675
--- /dev/null
+++ b/arch/ppc/boards/pcm030/barebox.lds.S
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-generic/barebox.lds.h>
+
+OUTPUT_ARCH("powerpc")
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  . = TEXT_BASE;
+
+  /* Read-only sections, merged into text segment: */
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    arch/ppc/mach-mpc5xxx/start.o	(.text)
+    *(.text*)
+    *(.got1*)
+    . = ALIGN(16);
+    *(.rodata*)
+    *(.rodata1*)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _etext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+
+  .data    :
+  {
+    *(.data*)
+    *(.data1*)
+    *(.sdata*)
+    *(.sdata2*)
+    *(.dynamic*)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __barebox_cmd_start = .;
+  .barebox_cmd : { BAREBOX_CMDS }
+  __barebox_cmd_end = .;
+
+  __barebox_initcalls_start = .;
+  .barebox_initcalls : { INITCALLS }
+  __barebox_initcalls_end = .;
+  __initcall_entries = (__barebox_initcalls_end - __barebox_initcalls_start) >> 2;
+
+  __usymtab_start = .;
+  __usymtab : { BAREBOX_SYMS }
+  __usymtab_end = .;
+
+  __early_init_data_begin = .;
+  .early_init_data : { *(.early_init_data) }
+  __early_init_data_end = .;
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __init_size = __init_end - _start;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss*) *(.scommon*)
+   *(.dynbss*)
+   *(.bss*)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/arch/ppc/boards/pcm030/config.h b/arch/ppc/boards/pcm030/config.h
new file mode 100644
index 0000000000..a772ee6d96
--- /dev/null
+++ b/arch/ppc/boards/pcm030/config.h
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2003-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messatechnik GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <mach/mpc5xxx.h>
+
+/* #define DEBUG */
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+High Level Configuration Options
+(easy to change)
+ ------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CONFIG_MPC5200_DDR	1	/* (with DDR-SDRAM) */
+#define CFG_MPC5XXX_CLKIN	33333333 /* ... running at 33.333333MHz */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot	     */
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+Serial console configuration
+ ------------------------------------------------------------------------------------------------------------------------------------------------------*/
+
+#if (TEXT_BASE == 0xFF000000)		/* Boot low */
+#define CFG_LOWBOOT		1
+#endif
+/* RAMBOOT will be defined automatically in memory section */
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+IPB Bus clocking configuration.
+ ------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define  CFG_IPBSPEED_133		/* define for 133MHz speed */
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66		/* define for 66MHz speed */
+#else
+#undef CFG_PCISPEED_66			/* for 33MHz speed */
+#endif
+
+/* we only use CS-Boot */
+#define CFG_BOOTCS_START	0xFF000000
+#define CFG_BOOTCS_SIZE		0x01000000
+
+#if CONFIG_MACH_PHYCORE_MPC5200B_TINY_REV == 1
+#define CFG_BOOTCS_CFG		0x0008FD00
+#else
+#define CFG_BOOTCS_CFG		0x00083800
+#endif
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+  Memory map
+ ------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CFG_MBAR		0xF0000000 /* MBAR hast to be switched by other bootloader or debugger config  */
+#define CFG_SDRAM_BASE		0x00000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+#define CONFIG_EARLY_INITDATA_SIZE 0x100
+
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ GPIO configuration
+ ------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CFG_GPS_PORT_CONFIG	0x00558c10 /* PSC6=UART, PSC3=UART ; Ether=100MBit with MD */
+
+/*------------------------------------------------------------------------------------------------------------------------------------------------------
+ Various low-level settings
+ ------------------------------------------------------------------------------------------------------------------------------------------------------*/
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define OF_CPU			"PowerPC,5200@0"
+#define OF_TBCLK		CFG_MPC5XXX_CLKIN
+#define OF_SOC                  "soc5200@f0000000"
+
+#endif /* __CONFIG_H */
diff --git a/arch/ppc/boards/pcm030/mt46v32m16-75.h b/arch/ppc/boards/pcm030/mt46v32m16-75.h
new file mode 100644
index 0000000000..4d191f1f91
--- /dev/null
+++ b/arch/ppc/boards/pcm030/mt46v32m16-75.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * Eric Schumann, Phytec Messtechnik
+ * adapted for mt46v32m16-75 DDR-RAM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x715f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+
+
+/* Settings for XLB = 99 MHz */
+/*
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714b0f00
+#define SDRAM_CONFIG1	0x63611730
+#define SDRAM_CONFIG2	0x47670000
+*/
+
+#define SDRAM_TAPDELAY	0x10000000 /* reserved Bit in MPC5200 B3-Step */
diff --git a/arch/ppc/boards/pcm030/pcm030.c b/arch/ppc/boards/pcm030/pcm030.c
new file mode 100644
index 0000000000..f3845adf4c
--- /dev/null
+++ b/arch/ppc/boards/pcm030/pcm030.c
@@ -0,0 +1,235 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messtechnik GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <init.h>
+#include <mach/mpc5xxx.h>
+#include <mach/fec.h>
+#include <types.h>
+#include <partition.h>
+#include <mem_malloc.h>
+#include <reloc.h>
+
+struct device_d cfi_dev = {
+	.name     = "cfi_flash",
+	.map_base = 0xff000000,
+	.size     = 16 * 1024 * 1024,
+};
+
+static struct memory_platform_data ram_pdata = {
+	.name = "ram0",
+	.flags = DEVFS_RDWR,
+};
+
+struct device_d sdram_dev = {
+	.name     = "mem",
+	.map_base = 0x0,
+	.size     = 64 * 1024 * 1024,
+	.platform_data = &ram_pdata,
+};
+
+static struct mpc5xxx_fec_platform_data fec_info = {
+	.xcv_type = MII100,
+};
+
+struct device_d eth_dev = {
+	.name		= "fec_mpc5xxx",
+	.map_base	= MPC5XXX_FEC,
+	.platform_data	= &fec_info,
+};
+
+static int devices_init (void)
+{
+	register_device(&cfi_dev);
+	register_device(&sdram_dev);
+	register_device(&eth_dev);
+
+	devfs_add_partition("nor0", 0x00f00000, 0x40000, PARTITION_FIXED, "self0");
+	devfs_add_partition("nor0", 0x00f60000, 0x20000, PARTITION_FIXED, "env0");
+
+	return 0;
+}
+
+device_initcall(devices_init);
+
+static struct device_d psc3 = {
+	.name     = "mpc5xxx_serial",
+	.map_base = MPC5XXX_PSC3,
+	.size     = 4096,
+};
+
+static struct device_d psc6 = {
+	.name     = "mpc5xxx_serial",
+	.map_base = MPC5XXX_PSC6,
+	.size     = 4096,
+};
+
+static int console_init(void)
+{
+	register_device(&psc3);
+	register_device(&psc6);
+	return 0;
+}
+
+console_initcall(console_init);
+
+void *get_early_console_base(const char *name)
+{
+	if (!strcmp(name, RELOC("psc3")))
+		return (void *)MPC5XXX_PSC3;
+	if (!strcmp(name, RELOC("psc6")))
+		return (void *)MPC5XXX_PSC6;
+	return NULL;
+}
+
+#include "mt46v32m16-75.h"
+
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+
+	ulong test1, test2;
+
+	if ((ulong)RELOC(initdram) > (2 << 30)) {
+		/* setup SDRAM chip selects */
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
+		__asm__ volatile ("sync");
+
+		/* setup config registers */
+		*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+		*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+		__asm__ volatile ("sync");
+
+#if SDRAM_DDR && SDRAM_TAPDELAY
+		/* set tap delay */
+		*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+		__asm__ volatile ("sync");
+#endif
+
+		/* find RAM size using SDRAM CS0 only */
+		sdram_start(0);
+		test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x10000000);
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x10000000);
+		if (test1 > test2) {
+			sdram_start(0);
+			dramsize = test1;
+		} else {
+			dramsize = test2;
+		}
+
+		/* memory smaller than 1MB is impossible */
+		if (dramsize < (1 << 20)) {
+			dramsize = 0;
+		}
+
+		/* set SDRAM CS0 size according to the amount of RAM found */
+		if (dramsize > 0) {
+			*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+		} else {
+			*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+		}
+	} else
+		puts(RELOC("skipping sdram initialization\n"));
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+	return dramsize + dramsize2;
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+}
+#endif
+
diff --git a/arch/ppc/boards/pcm030/pcm030.dox b/arch/ppc/boards/pcm030/pcm030.dox
new file mode 100644
index 0000000000..b9ada839f2
--- /dev/null
+++ b/arch/ppc/boards/pcm030/pcm030.dox
@@ -0,0 +1,8 @@
+/** @page pcm030 Phytec's phyCORE-MPC5200B-tiny
+
+This CPU card is based on a Freescale MPC5200B CPU. The card is shipped with:
+
+- up to 16MiB NOR type Flash Memory
+- 64MiB synchronous dynamic RAM
+
+*/