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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-03-22 14:39:08 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-03-23 12:16:25 +0100 |
| commit | 2a2ea36c14c2f301c6ce3705c6864f23e1e7e40c (patch) | |
| tree | 295b8784a4797f9e9cd5f96c65c04078b7d1ab8f /arch/riscv/boot/start.S | |
| parent | 497a1f97cb156863f78673cb3a2cbc8a2b0bdb9e (diff) | |
| download | barebox-2a2ea36c14c2f301c6ce3705c6864f23e1e7e40c.tar.gz barebox-2a2ea36c14c2f301c6ce3705c6864f23e1e7e40c.tar.xz | |
RISC-V: erizo: move to arch/riscv/boards/erizo
In preparation for migrating to PBL for RISC-V platforms, move the only
existing board support to a new arch/riscv/boards/ directory.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv/boot/start.S')
| -rw-r--r-- | arch/riscv/boot/start.S | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/arch/riscv/boot/start.S b/arch/riscv/boot/start.S deleted file mode 100644 index d1dbe48b7b..0000000000 --- a/arch/riscv/boot/start.S +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Startup Code for RISC-V CPU - * - * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com> - * - * based on coreboot/src/arch/riscv/bootblock.S - * and barebox/arch/mips/boot/start.S - * - * This file is part of barebox. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <asm-generic/memory_layout.h> - -#include "mach/debug_ll.h" - -#include "asm/riscv_nmon.h" - - .text - .section ".text_entry" - .align 2 - -.globl _start -_start: - debug_ll_ns16550_init - - riscv_nmon - - li sp, STACK_BASE + STACK_SIZE - - /* copy barebox to link location */ - - la a0, _start /* a0 <- _start actual address */ - li a1, CONFIG_TEXT_BASE /* a1 <- _start link address */ - - beq a0, a1, main_entry - - la a2, __bss_start - -#define LONGSIZE 4 - -copy_loop: - /* copy from source address [a0] */ - lw t0, LONGSIZE * 0(a0) - lw t1, LONGSIZE * 1(a0) - lw t2, LONGSIZE * 2(a0) - lw t3, LONGSIZE * 3(a0) - /* copy to target address [a1] */ - sw t0, LONGSIZE * 0(a1) - sw t1, LONGSIZE * 1(a1) - sw t2, LONGSIZE * 2(a1) - sw t3, LONGSIZE * 3(a1) - addi a0, a0, LONGSIZE * 4 - addi a1, a1, LONGSIZE * 4 - bgeu a2, a0, copy_loop - - /* Alas! At the moment I can't load main_entry __link__ address - into a0 with la. Use CONFIG_TEXT_BASE instead. This solution - leads to extra cycles for repeat sp initialization. */ - - li a0, CONFIG_TEXT_BASE - jalr a0 |