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authorAntony Pavlov <antonynpavlov@gmail.com>2018-12-18 10:19:35 +0300
committerSascha Hauer <s.hauer@pengutronix.de>2019-01-07 08:53:18 +0100
commitcccb796fb4d8c3f651f06ca110d442c5ac2303e3 (patch)
tree826c6df7cc80e560be3fcabfba61e51de0de4daa /arch/riscv/dts
parent8099f22c1bfac85110823ea2dafcfb01453bcbae (diff)
downloadbarebox-cccb796fb4d8c3f651f06ca110d442c5ac2303e3.tar.gz
RISC-V: add Erizo SoC support
Erizo is an opensource hardware SoC for FPGA. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv/dts')
-rw-r--r--arch/riscv/dts/Makefile2
-rw-r--r--arch/riscv/dts/erizo-generic.dts14
-rw-r--r--arch/riscv/dts/erizo.dtsi46
3 files changed, 62 insertions, 0 deletions
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 0a88af1..903fe8f 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,8 @@ ifneq ($(BUILTIN_DTB),)
obj-dtb-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
endif
+obj-dtb-$(CONFIG_BOARD_ERIZO_GENERIC) += erizo-generic.dtb.o
+
# just to build a built-in.o. Otherwise compilation fails when no devicetree is
# created.
obj- += dummy.o
diff --git a/arch/riscv/dts/erizo-generic.dts b/arch/riscv/dts/erizo-generic.dts
new file mode 100644
index 0000000..d1f8d57
--- /dev/null
+++ b/arch/riscv/dts/erizo-generic.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "erizo.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "generic Erizo SoC board";
+ compatible = "miet-riscv-workgroup,erizo-generic-board";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x80000000 0x00800000>;
+ };
+};
diff --git a/arch/riscv/dts/erizo.dtsi b/arch/riscv/dts/erizo.dtsi
new file mode 100644
index 0000000..0753479
--- /dev/null
+++ b/arch/riscv/dts/erizo.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/dts-v1/;
+
+/ {
+ compatible = "miet-riscv-workgroup,erizo";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clocks {
+ ref_clk: ref_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "cliffordwolf,picorv32";
+ clocks = <&ref_clk>;
+ reg = <0>;
+ };
+ };
+
+ uart0: uart@90000000 {
+ compatible = "ns16550a";
+ reg = <0x90000000 0x20>;
+ reg-shift = <2>;
+ clocks = <&ref_clk>;
+ };
+
+ gpio0: gpio@91000000 {
+ compatible = "wd,mbl-gpio";
+ reg-names = "dat", "dirout";
+ reg = <0x91000000 0x4>,
+ <0x91000004 0x4>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+};