diff options
author | Antony Pavlov <antonynpavlov@gmail.com> | 2018-12-18 10:19:34 +0300 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-01-07 08:53:18 +0100 |
commit | 8099f22c1bfac85110823ea2dafcfb01453bcbae (patch) | |
tree | 53ad0dbd618f659eacca533eb14c78582ed2b9dc /arch/riscv/lib | |
parent | 64fc4ac1b50a06b17a72c7427e797b3a33a30e8c (diff) | |
download | barebox-8099f22c1bfac85110823ea2dafcfb01453bcbae.tar.gz barebox-8099f22c1bfac85110823ea2dafcfb01453bcbae.tar.xz |
Add initial RISC-V architecture support
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv/lib')
-rw-r--r-- | arch/riscv/lib/.gitignore | 1 | ||||
-rw-r--r-- | arch/riscv/lib/Makefile | 3 | ||||
-rw-r--r-- | arch/riscv/lib/asm-offsets.c | 12 | ||||
-rw-r--r-- | arch/riscv/lib/barebox.lds.S | 79 | ||||
-rw-r--r-- | arch/riscv/lib/riscv_timer.c | 63 |
5 files changed, 158 insertions, 0 deletions
diff --git a/arch/riscv/lib/.gitignore b/arch/riscv/lib/.gitignore new file mode 100644 index 0000000000..d1165788c9 --- /dev/null +++ b/arch/riscv/lib/.gitignore @@ -0,0 +1 @@ +barebox.lds diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile new file mode 100644 index 0000000000..a1df0b7dc7 --- /dev/null +++ b/arch/riscv/lib/Makefile @@ -0,0 +1,3 @@ +extra-y += barebox.lds + +obj-y += riscv_timer.o diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c new file mode 100644 index 0000000000..22f382b71e --- /dev/null +++ b/arch/riscv/lib/asm-offsets.c @@ -0,0 +1,12 @@ +/* + * Generate definitions needed by assembly language modules. + * This code generates raw asm output which is post-processed to extract + * and format the required data. + */ + +#include <linux/kbuild.h> + +int main(void) +{ + return 0; +} diff --git a/arch/riscv/lib/barebox.lds.S b/arch/riscv/lib/barebox.lds.S new file mode 100644 index 0000000000..ffb97f40e8 --- /dev/null +++ b/arch/riscv/lib/barebox.lds.S @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2016 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <asm-generic/barebox.lds.h> + +OUTPUT_ARCH(riscv) +ENTRY(_start) +SECTIONS +{ + . = TEXT_BASE; + + . = ALIGN(8); + .text : + { + _stext = .; + _start = .; + KEEP(*(.text_entry*)) + _text = .; + *(.text*) + } + + . = ALIGN(8); + .rodata : { *(.rodata*) } + + _etext = .; /* End of text and rodata section */ + _sdata = .; + + . = ALIGN(8); + .data : { *(.data*) } + + .barebox_imd : { BAREBOX_IMD } + + . = ALIGN(8); + .got : { *(.got*) } + + . = .; + __barebox_cmd_start = .; + .barebox_cmd : { BAREBOX_CMDS } + __barebox_cmd_end = .; + + __barebox_magicvar_start = .; + .barebox_magicvar : { BAREBOX_MAGICVARS } + __barebox_magicvar_end = .; + + __barebox_initcalls_start = .; + .barebox_initcalls : { INITCALLS } + __barebox_initcalls_end = .; + + __barebox_exitcalls_start = .; + .barebox_exitcalls : { EXITCALLS } + __barebox_exitcalls_end = .; + + __usymtab_start = .; + __usymtab : { BAREBOX_SYMS } + __usymtab_end = .; + + .rela.dyn : { *(.rela*) } + + .oftables : { BAREBOX_CLK_TABLE() } + + .dtb : { BAREBOX_DTB() } + + _edata = .; + . = ALIGN(8); + __bss_start = .; + .bss : { *(.bss*) *(.sbss*) } + __bss_stop = .; + _end = .; +} diff --git a/arch/riscv/lib/riscv_timer.c b/arch/riscv/lib/riscv_timer.c new file mode 100644 index 0000000000..919d77d4b5 --- /dev/null +++ b/arch/riscv/lib/riscv_timer.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017 Antony Pavlov <antonynpavlov@gmail.com> + * + * This file is part of barebox. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/** + * @file + * @brief Clocksource based on RISC-V cycle CSR timer + */ + +#include <init.h> +#include <of.h> +#include <linux/clk.h> +#include <clock.h> + +static uint64_t rdcycle_read(void) +{ + register unsigned long __v; + + __asm__ __volatile__ ("rdcycle %0" : "=r" (__v)); + + return __v; +} + +static struct clocksource rdcycle_cs = { + .read = rdcycle_read, + .mask = CLOCKSOURCE_MASK(32), +}; + +static int rdcycle_cs_init(void) +{ + unsigned int cycle_frequency; + + /* default rate: 100 MHz */ + cycle_frequency = 100000000; + + if (IS_ENABLED(CONFIG_OFTREE)) { + struct device_node *np; + struct clk *clk; + + np = of_get_cpu_node(0, NULL); + if (np) { + clk = of_clk_get(np, 0); + if (!IS_ERR(clk)) { + cycle_frequency = clk_get_rate(clk); + } + } + } + + clocks_calc_mult_shift(&rdcycle_cs.mult, &rdcycle_cs.shift, + cycle_frequency, NSEC_PER_SEC, 10); + + return init_clock(&rdcycle_cs); +} +postcore_initcall(rdcycle_cs_init); |