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author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2022-01-03 13:05:36 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-01-05 08:58:44 +0100 |
commit | 37c070752a9ceac49633600df01c8513f6423908 (patch) | |
tree | b2916b2cf7f88984926e0f7c40a814a32004a04e /arch/riscv | |
parent | 5df7f569ee184a6280b0edd1965623e432984f3e (diff) | |
download | barebox-37c070752a9ceac49633600df01c8513f6423908.tar.gz barebox-37c070752a9ceac49633600df01c8513f6423908.tar.xz |
arch: add SPDX-License-Identifier to all headers
Record GPL-2.0-only as license for all files lacking an explicit license
statement.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20220103120539.1730644-9-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv')
-rw-r--r-- | arch/riscv/include/asm/asm-offsets.h | 2 | ||||
-rw-r--r-- | arch/riscv/include/asm/bitsperlong.h | 2 | ||||
-rw-r--r-- | arch/riscv/include/asm/byteorder.h | 2 | ||||
-rw-r--r-- | arch/riscv/include/asm/io.h | 2 | ||||
-rw-r--r-- | arch/riscv/include/asm/mmu.h | 2 | ||||
-rw-r--r-- | arch/riscv/include/asm/posix_types.h | 2 | ||||
-rw-r--r-- | arch/riscv/include/asm/swab.h | 2 | ||||
-rw-r--r-- | arch/riscv/include/asm/types.h | 2 | ||||
-rw-r--r-- | arch/riscv/include/asm/unaligned.h | 2 |
9 files changed, 18 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/asm-offsets.h b/arch/riscv/include/asm/asm-offsets.h index d370ee36a1..33db5a47e5 100644 --- a/arch/riscv/include/asm/asm-offsets.h +++ b/arch/riscv/include/asm/asm-offsets.h @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include <generated/asm-offsets.h> diff --git a/arch/riscv/include/asm/bitsperlong.h b/arch/riscv/include/asm/bitsperlong.h index 6dc0bb0c13..bf000a04cc 100644 --- a/arch/riscv/include/asm/bitsperlong.h +++ b/arch/riscv/include/asm/bitsperlong.h @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include <asm-generic/bitsperlong.h> diff --git a/arch/riscv/include/asm/byteorder.h b/arch/riscv/include/asm/byteorder.h index 0be826927b..36dfd37524 100644 --- a/arch/riscv/include/asm/byteorder.h +++ b/arch/riscv/include/asm/byteorder.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _ASM_RISCV_BYTEORDER_H #define _ASM_RISCV_BYTEORDER_H diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 795e670e3b..978f644340 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ASM_RISCV_IO_H #define __ASM_RISCV_IO_H diff --git a/arch/riscv/include/asm/mmu.h b/arch/riscv/include/asm/mmu.h index 95af871420..1c2646ebb3 100644 --- a/arch/riscv/include/asm/mmu.h +++ b/arch/riscv/include/asm/mmu.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ASM_MMU_H #define __ASM_MMU_H diff --git a/arch/riscv/include/asm/posix_types.h b/arch/riscv/include/asm/posix_types.h index 22cae6230c..feaed42471 100644 --- a/arch/riscv/include/asm/posix_types.h +++ b/arch/riscv/include/asm/posix_types.h @@ -1 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #include <asm-generic/posix_types.h> diff --git a/arch/riscv/include/asm/swab.h b/arch/riscv/include/asm/swab.h index 60a90120b6..0ca746f0f1 100644 --- a/arch/riscv/include/asm/swab.h +++ b/arch/riscv/include/asm/swab.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _ASM_SWAB_H #define _ASM_SWAB_H diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 1ad5904f91..add1c94fc7 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef __ASM_RISCV_TYPES_H #define __ASM_RISCV_TYPES_H diff --git a/arch/riscv/include/asm/unaligned.h b/arch/riscv/include/asm/unaligned.h index c37b71c21e..3bc2930989 100644 --- a/arch/riscv/include/asm/unaligned.h +++ b/arch/riscv/include/asm/unaligned.h @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + #ifndef _ASM_RISCV_UNALIGNED_H #define _ASM_RISCV_UNALIGNED_H |