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| author | Marco Felsch <m.felsch@pengutronix.de> | 2023-02-02 14:26:12 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-02-03 09:04:37 +0100 |
| commit | b0ad40ee6e5eceeb27e8f29ad54f80c75699e067 (patch) | |
| tree | 7957664bf46a1dad1c43133d1106df659ff123a2 /arch/riscv | |
| parent | 4dd9721f6b7fd76a2287063ffadc8a9638564ade (diff) | |
| download | barebox-b0ad40ee6e5eceeb27e8f29ad54f80c75699e067.tar.gz barebox-b0ad40ee6e5eceeb27e8f29ad54f80c75699e067.tar.xz | |
RISC-V: Makefile: fix build with binutils 2.38
With binutils >= 2.38 the default risc-v ISA spec version has been
bumped to 20191213, so we now need to specify the extension for csr and
fence.i as well. Do it the kernel way and port commit
| commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3
| Author: Aurelien Jarno <aurelien@aurel32.net>
| Date: Wed Jan 26 18:14:42 2022 +0100
|
| riscv: fix build with binutils 2.38
|
| From version 2.38, binutils default to ISA spec version 20191213. This
| means that the csr read/write (csrr*/csrw*) instructions and fence.i
| instruction has separated from the `I` extension, become two standalone
| extensions: Zicsr and Zifencei. As the kernel uses those instruction,
| this causes the following build failure:
|
| CC arch/riscv/kernel/vdso/vgettimeofday.o
| <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages:
| <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
| <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
| <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
| <<BUILDDIR>>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01'
|
| The fix is to specify those extensions explicitely in -march. However as
| older binutils version do not support this, we first need to detect
| that.
|
| Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| Tested-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
| Cc: stable@vger.kernel.org
| Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Link: https://lore.barebox.org/20230202132612.691206-3-m.felsch@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Makefile | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index d1b689b493..1371f17e7c 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -16,6 +16,10 @@ endif riscv-march-$(CONFIG_ARCH_RV32I) := rv32im riscv-march-$(CONFIG_ARCH_RV64I) := rv64im +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) +riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei KBUILD_CPPFLAGS += -march=$(riscv-march-y) KBUILD_CPPFLAGS += -Wstrict-prototypes -mcmodel=medany -fpic |