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author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2021-06-19 06:50:49 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2021-06-24 08:53:47 +0200 |
commit | bccfe152b73097903035b612845cdc33c8c01213 (patch) | |
tree | 58a71b53d6a6a0f596d21721c6b7c9cc8a5bb060 /arch/riscv | |
parent | 6f92e74e5b94d8e6a3652797b55521ac5d287541 (diff) | |
download | barebox-bccfe152b73097903035b612845cdc33c8c01213.tar.gz barebox-bccfe152b73097903035b612845cdc33c8c01213.tar.xz |
reset: add StarFive reset controller driver
The StarFive SoC has a single reset controller, which seems to control
reset of all clocks and peripherals. It differs from the ones supported
by the Linux reset-simple driver in that it has a dedicated status
registers that needs to be polled to verify the reset has completed.
Also special is that most resets (> 70) are synchronous. As the reset
status poll would just time out without the clock, have the reset
controller enable the clock as part of the reset. OS can decide later,
which clocks to disable again.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20210619045055.779-24-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv')
-rw-r--r-- | arch/riscv/Kconfig.socs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index c112fcc82e..e5603b001c 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -49,6 +49,7 @@ endif config SOC_STARFIVE bool "StarFive SoCs" + select ARCH_HAS_RESET_CONTROLLER help This enables support for SiFive SoC platform hardware. |