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| author | Ahmad Fatoum <a.fatoum@pengutronix.de> | 2023-04-11 09:14:29 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-04-11 13:43:19 +0200 |
| commit | c6400f87c4d133c27e8199ffeaff75f23b11f3e7 (patch) | |
| tree | cda9f14cd532e32041381052a49d6ce9f77cd032 /arch/riscv | |
| parent | b0f1c680331f9c89fa7bbc57d911c82a15358d01 (diff) | |
| download | barebox-c6400f87c4d133c27e8199ffeaff75f23b11f3e7.tar.gz barebox-c6400f87c4d133c27e8199ffeaff75f23b11f3e7.tar.xz | |
RISC-V: restrict GCC optimization some more
Some of these we are already setting for ARM and all of them are already
in use by the Linux RISC-V arch Makefile.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.barebox.org/20230411071436.1630752-8-a.fatoum@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 1371f17e7c..71ca82fe8d 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -22,6 +22,9 @@ toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zi riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei KBUILD_CPPFLAGS += -march=$(riscv-march-y) +KBUILD_CFLAGS += -mno-save-restore +KBUILD_CFLAGS += -fno-asynchronous-unwind-tables -fno-unwind-tables +KBUILD_CFLAGS += $(call cc-option,-mstrict-align) KBUILD_CPPFLAGS += -Wstrict-prototypes -mcmodel=medany -fpic riscv-ldflags-y += -pie -static |