Remove all ARM __raw_* functions. They are mixed all over

the place. This clean up all ARM architectures to use only one set
of io functions.

Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>

10 files changed, 79 insertions, 79 deletions

diff --git a/arch/arm/lib/io-readsb.S b/arch/arm/lib/io-readsb.S
index f4ee00afb7..9ee07b8fe5 100644
--- a/arch/arm/lib/io-readsb.S
+++ b/arch/arm/lib/io-readsb.S
@@ -25,7 +25,7 @@
 
 .section .text.readsb
 
-ENTRY(__raw_readsb)
+ENTRY(readsb)
 		teq	r2, #0		@ do we have to check for the zero len?
 		moveq	pc, lr
 		ands	ip, r1, #3
@@ -122,4 +122,4 @@ ENTRY(__raw_readsb)
 		strgtb	r3, [r1]
 
 		ldmfd	sp!, {r4 - r6, pc}
-ENDPROC(__raw_readsb)
+ENDPROC(readsb)
diff --git a/arch/arm/lib/io-readsw-armv4.S b/arch/arm/lib/io-readsw-armv4.S
index ad7a75aa39..f5b34a3479 100644
--- a/arch/arm/lib/io-readsw-armv4.S
+++ b/arch/arm/lib/io-readsw-armv4.S
@@ -26,7 +26,7 @@
 		sub	r2, r2, #1
 		strh	ip, [r1], #2
 
-ENTRY(__raw_readsw)
+ENTRY(readsw)
 		teq	r2, #0
 		moveq	pc, lr
 		tst	r1, #3
@@ -130,4 +130,4 @@ ENTRY(__raw_readsw)
    _BE_ONLY_(	movne	ip, ip, lsr #24		)
 		strneb	ip, [r1]
 		ldmfd	sp!, {r4, pc}
-ENDPROC(__raw_readsw)
+ENDPROC(readsw)
diff --git a/arch/arm/lib/io-writesb.S b/arch/arm/lib/io-writesb.S
index b8b8ebf3d9..1ab8e47cb4 100644
--- a/arch/arm/lib/io-writesb.S
+++ b/arch/arm/lib/io-writesb.S
@@ -45,7 +45,7 @@
 		subs	r2, r2, ip
 		bne	.Loutsb_aligned
 
-ENTRY(__raw_writesb)
+ENTRY(writesb)
 		teq	r2, #0		@ do we have to check for the zero len?
 		moveq	pc, lr
 		ands	ip, r1, #3
@@ -93,4 +93,4 @@ ENTRY(__raw_writesb)
 		strgtb	r3, [r0]
 
 		ldmfd	sp!, {r4, r5, pc}
-ENDPROC(__raw_writesb)
+ENDPROC(writesb)
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index a325186710..cd0aa7f2d8 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -31,7 +31,7 @@
 		sub	r2, r2, #1
 		strh	r3, [r0]
 
-ENTRY(__raw_writesw)
+ENTRY(writesw)
 		teq	r2, #0
 		moveq	pc, lr
 		ands	r3, r1, #3
@@ -96,4 +96,4 @@ ENTRY(__raw_writesw)
 3:		movne	ip, r3, lsr #8
 		strneh	ip, [r0]
 		mov	pc, lr
-ENDPROC(__raw_writesw)
+ENDPROC(writesw)
diff --git a/arch/arm/mach-at91sam9/gpio.c b/arch/arm/mach-at91sam9/gpio.c
index 5db628e07b..09894b7fd0 100644
--- a/arch/arm/mach-at91sam9/gpio.c
+++ b/arch/arm/mach-at91sam9/gpio.c
@@ -85,10 +85,10 @@ int at91_set_gpio_input(unsigned pin, int use_pullup)
 	if (!pio)
 		return -EINVAL;
 
-	__raw_writel(mask, pio + OFS_PIO_IDR);
-	__raw_writel(mask, pio + (use_pullup ? OFS_PIO_PUER : OFS_PIO_PUDR));
-	__raw_writel(mask, pio + OFS_PIO_ODR);
-	__raw_writel(mask, pio + OFS_PIO_PER);
+	writel(mask, pio + OFS_PIO_IDR);
+	writel(mask, pio + (use_pullup ? OFS_PIO_PUER : OFS_PIO_PUDR));
+	writel(mask, pio + OFS_PIO_ODR);
+	writel(mask, pio + OFS_PIO_PER);
 	return 0;
 }
 EXPORT_SYMBOL(at91_set_gpio_input);
@@ -105,11 +105,11 @@ int at91_set_gpio_output(unsigned pin, int value)
 	if (!pio)
 		return -EINVAL;
 
-	__raw_writel(mask, pio + OFS_PIO_IDR);
-	__raw_writel(mask, pio + OFS_PIO_PUDR);
-	__raw_writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
-	__raw_writel(mask, pio + OFS_PIO_OER);
-	__raw_writel(mask, pio + OFS_PIO_PER);
+	writel(mask, pio + OFS_PIO_IDR);
+	writel(mask, pio + OFS_PIO_PUDR);
+	writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
+	writel(mask, pio + OFS_PIO_OER);
+	writel(mask, pio + OFS_PIO_PER);
 	return 0;
 }
 EXPORT_SYMBOL(at91_set_gpio_output);
@@ -119,9 +119,9 @@ int gpio_direction_input(unsigned pin)
 	void __iomem	*pio = pin_to_controller(pin);
 	unsigned	mask = pin_to_mask(pin);
 
-	if (!pio || !(__raw_readl(pio + OFS_PIO_PSR) & mask))
+	if (!pio || !(readl(pio + OFS_PIO_PSR) & mask))
 		return -EINVAL;
-	__raw_writel(mask, pio + OFS_PIO_ODR);
+	writel(mask, pio + OFS_PIO_ODR);
 	return 0;
 }
 EXPORT_SYMBOL(gpio_direction_input);
@@ -131,10 +131,10 @@ int gpio_direction_output(unsigned pin, int value)
 	void __iomem	*pio = pin_to_controller(pin);
 	unsigned	mask = pin_to_mask(pin);
 
-	if (!pio || !(__raw_readl(pio + OFS_PIO_PSR) & mask))
+	if (!pio || !(readl(pio + OFS_PIO_PSR) & mask))
 		return -EINVAL;
-	__raw_writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
-	__raw_writel(mask, pio + OFS_PIO_OER);
+	writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
+	writel(mask, pio + OFS_PIO_OER);
 	return 0;
 }
 EXPORT_SYMBOL(gpio_direction_output);
@@ -151,7 +151,7 @@ void gpio_set_value(unsigned pin, int value)
 
 	if (!pio)
 		return;
-	__raw_writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
+	writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
 }
 EXPORT_SYMBOL(gpio_set_value);
 
@@ -167,7 +167,7 @@ int gpio_get_value(unsigned pin)
 
 	if (!pio)
 		return -EINVAL;
-	pdsr = __raw_readl(pio + OFS_PIO_PDSR);
+	pdsr = readl(pio + OFS_PIO_PDSR);
 	return (pdsr & mask) != 0;
 }
 EXPORT_SYMBOL(gpio_get_value);
diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c
index 22b5014f19..4e7383ccc0 100644
--- a/arch/arm/mach-omap/gpmc.c
+++ b/arch/arm/mach-omap/gpmc.c
@@ -54,20 +54,20 @@ void gpmc_generic_init(unsigned int cfg)
 	debug("gpmccfg=%x\n", cfg);
 	/* Generic Configurations */
 	/* No idle, L3 clock free running */
-	__raw_writel(0x10, GPMC_REG(SYS_CONFIG));
+	writel(0x10, GPMC_REG(SYS_CONFIG));
 	/* No Timeout */
-	__raw_writel(0x00, GPMC_REG(TIMEOUT_CONTROL));
+	writel(0x00, GPMC_REG(TIMEOUT_CONTROL));
 	/* No IRQs */
-	__raw_writel(0x00, GPMC_REG(IRQ_ENABLE));
+	writel(0x00, GPMC_REG(IRQ_ENABLE));
 	/* Write the gpmc_config value */
-	__raw_writel(cfg, GPMC_REG(CFG));
+	writel(cfg, GPMC_REG(CFG));
 
 	/* Disable all CS - prevents remaps
 	 * But NEVER run me in XIP mode! I will Die!
 	 */
 	while (x < GPMC_NUM_CS) {
 		debug("gpmccs=%d Reg:%x <-0x0\n", x, reg);
-		__raw_writel(0x0, reg);
+		writel(0x0, reg);
 		reg += GPMC_CONFIG_CS_SIZE;
 		x++;
 	}
@@ -91,14 +91,14 @@ void gpmc_cs_config(char cs, struct gpmc_config *config)
 	debug("gpmccs=%x cfg=%x\n", cs, (unsigned int)config);
 
 	/* Disable the CS before reconfiguring */
-	__raw_writel(0x0, GPMC_REG(CONFIG7_0) + (cs * GPMC_CONFIG_CS_SIZE));
+	writel(0x0, GPMC_REG(CONFIG7_0) + (cs * GPMC_CONFIG_CS_SIZE));
 	mdelay(1);		/* Settling time */
 
 	/* Write the CFG1-6 regs */
 	while (x < 6) {
 		debug("gpmccfg=%d Reg:%x <-0x%x\n",
 				x, reg, config->cfg[x]);
-		__raw_writel(config->cfg[x], reg);
+		writel(config->cfg[x], reg);
 		reg += GPMC_CONFIG_REG_OFF;
 		x++;
 	}
@@ -108,7 +108,7 @@ void gpmc_cs_config(char cs, struct gpmc_config *config)
 		     ((config->size & 0xF) << 8) |	/* Size */
 		     ((config->base >> 24) & 0x3F));
 
-	__raw_writel((0x1 << 6) |			/* CS enable */
+	writel((0x1 << 6) |			/* CS enable */
 		     ((config->size & 0xF) << 8) |	/* Size */
 		     ((config->base >> 24) & 0x3F),	/* Address */
 		     reg);
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 5c3e25e234..ce26cb5fac 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -67,34 +67,34 @@ static u32 get_osc_clk_speed(void)
 {
 	u32 start, cstart, cend, cdiff, val;
 
-	val = __raw_readl(PRM_REG(CLKSRC_CTRL));
+	val = readl(PRM_REG(CLKSRC_CTRL));
 	/* If SYS_CLK is being divided by 2, remove for now */
 	val = (val & (~(0x1 << 7))) | (0x1 << 6);
-	__raw_writel(val, PRM_REG(CLKSRC_CTRL));
+	writel(val, PRM_REG(CLKSRC_CTRL));
 
 	/* enable timer2 */
-	val = __raw_readl(CM_REG(CLKSEL_WKUP)) | (0x1 << 0);
-	__raw_writel(val, CM_REG(CLKSEL_WKUP));	/* select sys_clk for GPT1 */
+	val = readl(CM_REG(CLKSEL_WKUP)) | (0x1 << 0);
+	writel(val, CM_REG(CLKSEL_WKUP));	/* select sys_clk for GPT1 */
 
 	/* Enable I and F Clocks for GPT1 */
-	val = __raw_readl(CM_REG(ICLKEN_WKUP)) | (0x1 << 0) | (0x1 << 2);
-	__raw_writel(val, CM_REG(ICLKEN_WKUP));
-	val = __raw_readl(CM_REG(FCLKEN_WKUP)) | (0x1 << 0);
-	__raw_writel(val, CM_REG(FCLKEN_WKUP));
+	val = readl(CM_REG(ICLKEN_WKUP)) | (0x1 << 0) | (0x1 << 2);
+	writel(val, CM_REG(ICLKEN_WKUP));
+	val = readl(CM_REG(FCLKEN_WKUP)) | (0x1 << 0);
+	writel(val, CM_REG(FCLKEN_WKUP));
 	/* start counting at 0 */
-	__raw_writel(0, OMAP_GPTIMER1_BASE + TLDR);
+	writel(0, OMAP_GPTIMER1_BASE + TLDR);
 	/* enable clock */
-	__raw_writel(GPT_EN, OMAP_GPTIMER1_BASE + TCLR);
+	writel(GPT_EN, OMAP_GPTIMER1_BASE + TCLR);
 	/* enable 32kHz source - enabled out of reset */
 	/* determine sys_clk via gauging */
 
-	start = 20 + __raw_readl(S32K_CR);	/* start time in 20 cycles */
-	while (__raw_readl(S32K_CR) < start) ;	/* dead loop till start time */
+	start = 20 + readl(S32K_CR);	/* start time in 20 cycles */
+	while (readl(S32K_CR) < start) ;	/* dead loop till start time */
 	/* get start sys_clk count */
-	cstart = __raw_readl(OMAP_GPTIMER1_BASE + TCRR);
-	while (__raw_readl(S32K_CR) < (start + 20)) ;	/* wait for 40 cycles */
+	cstart = readl(OMAP_GPTIMER1_BASE + TCRR);
+	while (readl(S32K_CR) < (start + 20)) ;	/* wait for 40 cycles */
 	/* get end sys_clk count */
-	cend = __raw_readl(OMAP_GPTIMER1_BASE + TCRR);
+	cend = readl(OMAP_GPTIMER1_BASE + TCRR);
 	cdiff = cend - cstart;	/* get elapsed ticks */
 
 	/* based on number of ticks assign speed */
@@ -219,16 +219,16 @@ void prcm_init(void)
 		/* if running from flash,
 		 * jump to small relocated code area in SRAM.
 		 */
-		p0 = __raw_readl(CM_REG(CLKEN_PLL));
+		p0 = readl(CM_REG(CLKEN_PLL));
 		sr32((u32) &p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
 		sr32((u32) &p0, 4, 4, dpll_param_p->fsel);
 
-		p1 = __raw_readl(CM_REG(CLKSEL1_PLL));
+		p1 = readl(CM_REG(CLKSEL1_PLL));
 		sr32((u32) &p1, 27, 2, dpll_param_p->m2);
 		sr32((u32) &p1, 16, 11, dpll_param_p->m);
 		sr32((u32) &p1, 8, 7, dpll_param_p->n);
 		sr32((u32) &p1, 6, 1, 0);	/* set source for 96M */
-		p2 = __raw_readl(CM_REG(CLKSEL_CORE));
+		p2 = readl(CM_REG(CLKSEL_CORE));
 		sr32((u32) &p2, 8, 4, CORE_SSI_DIV);
 		sr32((u32) &p2, 4, 2, CORE_FUSB_DIV);
 		sr32((u32) &p2, 2, 2, CORE_L4_DIV);
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index c0221d9ee8..3acf911251 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -82,7 +82,7 @@ u32 get_cpu_type(void)
 u32 get_cpu_rev(void)
 {
 	u32 idcode_val;
-	idcode_val = __raw_readl(IDCODE_REG);
+	idcode_val = readl(IDCODE_REG);
 	if ((idcode_val & (HAWKEYE_MASK | VERSION_MASK)) == HAWKEYE_ES2_1)
 		return CPU_ES2P1;
 	if ((idcode_val & HAWKEYE_MASK) == HAWKEYE_ES2)
@@ -102,7 +102,7 @@ u32 get_sdr_cs_size(u32 offset)
 {
 	u32 size;
 	/* get ram size field */
-	size = __raw_readl(SDRC_REG(MCFG_0) + offset) >> 8;
+	size = readl(SDRC_REG(MCFG_0) + offset) >> 8;
 	size &= 0x3FF;		/* remove unwanted bits */
 	size *= 2 * (1024 * 1024);	/* find size in MB */
 	return size;
@@ -117,7 +117,7 @@ u32 get_sdr_cs_size(u32 offset)
  */
 inline u32 get_sysboot_value(void)
 {
-	return (0x0000003F & __raw_readl(CONTROL_REG(STATUS)));
+	return (0x0000003F & readl(CONTROL_REG(STATUS)));
 }
 
 /**
@@ -133,7 +133,7 @@ inline u32 get_sysboot_value(void)
 u32 get_gpmc0_base(void)
 {
 	u32 b;
-	b = __raw_readl(GPMC_REG(CONFIG7_0));
+	b = readl(GPMC_REG(CONFIG7_0));
 	b &= 0x1F;		/* keep base [5:0] */
 	b = b << 24;		/* ret 0x0b000000 */
 	return b;
@@ -225,7 +225,7 @@ u32 get_boot_type(void)
 u32 get_device_type(void)
 {
 	int mode;
-	mode = __raw_readl(CONTROL_REG(STATUS)) & (DEVICE_MASK);
+	mode = readl(CONTROL_REG(STATUS)) & (DEVICE_MASK);
 	return (mode >>= 8);
 }
 
@@ -243,26 +243,26 @@ static void secure_unlock_mem(void)
 #define UNLOCK_2 0x00000000
 #define UNLOCK_3 0x0000FFFF
 	/* Protection Module Register Target APE (PM_RT) */
-	__raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
-	__raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
-	__raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
-	__raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
+	writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
+	writel(UNLOCK_1, RT_READ_PERMISSION_0);
+	writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
+	writel(UNLOCK_2, RT_ADDR_MATCH_1);
 
-	__raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
-	__raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
-	__raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
+	writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
+	writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
+	writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
 
-	__raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
-	__raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
-	__raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
-	__raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
+	writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
+	writel(UNLOCK_3, OCM_READ_PERMISSION_0);
+	writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
+	writel(UNLOCK_2, OCM_ADDR_MATCH_2);
 
 	/* IVA Changes */
-	__raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
-	__raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
-	__raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
+	writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
+	writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
+	writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
 
-	__raw_writel(UNLOCK_1, SMS_RG_ATT0);	/* SDRC region 0 public */
+	writel(UNLOCK_1, SMS_RG_ATT0);	/* SDRC region 0 public */
 }
 
 /**
@@ -314,13 +314,13 @@ static void watchdog_init(void)
 	sr32(CM_REG(ICLKEN_WKUP), 5, 1, 1);
 	wait_on_value((0x1 << 5), 0x20, CM_REG(IDLEST_WKUP), 5);
 
-	__raw_writel(WDT_DISABLE_CODE1, WDT_REG(WSPR));
+	writel(WDT_DISABLE_CODE1, WDT_REG(WSPR));
 
 	do {
-		pending = __raw_readl(WDT_REG(WWPS));
+		pending = readl(WDT_REG(WWPS));
 	} while (pending);
 
-	__raw_writel(WDT_DISABLE_CODE2, WDT_REG(WSPR));
+	writel(WDT_DISABLE_CODE2, WDT_REG(WSPR));
 }
 
 /**
@@ -427,7 +427,7 @@ unsigned int omap_uart_read(unsigned long base, unsigned char reg_idx)
 {
 	unsigned int *reg_addr = (unsigned int *)base;
 	reg_addr += reg_idx;
-	return __raw_readb(reg_addr);
+	return readb(reg_addr);
 }
 EXPORT_SYMBOL(omap_uart_read);
 
@@ -445,6 +445,6 @@ void omap_uart_write(unsigned int val, unsigned long base,
 {
 	unsigned int *reg_addr = (unsigned int *)base;
 	reg_addr += reg_idx;
-	__raw_writeb(val, reg_addr);
+	writeb(val, reg_addr);
 }
 EXPORT_SYMBOL(omap_uart_write);
diff --git a/arch/arm/mach-omap/s32k_clksource.c b/arch/arm/mach-omap/s32k_clksource.c
index bacc0ddea7..4166d83d75 100644
--- a/arch/arm/mach-omap/s32k_clksource.c
+++ b/arch/arm/mach-omap/s32k_clksource.c
@@ -50,7 +50,7 @@
  */
 static uint64_t s32k_clocksource_read(void)
 {
-	return __raw_readl(S32K_CR);
+	return readl(S32K_CR);
 }
 
 /* A bit obvious isn't it? */
diff --git a/arch/arm/mach-omap/syslib.c b/arch/arm/mach-omap/syslib.c
index f1d6c2bdf1..0ca4ef21d3 100644
--- a/arch/arm/mach-omap/syslib.c
+++ b/arch/arm/mach-omap/syslib.c
@@ -66,9 +66,9 @@ void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
 	u32 tmp, msk = 0;
 	msk = 1 << num_bits;
 	--msk;
-	tmp = __raw_readl(addr) & ~(msk << start_bit);
+	tmp = readl(addr) & ~(msk << start_bit);
 	tmp |=  value << start_bit;
-	__raw_writel(tmp, addr);
+	writel(tmp, addr);
 }
 
 /**
@@ -87,7 +87,7 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
 	u32 i = 0, val;
 	do {
 		++i;
-		val = __raw_readl(read_addr) & read_bit_mask;
+		val = readl(read_addr) & read_bit_mask;
 		if (val == match_value)
 			return 1;
 		if (i == bound)