Merge branch 'docu_update' of octopus:/home/jbe/work/u-boot-v2 into jbe

4 files changed, 107 insertions, 17 deletions

diff --git a/arch/architecture.dox b/arch/architecture.dox
index 9013bae1b2..6ef5ba928d 100644
--- a/arch/architecture.dox
+++ b/arch/architecture.dox
@@ -84,10 +84,90 @@ Note: U-Boot-v2 expects an upward counting counter!
 
 TODO
 
- - @subpage dev_arm_mach
- - @subpage dev_bf_mach
- - @subpage dev_ppc_mach
+@li @subpage dev_arm_mach
+@li @subpage dev_bf_mach
+@li @subpage dev_ppc_mach
 
 */
 
+/** @page io_access_functions I/O access functions
 
+List of functions to be used for hardware register access (I/O).
+
+@section native_access Native IN/OUT access
+
+@note Native means: It uses the same endianess than the CPU.
+
+@subsection single_native_access Single access of various width
+
+The following functions are intended to be used for a single I/O access.
+
+To read a byte (8 bit) from a specific I/O address:
+@code
+uint8_t readb(unsigned long)
+@endcode
+
+To read a word (16 bit) from a specific I/O address:
+@code
+uint16_t readw(unsigned long)
+@endcode
+
+To read a long word (32 bit) from a specific I/O address:
+@code
+uint32_t readl(unsigned long)
+@endcode
+
+To write a byte (8 bit) into a specific I/O address:
+@code
+void writeb(uint8_t val, unsigned long)
+@endcode
+
+To write a word (16 bit) into a specific I/O address:
+@code
+void writew(uint16_t val, unsigned long)
+@endcode
+
+To write a long word (32 bit) into a specific I/O address:
+@code
+void writel(uint32_t val, unsigned long)
+@endcode
+
+@subsection string_native_access String native access of various width
+
+The following functions are intended to be used for string based I/O access.
+
+To read a string of bytes (8 bit) from one specific I/O address:
+@code
+void readsb(const void __iomem *addr, void *mem_buffer, int byte_count);
+@endcode
+
+To read a string of words (16 bit) from one specific I/O address:
+@code
+void readsw(const void __iomem *addr, void *mem_buffer, int word_count);
+@endcode
+
+To read a string of long words (32 bit) from one specific I/O address:
+@code
+void readsl(const void __iomem *addr, void *mem_buffer, int long_count);
+@endcode
+
+To write a string of bytes (8 bit) to one specific I/O address:
+@code
+void writesb(void __iomem *addr, const void *mem_buffer, int byte_count);
+@endcode
+
+To write a string of words (16 bit) to one specific I/O address:
+@code
+void writesw(void __iomem *addr, const void *mem_buffer, int word_count);
+@endcode
+
+To write a string of long words (32 bit) to one specific I/O address:
+@code
+void writesl(void __iomem *addr, const void *mem_buffer, int long_count);
+@endcode
+
+@section special_access Special IN/OUT access
+
+TBD
+
+*/
diff --git a/arch/arm/lib/findbit.S b/arch/arm/lib/findbit.S
index 30c8a1a62a..7fa93a5d0a 100644
--- a/arch/arm/lib/findbit.S
+++ b/arch/arm/lib/findbit.S
@@ -1,7 +1,3 @@
-/**
- * @file
- * @brief common bitops
- */
 /*
  * Originally from Linux kernel
  *  arch/arm/lib/findbit.S
diff --git a/arch/arm/mach-arm.dox b/arch/arm/mach-arm.dox
index 412ce3840f..106aa39df9 100644
--- a/arch/arm/mach-arm.dox
+++ b/arch/arm/mach-arm.dox
@@ -6,7 +6,7 @@
 
 FIXME
 
-@par What's happens when the reset signal is gone
+@section mach_arm_reset What's happens when the reset signal is gone
 
 @note Code running immediately after reset runs at an address it is not linked
       to: "runtime address != link address". You should only use branches and
@@ -22,29 +22,44 @@ After handling some MMU related things \<board_init_lowlevel\> can be called (if
 not disabled). This is a board specific function for SDRAM setup for example.
 As its board specific, your can do whatever you need to bring your board up.
 
+In the case the boot happens from NAND flash memory, further steps are required.
+Most of the known processor devices are reading the first few blocks from the
+NAND flash memory into some kind of internal SRAM. This small part must be able
+to initialize the SDRAM controller and to read the remaining rest of the
+U-Boot-v2 binary from the NAND flash memory prior returning from \<board_init_lowlevel\>.
+
 When \<board_init_lowlevel\> returns it will be assumed there is now a working
 RAM that can be used for all further steps.
 
-Next step is relocation of U-Boot itself. It gets copied to RAM and the last
-assembler instruction is a jump into \<start_uboot\>. This target address is
-the first C instruction in U-Boot. At this point of time:\n
+Next step is relocation of U-Boot itself (if not already done). It gets copied
+to RAM and the last assembler instruction is a jump into start_uboot(). This
+target address is the first C instruction in U-Boot. At this point of time:\n
 "runtime address == link address".
 
-@par Architectures using ARM processors
-For details on specific architectures:
- - @subpage dev_omap_arch
-
 @section mach_arm_files List of changes
 
 Lets call the new MACH new_cpu.
 
  - create a new subdirectory in /arch/arm/new_cpu
+ - create a new subdirectory in /include/asm-arm/new_cpu
+ - add CPU specific definitions into /include/asm-arm/new_cpu/
  - add /arch/arm/new_cpu/Kconfig
  - add /arch/arm/new_cpu/Makfile
  - add other CPU specific code into /arch/arm/new_cpu/
  - modify /arch/arm/Kconfig
  - modify /arch/arm/Makfile
 
+@section mach_arm_architecures Architectures using ARM processors
+For details on specific architectures:
+
+@subsection mach_arm_omap_info OMAP CPUs
+
+@li @subpage dev_omap_arch
+
+@subsection mach_arm_s3c24xx_info S3C24XX CPUs
+
+@li @subpage dev_s3c24xx_arch
+
 TODO add more details
 
 */
diff --git a/arch/arm/mach-s3c24xx/lowlevel-init.S b/arch/arm/mach-s3c24xx/lowlevel-init.S
index 8c32f50508..d27cfa5dfb 100644
--- a/arch/arm/mach-s3c24xx/lowlevel-init.S
+++ b/arch/arm/mach-s3c24xx/lowlevel-init.S
@@ -162,8 +162,7 @@ Define in the machine specific config.h the following symbols:
 
 @note Valid values for the PLL settings can be found in the CPU manual.
 
-@par Background: PLL frequency calculation for the S3C2410 CPU (both PLLs)
-and S3C2440 (UPLL only)
+@par Background: PLL frequency calculation for the S3C2410 CPU (both PLLs) and S3C2440 (UPLL only)
 
 @f[
 	f_{PLL} = \frac{m * f_{Ref}}{p * 2^s}