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authorSascha Hauer <s.hauer@pengutronix.de>2010-04-16 15:46:53 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2010-05-03 15:05:38 +0200
commitbd9e5ca89e29809561181fddea04af2361f18c4c (patch)
tree53d8eb85233ba081604f6ff500cfcf7178f8d3a5 /arch
parent64a6eb6a38fa5a4511b797a6ac5e50cdbf9dc69d (diff)
downloadbarebox-bd9e5ca89e29809561181fddea04af2361f18c4c.tar.gz
barebox-bd9e5ca89e29809561181fddea04af2361f18c4c.tar.xz
arm: move __mmu_cache_flush to bare_init section
Instead of having seperate cache flush functions in the startup code we want to call the generic functions. To accomplish this they have to be in the bare_init section. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/cache-armv4.S2
-rw-r--r--arch/arm/cpu/cache-armv5.S2
-rw-r--r--arch/arm/cpu/cache-armv6.S3
-rw-r--r--arch/arm/cpu/cache-armv7.S2
4 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index a79cc27789..3cec4dd9af 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -41,6 +41,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
+.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
@@ -73,6 +74,7 @@ no_cache_id:
mov pc, lr
ENDPROC(__mmu_cache_flush)
+.section ".text.text"
/*
* dma_inv_range(start, end)
*
diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S
index f52bcb77ca..9fb320ff0c 100644
--- a/arch/arm/cpu/cache-armv5.S
+++ b/arch/arm/cpu/cache-armv5.S
@@ -41,6 +41,7 @@ ENTRY(__mmu_cache_off)
mov pc, lr
ENDPROC(__mmu_cache_off)
+.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
@@ -48,6 +49,7 @@ ENTRY(__mmu_cache_flush)
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
ENDPROC(__mmu_cache_flush)
+.section ".text.text"
/*
* dma_inv_range(start, end)
diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S
index e3498bb117..25476d5a29 100644
--- a/arch/arm/cpu/cache-armv6.S
+++ b/arch/arm/cpu/cache-armv6.S
@@ -31,6 +31,7 @@ __common_mmu_cache_on:
mrc p15, 0, r0, c1, c0, 0 @ and read it back to
sub pc, lr, r0, lsr #32 @ properly flush pipeline
+
ENTRY(__mmu_cache_off)
#ifdef CONFIG_MMU
mrc p15, 0, r0, c1, c0
@@ -42,6 +43,7 @@ ENTRY(__mmu_cache_off)
#endif
mov pc, lr
+.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
@@ -50,6 +52,7 @@ ENTRY(__mmu_cache_flush)
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
ENDPROC(__mmu_cache_flush)
+.section ".text.text"
/*
* v6_dma_inv_range(start,end)
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 9afa20d25a..a303dc1285 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -49,6 +49,7 @@ ENTRY(__mmu_cache_off)
mov pc, r12
ENDPROC(__mmu_cache_on)
+.section ".text_bare_init.text"
ENTRY(__mmu_cache_flush)
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
@@ -105,6 +106,7 @@ iflush:
mcr p15, 0, r10, c7, c5, 4 @ ISB
mov pc, lr
ENDPROC(__mmu_cache_flush)
+.section ".text.text"
/*
* cache_line_size - get the cache line size from the CSIDR register