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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-06-10 14:19:43 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-06-10 14:20:39 +0200 |
| commit | ce971c2367ed57d947f73347f6f9ab3263aec4b9 (patch) | |
| tree | 1026ce9fb5af60281d6162279e7348aa72d77473 /arch | |
| parent | fa9153df32c41bbd73d7c15af363421b2d50f31f (diff) | |
| download | barebox-ce971c2367ed57d947f73347f6f9ab3263aec4b9.tar.gz barebox-ce971c2367ed57d947f73347f6f9ab3263aec4b9.tar.xz | |
arm: use processor specififc functions to turn off MMU
The way it was done before does not work on Cortex processors.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Orjan Friberg <of@flatfrog.com>
Tested-by: Luca Ceresoli <list@lucaceresoli.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/cpu.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c index fbc91aabf2..2b36a793dc 100644 --- a/arch/arm/cpu/cpu.c +++ b/arch/arm/cpu/cpu.c @@ -75,12 +75,19 @@ void arch_shutdown(void) int i; #ifdef CONFIG_MMU + /* nearly the same as below, but this could also disable + * second level cache. + */ mmu_disable(); +#else + asm volatile ( + "bl __mmu_cache_flush;" + "bl __mmu_cache_off;" + : + : + : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory" + ); #endif - - /* flush I/D-cache */ - i = 0; - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); } /** |