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| author | Michael Grzeschik <m.grzeschik@pengutronix.de> | 2010-08-03 19:51:51 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-08-03 22:26:06 +0200 |
| commit | 72ba847b32b052a30d3181968433b32d6d0aa533 (patch) | |
| tree | 0e0932b0ec6b7be6cfd9230ead274a964df87684 /arch | |
| parent | 3b2d5e78e9e80b28a4472133d9833a9f385d9cf1 (diff) | |
| download | barebox-72ba847b32b052a30d3181968433b32d6d0aa533.tar.gz barebox-72ba847b32b052a30d3181968433b32d6d0aa533.tar.xz | |
omap clock: bugfix remove silicon offset sil_index
In omap3_clock_core.S we have just clock values for the ES2
revision, so we should not set any silicon index.
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap/omap3_clock.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c index f1b3b07172..13e8729c3d 100644 --- a/arch/arm/mach-omap/omap3_clock.c +++ b/arch/arm/mach-omap/omap3_clock.c @@ -148,7 +148,7 @@ void prcm_init(void) { int xip_safe; u32 osc_clk = 0, sys_clkin_sel = 0; - u32 clk_index, sil_index; + u32 clk_index, sil_index = 0; struct dpll_param *dpll_param_p; #ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM int p0, p1, p2, p3; @@ -176,14 +176,6 @@ void prcm_init(void) clk_index = sys_clkin_sel; } - /* The DPLL tables are defined according to sysclk value and - * silicon revision. The clk_index value will be used to get - * the values for that input sysclk from the DPLL param table - * and sil_index will get the values for that SysClk for the - * appropriate silicon rev. - */ - if (get_cpu_rev() >= CPU_ES2) - sil_index = 1; /* Unlock MPU DPLL (slows things down, and needed later) */ sr32(CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS); wait_on_value((0x1 << 0), 0, CM_REG(IDLEST_PLL_MPU), LDELAY); |