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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2010-09-12 13:30:04 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-09-20 08:56:37 +0200 |
| commit | e34c1d4fccda53fe7f83dba57d1102e4ba2baf91 (patch) | |
| tree | bb8342665df55a147fcae0844143aa5500deddaf /arch | |
| parent | 427c6085838cb52bf71c316a2c7b5630e94c65f8 (diff) | |
| download | barebox-e34c1d4fccda53fe7f83dba57d1102e4ba2baf91.tar.gz barebox-e34c1d4fccda53fe7f83dba57d1102e4ba2baf91.tar.xz | |
init: introduce __BARE_INIT for .section ".text_bare_init.text"
and make init.h availlable for assembly too
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/cache-armv4.S | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/cache-armv5.S | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/cache-armv6.S | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/cache-armv7.S | 3 |
4 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S index 3cec4dd9af..fc53653c34 100644 --- a/arch/arm/cpu/cache-armv4.S +++ b/arch/arm/cpu/cache-armv4.S @@ -1,4 +1,5 @@ #include <linux/linkage.h> +#include <init.h> #define CACHE_DLINESIZE 32 @@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off) mov pc, lr ENDPROC(__mmu_cache_off) -.section ".text_bare_init.text" +__BARE_INIT ENTRY(__mmu_cache_flush) mrc p15, 0, r6, c0, c0 @ get processor ID mov r2, #64*1024 @ default: 32K dcache size (*2) diff --git a/arch/arm/cpu/cache-armv5.S b/arch/arm/cpu/cache-armv5.S index 9fb320ff0c..d870e6b80f 100644 --- a/arch/arm/cpu/cache-armv5.S +++ b/arch/arm/cpu/cache-armv5.S @@ -1,4 +1,5 @@ #include <linux/linkage.h> +#include <init.h> #define CACHE_DLINESIZE 32 @@ -41,7 +42,7 @@ ENTRY(__mmu_cache_off) mov pc, lr ENDPROC(__mmu_cache_off) -.section ".text_bare_init.text" +__BARE_INIT ENTRY(__mmu_cache_flush) 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache bne 1b diff --git a/arch/arm/cpu/cache-armv6.S b/arch/arm/cpu/cache-armv6.S index 25476d5a29..9de76da452 100644 --- a/arch/arm/cpu/cache-armv6.S +++ b/arch/arm/cpu/cache-armv6.S @@ -1,4 +1,5 @@ #include <linux/linkage.h> +#include <init.h> #define HARVARD_CACHE #define CACHE_LINE_SIZE 32 @@ -43,7 +44,7 @@ ENTRY(__mmu_cache_off) #endif mov pc, lr -.section ".text_bare_init.text" +__BARE_INIT ENTRY(__mmu_cache_flush) mov r1, #0 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index a303dc1285..79bc24358c 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -1,4 +1,5 @@ #include <linux/linkage.h> +#include <init.h> ENTRY(__mmu_cache_on) mov r12, lr @@ -49,7 +50,7 @@ ENTRY(__mmu_cache_off) mov pc, r12 ENDPROC(__mmu_cache_on) -.section ".text_bare_init.text" +__BARE_INIT ENTRY(__mmu_cache_flush) mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) |