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authorSascha Hauer <s.hauer@pengutronix.de>2014-11-06 17:02:45 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2014-11-06 17:16:14 +0100
commit1b88af18a7ba7454f9b074f9aaa4ff1a1e3cc6d8 (patch)
tree59cc6c26370f2a7f9bd65d24744b36497749accd /arch
parent380813ff48cc82271782579dd85cfbe6a26e8d34 (diff)
downloadbarebox-1b88af18a7ba7454f9b074f9aaa4ff1a1e3cc6d8.tar.gz
barebox-1b88af18a7ba7454f9b074f9aaa4ff1a1e3cc6d8.tar.xz
ARM: i.MX6 GuF Santaro: Fix phy clock
Use external phy clock so that the kernel configures GPR1 bit 21 correctly. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/imx6q-guf-santaro.dts9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6q-guf-santaro.dts b/arch/arm/dts/imx6q-guf-santaro.dts
index 7978d803af..98fb78f6f5 100644
--- a/arch/arm/dts/imx6q-guf-santaro.dts
+++ b/arch/arm/dts/imx6q-guf-santaro.dts
@@ -51,6 +51,12 @@
power-supply = <&reg_backlight>;
status = "okay";
};
+
+ phyclk: phyclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
};
&fec {
@@ -58,6 +64,9 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
status = "okay";
+ clocks = <&clks IMX6QDL_CLK_ENET>,
+ <&clks IMX6QDL_CLK_ENET>,
+ <&phyclk>;
};
&i2c1 {