diff options
author | Alexander Kurz <akurz@blala.de> | 2016-06-30 23:24:14 +0200 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-07-04 11:47:58 +0200 |
commit | ca07b91eff5f48150b1cc11b61b445305721f5f4 (patch) | |
tree | 1ff1d17d412b26dbfaf71fec3f5ac4e17c503960 /arch | |
parent | 59a2582df555e511e931571169eca36cf2bf1baf (diff) | |
download | barebox-ca07b91eff5f48150b1cc11b61b445305721f5f4.tar.gz barebox-ca07b91eff5f48150b1cc11b61b445305721f5f4.tar.xz |
imx35-regs: add and use common CGR element shifters
Add some missing Clock Gate Register element shifters which were implemented
as magic numbers in the arm/boards directory. Use the new shifters for
inproved code readability.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boards/eukrea_cpuimx35/lowlevel.c | 9 | ||||
-rw-r--r-- | arch/arm/boards/guf-cupid/lowlevel.c | 5 | ||||
-rw-r--r-- | arch/arm/boards/phytec-phycore-imx35/lowlevel.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-imx/include/mach/imx35-regs.h | 15 |
4 files changed, 26 insertions, 9 deletions
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index 27ca078fd2..aca77a7fbf 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -87,17 +87,18 @@ void __bare_init __naked barebox_arm_reset_vector(void) writel(0x00001000, ccm_base + MX35_CCM_PDR0); r = readl(ccm_base + MX35_CCM_CGR0); - r |= 0x00300000; + r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT; writel(r, ccm_base + MX35_CCM_CGR0); r = readl(ccm_base + MX35_CCM_CGR1); - r |= 0x00030C00; - r |= 0x00000003; + r |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; + r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; + r |= 0x3 << MX35_CCM_CGR1_IOMUX_SHIFT; writel(r, ccm_base + MX35_CCM_CGR1); /* enable watchdog asap */ r = readl(ccm_base + MX35_CCM_CGR2); - r |= 0x03000000; + r |= 0x3 << MX35_CCM_CGR2_WDOG_SHIFT; writel(r, ccm_base + MX35_CCM_CGR2); r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index 1a48b1d142..66d76ae795 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -289,11 +289,12 @@ void __bare_init __naked barebox_arm_reset_vector(void) /* configure clock-gates */ r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); - r0 |= 0x00300000; + r0 |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT; writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - r0 |= 0x00000c03; + r0 |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; + r0 |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); /* Configure SDRAM */ diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c index 7753568c34..5e2f335efa 100644 --- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c +++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c @@ -99,12 +99,12 @@ void __bare_init __naked barebox_arm_reset_vector(void) writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0); r = readl(ccm_base + MX35_CCM_CGR0); - r |= 0x00300000; + r |= 0x3 << MX35_CCM_CGR0_EPIT1_SHIFT; writel(r, ccm_base + MX35_CCM_CGR0); r = readl(ccm_base + MX35_CCM_CGR1); - r |= 0x00000C00; - r |= 0x00000003; + r |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; + r |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; writel(r, ccm_base + MX35_CCM_CGR1); r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h index 6905400304..48bf64386a 100644 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -150,11 +150,26 @@ #define MX35_CCM_CGR3 0x38 #define MX35_CCM_CGR0_CSPI1_SHIFT 10 +#define MX35_CCM_CGR0_CSPI2_SHIFT 12 +#define MX35_CCM_CGR0_EPIT1_SHIFT 20 +#define MX35_CCM_CGR0_EPIT2_SHIFT 22 #define MX35_CCM_CGR0_ESDHC1_SHIFT 26 +#define MX35_CCM_CGR0_ESDHC2_SHIFT 28 +#define MX35_CCM_CGR0_ESDHC3_SHIFT 30 #define MX35_CCM_CGR1_FEC_SHIFT 0 +#define MX35_CCM_CGR1_GPIO1_SHIFT 2 +#define MX35_CCM_CGR1_GPIO2_SHIFT 4 +#define MX35_CCM_CGR1_GPIO3_SHIFT 6 #define MX35_CCM_CGR1_I2C1_SHIFT 10 +#define MX35_CCM_CGR1_I2C2_SHIFT 12 +#define MX35_CCM_CGR1_I2C3_SHIFT 14 +#define MX35_CCM_CGR1_IOMUX_SHIFT 16 +#define MX35_CCM_CGR1_KPP_SHIFT 20 +#define MX35_CCM_CGR2_UART1_SHIFT 16 #define MX35_CCM_CGR2_UART2_SHIFT 18 +#define MX35_CCM_CGR2_UART3_SHIFT 20 #define MX35_CCM_CGR2_USB_SHIFT 22 +#define MX35_CCM_CGR2_WDOG_SHIFT 24 #define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25 #define MX35_CCM_RCSR_MEM_TYPE_SHIFT 23 |