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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2014-01-27 16:24:10 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-01-31 21:29:34 +0100 |
| commit | 45c5110587deb65c820ed2da6602dc16dea9e8d9 (patch) | |
| tree | 72a9e18b994f962ebb1511e4791a70f15635d389 /arch | |
| parent | fe0a08f1a1848f72993ca9556cda24b7673f63ea (diff) | |
| download | barebox-45c5110587deb65c820ed2da6602dc16dea9e8d9.tar.gz barebox-45c5110587deb65c820ed2da6602dc16dea9e8d9.tar.xz | |
ARM: i.MX25: Add missing GPT clock lookups
Only one GPT will be used, but with devicetree support we can't predict
which one it is, so we need the clock lookup for all GPTs to ensure
that the timer gets its clock.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx25.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-imx/include/mach/imx25-regs.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 9817990667..4d8631cb01 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -140,6 +140,9 @@ static int imx25_ccm_probe(struct device_d *dev) clkdev_add_physbase(clks[per15], MX25_UART4_BASE_ADDR, NULL); clkdev_add_physbase(clks[per15], MX25_UART5_BASE_ADDR, NULL); clkdev_add_physbase(clks[per5], MX25_GPT1_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per5], MX25_GPT2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per5], MX25_GPT3_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per5], MX25_GPT4_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX25_FEC_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX25_I2C1_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX25_I2C2_BASE_ADDR, NULL); diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 9ab0fb3eee..71812764c9 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -35,6 +35,9 @@ #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) #define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) +#define MX25_GPT4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x84000) +#define MX25_GPT3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x88000) +#define MX25_GPT2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x8c000) #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) #define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) |