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authorSascha Hauer <s.hauer@pengutronix.de>2015-03-09 08:30:24 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-03-09 08:30:24 +0100
commit696bd3833712e2b0f1ce296353a5cfbfb5ef3321 (patch)
tree9bbe59cf28419ad700a028beaf06301c1de4c092 /arch
parentac1bffb220f6ca82960bf4a2c6f543e953b3b806 (diff)
parent478fb5c3ddcc1bdc9f05583b42fa2ad8a9ad1a78 (diff)
downloadbarebox-696bd3833712e2b0f1ce296353a5cfbfb5ef3321.tar.gz
barebox-696bd3833712e2b0f1ce296353a5cfbfb5ef3321.tar.xz
Merge branch 'for-next/imx'
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boards/Makefile1
-rw-r--r--arch/arm/boards/eukrea_cpuimx25/lowlevel.c9
-rw-r--r--arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S5
-rw-r--r--arch/arm/boards/eukrea_cpuimx35/lowlevel.c5
-rw-r--r--arch/arm/boards/eukrea_cpuimx51/lowlevel.c1
-rw-r--r--arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S7
-rw-r--r--arch/arm/boards/freescale-mx27-ads/lowlevel_init.S2
-rw-r--r--arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S6
-rw-r--r--arch/arm/boards/freescale-mx51-babbage/lowlevel.c1
-rw-r--r--arch/arm/boards/freescale-mx53-qsb/board.c4
-rw-r--r--arch/arm/boards/freescale-mx53-qsb/lowlevel.c2
-rw-r--r--arch/arm/boards/freescale-mx53-smd/lowlevel.c1
-rw-r--r--arch/arm/boards/freescale-mx53-vmx53/lowlevel.c1
-rw-r--r--arch/arm/boards/freescale-mx6-arm2/Makefile2
-rw-r--r--arch/arm/boards/freescale-mx6-arm2/board.c157
-rw-r--r--arch/arm/boards/freescale-mx6-arm2/env/config47
-rw-r--r--arch/arm/boards/freescale-mx6-arm2/flash-header.imxcfg122
-rw-r--r--arch/arm/boards/freescale-mx6-arm2/lowlevel.c11
-rw-r--r--arch/arm/boards/guf-cupid/lowlevel.c3
-rw-r--r--arch/arm/boards/guf-neso/lowlevel.c8
-rw-r--r--arch/arm/boards/guf-vincell/board.c10
-rw-r--r--arch/arm/boards/guf-vincell/lowlevel.c1
-rw-r--r--arch/arm/boards/karo-tx51/lowlevel.c1
-rw-r--r--arch/arm/boards/karo-tx53/lowlevel.c1
-rw-r--r--arch/arm/boards/phytec-phycore-imx31/lowlevel.c10
-rw-r--r--arch/arm/boards/phytec-phycore-imx35/lowlevel.c5
-rw-r--r--arch/arm/boards/scb9328/lowlevel_init.S4
-rw-r--r--arch/arm/configs/freescale-mx6-arm2_defconfig68
-rw-r--r--arch/arm/configs/imx_v7_defconfig1
-rw-r--r--arch/arm/dts/imx6q-embedsky-e9.dts2
-rw-r--r--arch/arm/dts/imx6q-embedsky-e9.dtsi5
-rw-r--r--arch/arm/mach-imx/Kconfig8
-rw-r--r--arch/arm/mach-imx/clk-imx5.c27
-rw-r--r--arch/arm/mach-imx/clk-imx6.c366
-rw-r--r--arch/arm/mach-imx/esdctl.c14
-rw-r--r--arch/arm/mach-imx/include/mach/esdctl.h16
37 files changed, 241 insertions, 694 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f0133d4165..c10d471884 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -217,7 +217,6 @@ barebox.imximg: $(KBUILD_BINARY) FORCE
boarddir = $(srctree)/arch/arm/boards
imxcfg-$(CONFIG_MACH_FREESCALE_MX53_SMD) += $(boarddir)/freescale-mx53-smd/flash-header.imxcfg
-imxcfg-$(CONFIG_MACH_MX6Q_ARM2) += $(boarddir)/freescale-mx6-arm2/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_CCMX51) += $(boarddir)/ccxmx51/flash-header.imxcfg
imxcfg-$(CONFIG_MACH_TX51) += $(boarddir)/karo-tx51/flash-header-karo-tx51.imxcfg
imxcfg-$(CONFIG_MACH_GUF_VINCELL) += $(boarddir)/guf-vincell/flash-header.imxcfg
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 5b0a6d67bd..edc1bb51e8 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -64,7 +64,6 @@ obj-$(CONFIG_MACH_MMCCPU) += mmccpu/
obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/
obj-$(CONFIG_MACH_MX28EVK) += freescale-mx28-evk/
obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard/
-obj-$(CONFIG_MACH_MX6Q_ARM2) += freescale-mx6-arm2/
obj-$(CONFIG_MACH_NESO) += guf-neso/
obj-$(CONFIG_MACH_NOMADIK_8815NHK) += nhk8815/
obj-$(CONFIG_MACH_NVIDIA_BEAVER) += nvidia-beaver/
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index 4edbbe4b8a..7ae8a18e06 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -37,6 +37,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
arm_cpu_lowlevel_init();
+ arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12);
+
/* restart the MPLL and wait until it's stable */
writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27),
MX25_CCM_BASE_ADDR + MX25_CCM_CCTL);
@@ -127,12 +129,9 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000);
writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
- if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
- /* setup a stack to be able to call imx25_barebox_boot_nand_external() */
- arm_setup_stack(MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 12);
-
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND))
imx25_barebox_boot_nand_external(0);
- }
+
out:
imx25_barebox_entry(NULL);
}
diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
index f8e3c23540..b3504832d7 100644
--- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
+++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S
@@ -76,6 +76,8 @@ barebox_arm_reset_vector:
bl arm_cpu_lowlevel_init
+ ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4;
+
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
@@ -124,9 +126,6 @@ barebox_arm_reset_vector:
sdram_init
#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
- /* Setup a temporary stack in SDRAM */
- ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4;
-
mov r0, #0
b imx27_barebox_boot_nand_external
#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index 4788ae2e42..83c25feb41 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -43,6 +43,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
arm_cpu_lowlevel_init();
+ arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
+
r = get_cr();
r |= CR_Z; /* Flow prediction (Z) */
r |= CR_U; /* unaligned accesses */
@@ -137,9 +139,6 @@ void __bare_init __naked barebox_arm_reset_vector(void)
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
- /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
- arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
-
imx35_barebox_boot_nand_external(0);
}
diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c
index 7a85b489d2..ad89076329 100644
--- a/arch/arm/boards/eukrea_cpuimx51/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel.c
@@ -6,5 +6,6 @@
void __naked barebox_arm_reset_vector(void)
{
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0x20000000 - 16);
imx51_barebox_entry(NULL);
}
diff --git a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S
index 4ca4c82d32..a5d54e8d01 100644
--- a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S
@@ -17,6 +17,7 @@
*
*/
+#include <linux/sizes.h>
#include <asm-generic/memory_layout.h>
#include <mach/imx25-regs.h>
#include <mach/imx-pll.h>
@@ -71,6 +72,9 @@ barebox_arm_reset_vector:
writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2)
writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR)
+ /* Setup a temporary stack in SRAM */
+ ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4
+
/* Skip SDRAM initialization if we run from RAM */
cmp pc, #0x80000000
bls 1f
@@ -99,9 +103,6 @@ barebox_arm_reset_vector:
#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
- /* Setup a temporary stack in SRAM */
- ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4
-
mov r0, #0
b imx25_barebox_boot_nand_external
#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
diff --git a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S
index 45f39921ec..e79b96dd2c 100644
--- a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S
@@ -54,6 +54,8 @@ barebox_arm_reset_vector:
bl arm_cpu_lowlevel_init
+ ldr sp, =MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 4;
+
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
diff --git a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S
index 6d37f35a2e..0f9e813191 100644
--- a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S
+++ b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S
@@ -60,6 +60,9 @@ CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR
barebox_arm_reset_vector:
bl arm_cpu_lowlevel_init
+ /* Setup a temporary stack in internal SRAM */
+ ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4
+
mrc 15, 0, r1, c1, c0, 0
mrc 15, 0, r0, c1, c0, 1
@@ -155,9 +158,6 @@ barebox_arm_reset_vector:
str r3, [r0, #0x30]
#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND
- /* Setup a temporary stack in internal SRAM */
- ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4
-
mov r0, #0
b imx35_barebox_boot_nand_external
#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */
diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
index 1b9ba16ef6..0f453f3367 100644
--- a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
+++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c
@@ -11,6 +11,7 @@ ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2)
void *fdt;
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0x20000000 - 16);
fdt = __dtb_imx51_babbage_start - get_runtime_offset();
diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c
index f65b55658f..dd2abb5f5d 100644
--- a/arch/arm/boards/freescale-mx53-qsb/board.c
+++ b/arch/arm/boards/freescale-mx53-qsb/board.c
@@ -85,10 +85,6 @@ static int loco_late_init(void)
!of_machine_is_compatible("fsl,imx53-qsrb"))
return 0;
- device_detect_by_name("mmc0");
-
- devfs_add_partition("mmc0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
-
mc34708 = mc13xxx_get();
if (mc34708) {
unsigned int val;
diff --git a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
index aff6e3bc54..ce6a290ca2 100644
--- a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c
@@ -12,6 +12,7 @@ ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2)
void *fdt;
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0xf8020000 - 8);
fdt = __dtb_imx53_qsb_start - get_runtime_offset();
@@ -25,6 +26,7 @@ ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2)
void *fdt;
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0xf8020000 - 8);
fdt = __dtb_imx53_qsrb_start - get_runtime_offset();
diff --git a/arch/arm/boards/freescale-mx53-smd/lowlevel.c b/arch/arm/boards/freescale-mx53-smd/lowlevel.c
index 306db09acf..5ad0312e82 100644
--- a/arch/arm/boards/freescale-mx53-smd/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-smd/lowlevel.c
@@ -6,5 +6,6 @@
void __naked barebox_arm_reset_vector(void)
{
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0xf8020000 - 8);
imx53_barebox_entry(NULL);
}
diff --git a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
index 487a9fd899..3545a1c352 100644
--- a/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
+++ b/arch/arm/boards/freescale-mx53-vmx53/lowlevel.c
@@ -11,6 +11,7 @@ ENTRY_FUNCTION(start_imx53_vmx53, r0, r1, r2)
void *fdt;
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0xf8020000 - 8);
fdt = __dtb_imx53_voipac_bsb_start - get_runtime_offset();
diff --git a/arch/arm/boards/freescale-mx6-arm2/Makefile b/arch/arm/boards/freescale-mx6-arm2/Makefile
deleted file mode 100644
index 01c7a259e9..0000000000
--- a/arch/arm/boards/freescale-mx6-arm2/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-y += board.o
-lwl-y += lowlevel.o
diff --git a/arch/arm/boards/freescale-mx6-arm2/board.c b/arch/arm/boards/freescale-mx6-arm2/board.c
deleted file mode 100644
index 3d5576c065..0000000000
--- a/arch/arm/boards/freescale-mx6-arm2/board.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) 2012 Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <init.h>
-#include <environment.h>
-#include <mach/imx6-regs.h>
-#include <fec.h>
-#include <gpio.h>
-#include <asm/armlinux.h>
-#include <generated/mach-types.h>
-#include <partition.h>
-#include <linux/phy.h>
-#include <asm/io.h>
-#include <asm/mmu.h>
-#include <mach/generic.h>
-#include <linux/sizes.h>
-#include <mach/imx6.h>
-#include <mach/devices-imx6.h>
-#include <mach/iomux-mx6.h>
-
-static iomux_v3_cfg_t arm2_pads[] = {
- /* UART1 */
- MX6Q_PAD_KEY_COL0__UART4_TXD,
- MX6Q_PAD_KEY_ROW0__UART4_RXD,
-
- MX6Q_PAD_SD1_CLK__USDHC1_CLK,
- MX6Q_PAD_SD1_CMD__USDHC1_CMD,
- MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
- MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
- MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
- MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
-
- MX6Q_PAD_SD2_CLK__USDHC2_CLK,
- MX6Q_PAD_SD2_CMD__USDHC2_CMD,
- MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
- MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
- MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
- MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
-
- MX6Q_PAD_SD3_CLK__USDHC3_CLK,
- MX6Q_PAD_SD3_CMD__USDHC3_CMD,
- MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
- MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
- MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
- MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
- MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
- MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
- MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
- MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
- MX6Q_PAD_GPIO_18__USDHC3_VSELECT,
-
- MX6Q_PAD_SD4_CLK__USDHC4_CLK,
- MX6Q_PAD_SD4_CMD__USDHC4_CMD,
- MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
- MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
- MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
- MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
- MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
- MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
- MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
- MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
-
- MX6Q_PAD_KEY_COL1__ENET_MDIO,
- MX6Q_PAD_KEY_COL2__ENET_MDC,
- MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
- MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
- MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
- MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
- MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
- MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
- MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
- MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
- MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
- MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
- MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
- MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
- MX6Q_PAD_GPIO_0__CCM_CLKO,
- MX6Q_PAD_GPIO_3__CCM_CLKO2,
-};
-
-static int arm2_mem_init(void)
-{
- arm_add_mem_device("ram0", 0x10000000, SZ_2G);
-
- return 0;
-}
-mem_initcall(arm2_mem_init);
-
-static void mx6_rgmii_rework(struct phy_device *dev)
-{
- u16 val;
-
- /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
- phy_write(dev, 0xd, 0x7);
- phy_write(dev, 0xe, 0x8016);
- phy_write(dev, 0xd, 0x4007);
-
- val = phy_read(dev, 0xe);
- val &= 0xffe3;
- val |= 0x18;
- phy_write(dev, 0xe, val);
-
- /* introduce tx clock delay */
- phy_write(dev, 0x1d, 0x5);
-
- val = phy_read(dev, 0x1e);
- val |= 0x0100;
- phy_write(dev, 0x1e, val);
-}
-
-static struct fec_platform_data fec_info = {
- .xcv_type = PHY_INTERFACE_MODE_RGMII,
- .phy_init = mx6_rgmii_rework,
- .phy_addr = 0,
-};
-
-static int arm2_devices_init(void)
-{
- imx6_add_mmc3(NULL);
-
- imx6_add_fec(&fec_info);
-
- armlinux_set_architecture(3837);
-
- devfs_add_partition("disk0", 0, SZ_1M, DEVFS_PARTITION_FIXED, "self0");
- devfs_add_partition("disk0", SZ_1M + SZ_1M, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
-
- return 0;
-}
-
-device_initcall(arm2_devices_init);
-
-static int arm2_console_init(void)
-{
- mxc_iomux_v3_setup_multiple_pads(arm2_pads, ARRAY_SIZE(arm2_pads));
-
- barebox_set_model("Freescale i.MX6 Armadillo2");
- barebox_set_hostname("armadillo2");
-
- imx6_add_uart3();
-
- return 0;
-}
-console_initcall(arm2_console_init);
diff --git a/arch/arm/boards/freescale-mx6-arm2/env/config b/arch/arm/boards/freescale-mx6-arm2/env/config
deleted file mode 100644
index 0ab5bdf0e0..0000000000
--- a/arch/arm/boards/freescale-mx6-arm2/env/config
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/bin/sh
-
-machine=armadillo2
-serverip=
-user=
-
-# use 'dhcp' to do dhcp in barebox and in kernel
-# use 'none' if you want to skip kernel ip autoconfiguration
-ip=dhcp
-
-# or set your networking parameters here
-#eth0.ipaddr=a.b.c.d
-#eth0.netmask=a.b.c.d
-#eth0.gateway=a.b.c.d
-#eth0.serverip=a.b.c.d
-
-# can be either 'nfs', 'tftp', 'nor' or 'nand'
-kernel_loc=tftp
-# can be either 'net', 'nor', 'nand' or 'initrd'
-rootfs_loc=disk
-
-# can be either 'jffs2' or 'ubifs'
-rootfs_type=ubifs
-rootfsimage=root-$machine.$rootfs_type
-
-# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
-kernelimage=zImage-$machine
-
-if [ -n $user ]; then
- kernelimage="$user"-"$kernelimage"
- nfsroot="$serverip:/home/$user/nfsroot/$machine"
- rootfsimage="$user"-"$rootfsimage"
-else
- nfsroot="$serverip:/path/to/nfs/root"
-fi
-
-autoboot_timeout=3
-
-bootargs="console=ttymxc2,115200"
-
-disk_parts="1M(barebox)ro,3M(bareboxenv),4M(kernel),-(root)"
-
-rootfs_part_linux_dev=sda1
-rootfs_type=ext2
-
-# set a fancy prompt (if support is compiled in)
-PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/freescale-mx6-arm2/flash-header.imxcfg b/arch/arm/boards/freescale-mx6-arm2/flash-header.imxcfg
deleted file mode 100644
index 403d184834..0000000000
--- a/arch/arm/boards/freescale-mx6-arm2/flash-header.imxcfg
+++ /dev/null
@@ -1,122 +0,0 @@
-soc imx6
-loadaddr 0x10000000
-dcdofs 0x400
-
-wm 32 0x020e05a8 0x00000030
-wm 32 0x020e05b0 0x00000030
-wm 32 0x020e0524 0x00000030
-wm 32 0x020e051c 0x00000030
-
-wm 32 0x020e0518 0x00000030
-wm 32 0x020e050c 0x00000030
-wm 32 0x020e05b8 0x00000030
-wm 32 0x020e05c0 0x00000030
-
-wm 32 0x020e05ac 0x00020030
-wm 32 0x020e05b4 0x00020030
-wm 32 0x020e0528 0x00020030
-wm 32 0x020e0520 0x00020030
-
-wm 32 0x020e0514 0x00020030
-wm 32 0x020e0510 0x00020030
-wm 32 0x020e05bc 0x00020030
-wm 32 0x020e05c4 0x00020030
-
-wm 32 0x020e056c 0x00020030
-wm 32 0x020e0578 0x00020030
-wm 32 0x020e0588 0x00020030
-wm 32 0x020e0594 0x00020030
-
-wm 32 0x020e057c 0x00020030
-wm 32 0x020e0590 0x00003000
-wm 32 0x020e0598 0x00003000
-wm 32 0x020e058c 0x00000000
-
-wm 32 0x020e059c 0x00003030
-wm 32 0x020e05a0 0x00003030
-wm 32 0x020e0784 0x00000030
-wm 32 0x020e0788 0x00000030
-
-wm 32 0x020e0794 0x00000030
-wm 32 0x020e079c 0x00000030
-wm 32 0x020e07a0 0x00000030
-wm 32 0x020e07a4 0x00000030
-
-wm 32 0x020e07a8 0x00000030
-wm 32 0x020e0748 0x00000030
-wm 32 0x020e074c 0x00000030
-wm 32 0x020e0750 0x00020000
-
-wm 32 0x020e0758 0x00000000
-wm 32 0x020e0774 0x00020000
-wm 32 0x020e078c 0x00000030
-wm 32 0x020e0798 0x000C0000
-
-wm 32 0x021b081c 0x33333333
-wm 32 0x021b0820 0x33333333
-wm 32 0x021b0824 0x33333333
-wm 32 0x021b0828 0x33333333
-
-wm 32 0x021b481c 0x33333333
-wm 32 0x021b4820 0x33333333
-wm 32 0x021b4824 0x33333333
-wm 32 0x021b4828 0x33333333
-
-wm 32 0x021b0018 0x00081740
-
-wm 32 0x021b001c 0x00008000
-wm 32 0x021b000c 0x555A7975
-wm 32 0x021b0010 0xFF538E64
-wm 32 0x021b0014 0x01FF00DB
-wm 32 0x021b002c 0x000026D2
-
-wm 32 0x021b0030 0x005B0E21
-wm 32 0x021b0008 0x09444040
-wm 32 0x021b0004 0x00025576
-wm 32 0x021b0040 0x00000027
-wm 32 0x021b0000 0xC31A0000
-
-wm 32 0x021b001c 0x04088032
-wm 32 0x021b001c 0x0408803A
-wm 32 0x021b001c 0x00008033
-wm 32 0x021b001c 0x0000803B
-wm 32 0x021b001c 0x00428031
-wm 32 0x021b001c 0x00428039
-wm 32 0x021b001c 0x09408030
-wm 32 0x021b001c 0x09408038
-
-wm 32 0x021b001c 0x04008040
-wm 32 0x021b001c 0x04008048
-wm 32 0x021b0800 0xA1380003
-wm 32 0x021b4800 0xA1380003
-wm 32 0x021b0020 0x00005800
-wm 32 0x021b0818 0x00022227
-wm 32 0x021b4818 0x00022227
-
-wm 32 0x021b083c 0x434B0350
-wm 32 0x021b0840 0x034C0359
-wm 32 0x021b483c 0x434B0350
-wm 32 0x021b4840 0x03650348
-wm 32 0x021b0848 0x4436383B
-wm 32 0x021b4848 0x39393341
-wm 32 0x021b0850 0x35373933
-wm 32 0x021b4850 0x48254A36
-
-wm 32 0x021b080c 0x001F001F
-wm 32 0x021b0810 0x001F001F
-
-wm 32 0x021b480c 0x00440044
-wm 32 0x021b4810 0x00440044
-
-wm 32 0x021b08b8 0x00000800
-wm 32 0x021b48b8 0x00000800
-
-wm 32 0x021b001c 0x00000000
-wm 32 0x021b0404 0x00011006
-
-/* enable AXI cache for VDOA/VPU/IPU */
-wm 32 0x020e0010 0xf00000ff
-
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-wm 32 0x020e0018 0x007f007f
-wm 32 0x020e001c 0x007f007f
diff --git a/arch/arm/boards/freescale-mx6-arm2/lowlevel.c b/arch/arm/boards/freescale-mx6-arm2/lowlevel.c
deleted file mode 100644
index f833893335..0000000000
--- a/arch/arm/boards/freescale-mx6-arm2/lowlevel.c
+++ /dev/null
@@ -1,11 +0,0 @@
-#include <common.h>
-#include <linux/sizes.h>
-#include <asm/barebox-arm-head.h>
-#include <asm/barebox-arm.h>
-#include <mach/generic.h>
-
-void __naked barebox_arm_reset_vector(void)
-{
- imx6_cpu_lowlevel_init();
- barebox_arm_entry(0x10000000, SZ_2G, NULL);
-}
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
index 6fc90fbbdc..bcd2a24f8f 100644
--- a/arch/arm/boards/guf-cupid/lowlevel.c
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -313,9 +313,6 @@ void __bare_init __naked barebox_arm_reset_vector(void)
r0 |= 0x1 << 28;
writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
- /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
- arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
-
imx35_barebox_boot_nand_external(0);
}
diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c
index 2828359598..98512a976c 100644
--- a/arch/arm/boards/guf-neso/lowlevel.c
+++ b/arch/arm/boards/guf-neso/lowlevel.c
@@ -39,6 +39,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
arm_cpu_lowlevel_init();
+ arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
+
/* ahb lite ip interface */
writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0);
writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1);
@@ -86,12 +88,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
- if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
- /* setup a stack to be able to call imx27_barebox_boot_nand_external() */
- arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
-
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND))
imx27_barebox_boot_nand_external(0);
- }
out:
imx27_barebox_entry(NULL);
diff --git a/arch/arm/boards/guf-vincell/board.c b/arch/arm/boards/guf-vincell/board.c
index 0c46ade9fc..ded7a3797e 100644
--- a/arch/arm/boards/guf-vincell/board.c
+++ b/arch/arm/boards/guf-vincell/board.c
@@ -29,6 +29,7 @@
#include <io.h>
#include <i2c/i2c.h>
#include <linux/clk.h>
+#include <usb/fsl_usb2.h>
#include <generated/mach-types.h>
@@ -42,6 +43,7 @@
#include <mach/bbu.h>
#include <mach/imx-flash-header.h>
#include <mach/imx5.h>
+#include <mach/usb.h>
#include <asm/armlinux.h>
#include <asm/mmu.h>
@@ -265,6 +267,11 @@ static struct i2c_board_info i2c_devices[] = {
},
};
+static struct fsl_usb2_platform_data usb_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+};
+
static int vincell_devices_init(void)
{
writel(0, MX53_M4IF_BASE_ADDR + 0xc);
@@ -280,6 +287,9 @@ static int vincell_devices_init(void)
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx53_add_i2c0(NULL);
+ add_generic_device("fsl-udc", DEVICE_ID_DYNAMIC, NULL, MX53_OTG_BASE_ADDR, 0x200,
+ IORESOURCE_MEM, &usb_pdata);
+
vincell_fec_reset();
armlinux_set_architecture(3297);
diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c
index 00e34fba39..629529d90a 100644
--- a/arch/arm/boards/guf-vincell/lowlevel.c
+++ b/arch/arm/boards/guf-vincell/lowlevel.c
@@ -129,6 +129,7 @@ void __bare_init __naked barebox_arm_reset_vector(void)
u32 r;
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0xf8020000 - 8);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
diff --git a/arch/arm/boards/karo-tx51/lowlevel.c b/arch/arm/boards/karo-tx51/lowlevel.c
index 7a85b489d2..ad89076329 100644
--- a/arch/arm/boards/karo-tx51/lowlevel.c
+++ b/arch/arm/boards/karo-tx51/lowlevel.c
@@ -6,5 +6,6 @@
void __naked barebox_arm_reset_vector(void)
{
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0x20000000 - 16);
imx51_barebox_entry(NULL);
}
diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c
index 8adbd8d666..fdfb1b7573 100644
--- a/arch/arm/boards/karo-tx53/lowlevel.c
+++ b/arch/arm/boards/karo-tx53/lowlevel.c
@@ -8,6 +8,7 @@
void __naked barebox_arm_reset_vector(void)
{
imx5_cpu_lowlevel_init();
+ arm_setup_stack(0xf8020000 - 8);
/*
* For the TX53 rev 8030 the SDRAM setup is not stable without
diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c
index 44fc5bc765..27e275676f 100644
--- a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c
@@ -39,6 +39,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
arm_cpu_lowlevel_init();
+ arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12);
+
writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR);
writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR);
@@ -125,12 +127,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC);
#endif
- if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
- /* setup a stack to be able to call imx31_barebox_boot_nand_external() */
- arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12);
-
+ if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND))
imx31_barebox_boot_nand_external(0);
- } else {
+ else
imx31_barebox_entry(NULL);
- }
}
diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c
index 919a9af3da..1ad5439c28 100644
--- a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c
+++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c
@@ -49,6 +49,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
arm_cpu_lowlevel_init();
+ arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
+
r = get_cr();
r |= CR_Z; /* Flow prediction (Z) */
r |= CR_U; /* unaligned accesses */
@@ -189,9 +191,6 @@ void __bare_init __naked barebox_arm_reset_vector(void)
r |= 0x1 << 28;
writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4);
- /* setup a stack to be able to call imx35_barebox_boot_nand_external() */
- arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8);
-
imx35_barebox_boot_nand_external(0);
}
diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S
index 717bb90e40..73afc09b70 100644
--- a/arch/arm/boards/scb9328/lowlevel_init.S
+++ b/arch/arm/boards/scb9328/lowlevel_init.S
@@ -100,7 +100,7 @@ barebox_arm_reset_vector:
cmp pc, #0x09000000
bhi 1f
- b imx1_barebox_entry
+ b 2f
1:
@@ -129,5 +129,7 @@ barebox_arm_reset_vector:
writel(0x0, 0x08223000)
/* Set to Normal Mode CAS 2 */
writel(0x810a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0)
+2:
+ ldr sp, =0x08100000 - 4;
b imx1_barebox_entry
diff --git a/arch/arm/configs/freescale-mx6-arm2_defconfig b/arch/arm/configs/freescale-mx6-arm2_defconfig
deleted file mode 100644
index f4119f0986..0000000000
--- a/arch/arm/configs/freescale-mx6-arm2_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
-CONFIG_ARCH_IMX=y
-CONFIG_MACH_MX6Q_ARM2=y
-CONFIG_IMX_IIM=y
-CONFIG_IMX_IIM_FUSE_BLOW=y
-CONFIG_AEABI=y
-CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
-CONFIG_ARM_UNWIND=y
-CONFIG_MMU=y
-CONFIG_MALLOC_SIZE=0x8000000
-CONFIG_MALLOC_TLSF=y
-CONFIG_KALLSYMS=y
-CONFIG_LONGHELP=y
-CONFIG_GLOB=y
-CONFIG_HUSH_FANCY_PROMPT=y
-CONFIG_CMDLINE_EDITING=y
-CONFIG_AUTO_COMPLETE=y
-CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx6-arm2/env/"
-CONFIG_DEBUG_INFO=y
-CONFIG_CMD_EDIT=y
-CONFIG_CMD_SLEEP=y
-CONFIG_CMD_SAVEENV=y
-CONFIG_CMD_EXPORT=y
-CONFIG_CMD_PRINTENV=y
-CONFIG_CMD_READLINE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_TFTP=y
-CONFIG_CMD_ECHO_E=y
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_IOMEM=y
-CONFIG_CMD_FLASH=y
-CONFIG_CMD_BOOTM_SHOW_TYPE=y
-CONFIG_CMD_BOOTM_VERBOSE=y
-CONFIG_CMD_BOOTM_INITRD=y
-CONFIG_CMD_BOOTM_OFTREE=y
-CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
-CONFIG_CMD_UIMAGE=y
-# CONFIG_CMD_BOOTU is not set
-CONFIG_CMD_RESET=y
-CONFIG_CMD_GO=y
-CONFIG_CMD_TIMEOUT=y
-CONFIG_CMD_PARTITION=y
-CONFIG_CMD_MAGICVAR=y
-CONFIG_CMD_MAGICVAR_HELP=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_UNCOMPRESS=y
-CONFIG_NET=y
-CONFIG_CMD_DHCP=y
-CONFIG_NET_NFS=y
-CONFIG_CMD_PING=y
-CONFIG_NET_NETCONSOLE=y
-CONFIG_DRIVER_NET_FEC_IMX=y
-CONFIG_NET_USB=y
-CONFIG_NET_USB_ASIX=y
-CONFIG_NET_USB_SMSC95XX=y
-# CONFIG_SPI is not set
-CONFIG_USB_HOST=y
-CONFIG_USB_EHCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_MCI=y
-CONFIG_MCI_STARTUP=y
-CONFIG_MCI_IMX_ESDHC=y
-CONFIG_FS_TFTP=y
-CONFIG_FS_FAT=y
-CONFIG_FS_FAT_WRITE=y
-CONFIG_FS_FAT_LFN=y
-CONFIG_ZLIB=y
-CONFIG_LZO_DECOMPRESS=y
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 755217f062..c4c28a01d2 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -179,3 +179,4 @@ CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_FS_UBIFS=y
CONFIG_FS_UBIFS_COMPRESSION_LZO=y
+CONFIG_PNG=y
diff --git a/arch/arm/dts/imx6q-embedsky-e9.dts b/arch/arm/dts/imx6q-embedsky-e9.dts
index 53665cf9d5..ab70d05ad9 100644
--- a/arch/arm/dts/imx6q-embedsky-e9.dts
+++ b/arch/arm/dts/imx6q-embedsky-e9.dts
@@ -17,7 +17,7 @@
/ {
chosen {
- linux,stdout-path = &uart4;
+ linux,stdout-path = &uart1;
environment-mmc1 {
compatible = "barebox,environment";
diff --git a/arch/arm/dts/imx6q-embedsky-e9.dtsi b/arch/arm/dts/imx6q-embedsky-e9.dtsi
index a29de9f3c4..f117cae920 100644
--- a/arch/arm/dts/imx6q-embedsky-e9.dtsi
+++ b/arch/arm/dts/imx6q-embedsky-e9.dtsi
@@ -372,10 +372,7 @@
&hdmi {
status = "okay";
-};
-
-&pcie {
- status = "okay";
+ ddc-i2c-bus = <&i2c2>;
};
&can1 {
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 477207e646..c62cea8a0b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -26,7 +26,6 @@ config ARCH_TEXT_BASE
default 0x93d00000 if MACH_TX25
default 0x7ff00000 if MACH_TQMA53
default 0x97f00000 if MACH_TX51
- default 0x4fc00000 if MACH_MX6Q_ARM2
default 0x97f00000 if MACH_CCMX51
default 0x4fc00000 if MACH_SABRELITE
default 0x8fe00000 if MACH_TX53
@@ -174,6 +173,7 @@ config ARCH_IMX6
select ARCH_HAS_FEC_IMX
select CPU_V7
select PINCTRL_IMX_IOMUX_V3
+ select COMMON_CLK_OF_PROVIDER
config ARCH_IMX6SX
bool
@@ -527,12 +527,6 @@ config MACH_GUF_VINCELL
select ARCH_IMX53
select HAVE_DEFAULT_ENVIRONMENT_NEW
-comment "i.MX6 Boards"
-
-config MACH_MX6Q_ARM2
- bool "Freescale i.MX6q Armadillo2"
- select ARCH_IMX6
-
endchoice
# ----------------------------------------------------------
diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c
index ea805b0f64..8a0d875049 100644
--- a/arch/arm/mach-imx/clk-imx5.c
+++ b/arch/arm/mach-imx/clk-imx5.c
@@ -178,9 +178,7 @@ static const char *ipu_sel[] = {
"ahb",
};
-static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate_ckil,
- unsigned long rate_osc, unsigned long rate_ckih1,
- unsigned long rate_ckih2)
+static void __init mx5_clocks_common_init(struct device_d *dev, void __iomem *base)
{
writel(0xffffffff, base + CCM_CCGR0);
writel(0xffffffff, base + CCM_CCGR1);
@@ -191,11 +189,10 @@ static void __init mx5_clocks_common_init(void __iomem *base, unsigned long rate
writel(0xffffffff, base + CCM_CCGR6);
writel(0xffffffff, base + CCM_CCGR7);
- clks[IMX5_CLK_DUMMY] = clk_fixed("dummy", 0);
- clks[IMX5_CLK_CKIL] = clk_fixed("ckil", rate_ckil);
- clks[IMX5_CLK_OSC] = clk_fixed("osc", rate_osc);
- clks[IMX5_CLK_CKIH1] = clk_fixed("ckih1", rate_ckih1);
- clks[IMX5_CLK_CKIH2] = clk_fixed("ckih2", rate_ckih2);
+ if (!IS_ENABLED(COMMON_CLK_OF_PROVIDER) || !dev->device_node) {
+ clks[IMX5_CLK_CKIL] = clk_fixed("ckil", 32768);
+ clks[IMX5_CLK_OSC] = clk_fixed("osc", 24000000);
+ }
clks[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", base + CCM_CCSR, 9, 1,
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -273,14 +270,13 @@ static void mx51_clocks_ipu_init(void __iomem *regs)
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX51_IPU_BASE_ADDR, "di1");
}
-int __init mx51_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
- unsigned long rate_ckih1, unsigned long rate_ckih2)
+int __init mx51_clocks_init(struct device_d *dev, void __iomem *regs)
{
clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX51_PLL1_BASE_ADDR);
clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX51_PLL2_BASE_ADDR);
clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX51_PLL3_BASE_ADDR);
- mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+ mx5_clocks_common_init(dev, regs);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX51_UART2_BASE_ADDR, NULL);
@@ -314,7 +310,7 @@ static int imx51_ccm_probe(struct device_d *dev)
if (IS_ERR(regs))
return PTR_ERR(regs);
- mx51_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */
+ mx51_clocks_init(dev, regs);
return 0;
}
@@ -359,15 +355,14 @@ static void mx53_clocks_ipu_init(void __iomem *regs)
clkdev_add_physbase(clks[IMX5_CLK_IPU_DI1_SEL], MX53_IPU_BASE_ADDR, "di1");
}
-int __init mx53_clocks_init(void __iomem *regs, unsigned long rate_ckil, unsigned long rate_osc,
- unsigned long rate_ckih1, unsigned long rate_ckih2)
+int __init mx53_clocks_init(struct device_d *dev, void __iomem *regs)
{
clks[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", (void *)MX53_PLL1_BASE_ADDR);
clks[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", (void *)MX53_PLL2_BASE_ADDR);
clks[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", (void *)MX53_PLL3_BASE_ADDR);
clks[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", (void *)MX53_PLL4_BASE_ADDR);
- mx5_clocks_common_init(regs, rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
+ mx5_clocks_common_init(dev, regs);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART1_BASE_ADDR, NULL);
clkdev_add_physbase(clks[IMX5_CLK_UART_ROOT], MX53_UART2_BASE_ADDR, NULL);
@@ -401,7 +396,7 @@ static int imx53_ccm_probe(struct device_d *dev)
regs = dev_request_mem_region(dev, 0);
- mx53_clocks_init(regs, 32768, 24000000, 22579200, 0); /* FIXME */
+ mx53_clocks_init(dev, regs);
return 0;
}
diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c
index 3bc59497a8..dccf0a8c20 100644
--- a/arch/arm/mach-imx/clk-imx6.c
+++ b/arch/arm/mach-imx/clk-imx6.c
@@ -21,6 +21,7 @@
#include <mach/imx6-regs.h>
#include <mach/revision.h>
#include <mach/imx6.h>
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include "clk.h"
@@ -55,44 +56,8 @@
#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
-enum mx6q_clks {
- dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
- pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
- pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
- periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
- esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
- gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
- ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
- ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
- ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
- usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
- emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
- periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
- asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
- gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
- ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
- ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
- ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
- usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
- emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
- mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
- can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
- esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
- hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
- ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
- mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
- gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
- ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
- usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
- pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
- ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
- sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
- usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
- spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
- lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, enfc_gate, clk_max,
-};
-
-static struct clk *clks[clk_max];
+static struct clk *clks[IMX6QDL_CLK_END];
+static struct clk_onecell_data clk_data;
static const char *step_sels[] = {
"osc",
@@ -144,7 +109,7 @@ static const char *enfc_sels[] = {
"pll2_pfd2_396m",
};
-static const char *emi_sels[] = {
+static const char *eim_sels[] = {
"axi",
"pll3_usb_otg",
"pll2_pfd2_396m",
@@ -256,65 +221,56 @@ static struct clk_div_table video_div_table[] = {
static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb)
{
- clks[pll5_post_div] = imx_clk_divider_table("pll5_post_div", "pll5_video", anab + 0xa0, 19, 2, post_div_table);
- clks[pll5_video_div] = imx_clk_divider_table("pll5_video_div", "pll5_post_div", anab + 0x170, 30, 2, video_div_table);
-
- clks[ipu1_sel] = imx_clk_mux("ipu1_sel", cb + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
- clks[ipu2_sel] = imx_clk_mux("ipu2_sel", cb + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
- clks[ldb_di0_sel] = imx_clk_mux_p("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
- clks[ldb_di1_sel] = imx_clk_mux_p("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
- clks[ipu1_di0_pre_sel] = imx_clk_mux_p("ipu1_di0_pre_sel", cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
- clks[ipu1_di1_pre_sel] = imx_clk_mux_p("ipu1_di1_pre_sel", cb + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
- clks[ipu2_di0_pre_sel] = imx_clk_mux_p("ipu2_di0_pre_sel", cb + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
- clks[ipu2_di1_pre_sel] = imx_clk_mux_p("ipu2_di1_pre_sel", cb + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
- clks[ipu1_di0_sel] = imx_clk_mux_p("ipu1_di0_sel", cb + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
- clks[ipu1_di1_sel] = imx_clk_mux_p("ipu1_di1_sel", cb + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
- clks[ipu2_di0_sel] = imx_clk_mux_p("ipu2_di0_sel", cb + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
- clks[ipu2_di1_sel] = imx_clk_mux_p("ipu2_di1_sel", cb + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
-
- clks[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", cb + 0x3c, 11, 3);
- clks[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", cb + 0x3c, 16, 3);
- clks[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
- clks[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1);
- clks[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
- clks[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1);
- clks[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", cb + 0x34, 3, 3);
- clks[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", cb + 0x34, 12, 3);
- clks[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3);
- clks[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", cb + 0x38, 12, 3);
-
- clkdev_add_physbase(clks[ipu1_podf], MX6_IPU1_BASE_ADDR, "bus");
- clkdev_add_physbase(clks[ipu1_di0_sel], MX6_IPU1_BASE_ADDR, "di0");
- clkdev_add_physbase(clks[ipu1_di1_sel], MX6_IPU1_BASE_ADDR, "di1");
- clkdev_add_physbase(clks[ipu2_podf], MX6_IPU2_BASE_ADDR, "bus");
- clkdev_add_physbase(clks[ipu2_di0_sel], MX6_IPU2_BASE_ADDR, "di0");
- clkdev_add_physbase(clks[ipu2_di1_sel], MX6_IPU2_BASE_ADDR, "di1");
-
- clkdev_add_physbase(clks[ldb_di0_sel], 0x020e0008, "di0_pll");
- clkdev_add_physbase(clks[ldb_di1_sel], 0x020e0008, "di1_pll");
- clkdev_add_physbase(clks[ipu1_di0_sel], 0x020e0008, "di0_sel");
- clkdev_add_physbase(clks[ipu1_di1_sel], 0x020e0008, "di1_sel");
- clkdev_add_physbase(clks[ipu2_di0_sel], 0x020e0008, "di2_sel");
- clkdev_add_physbase(clks[ipu2_di1_sel], 0x020e0008, "di3_sel");
- clkdev_add_physbase(clks[ldb_di0], 0x020e0008, "di0");
- clkdev_add_physbase(clks[ldb_di1], 0x020e0008, "di1");
- clkdev_add_physbase(clks[ahb], 0x00120000, "iahb");
- clkdev_add_physbase(clks[pll3_pfd1_540m], 0x00120000, "isfr");
-
- clk_set_parent(clks[ipu1_di0_sel], clks[ipu1_di0_pre]);
- clk_set_parent(clks[ipu1_di1_sel], clks[ipu1_di1_pre]);
- clk_set_parent(clks[ipu2_di0_sel], clks[ipu2_di0_pre]);
- clk_set_parent(clks[ipu2_di1_sel], clks[ipu2_di1_pre]);
-
- clk_set_parent(clks[ipu1_di0_pre_sel], clks[pll5_video_div]);
- clk_set_parent(clks[ipu1_di1_pre_sel], clks[pll5_video_div]);
- clk_set_parent(clks[ipu2_di0_pre_sel], clks[pll5_video_div]);
- clk_set_parent(clks[ipu2_di1_pre_sel], clks[pll5_video_div]);
+ clks[IMX6QDL_CLK_PLL5_POST_DIV] = imx_clk_divider_table("pll5_post_div", "pll5_video", anab + 0xa0, 19, 2, post_div_table);
+ clks[IMX6QDL_CLK_PLL5_VIDEO_DIV] = imx_clk_divider_table("pll5_video_div", "pll5_post_div", anab + 0x170, 30, 2, video_div_table);
+
+ clks[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", cb + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
+ clks[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", cb + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
+ clks[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_p("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
+ clks[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
+ clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_p("ipu1_di0_pre_sel", cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+ clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_p("ipu1_di1_pre_sel", cb + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+ clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_p("ipu2_di0_pre_sel", cb + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+ clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_p("ipu2_di1_pre_sel", cb + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+ clks[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_p("ipu1_di0_sel", cb + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
+ clks[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_p("ipu1_di1_sel", cb + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
+ clks[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_p("ipu2_di0_sel", cb + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
+ clks[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_p("ipu2_di1_sel", cb + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
+
+ clks[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", cb + 0x3c, 11, 3);
+ clks[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", cb + 0x3c, 16, 3);
+ clks[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+ clks[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1);
+ clks[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+ clks[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1);
+ clks[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", cb + 0x34, 3, 3);
+ clks[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", cb + 0x34, 12, 3);
+ clks[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3);
+ clks[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", cb + 0x38, 12, 3);
+
+ clks[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", cb + 0x74, 0);
+ clks[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", cb + 0x74, 2);
+ clks[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", cb + 0x74, 4);
+ clks[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", cb + 0x74, 6);
+ clks[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", cb + 0x74, 8);
+ clks[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", cb + 0x74, 12);
+ clks[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", cb + 0x74, 14);
+ clks[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", cb + 0x74, 10);
+
+ clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_SEL], clks[IMX6QDL_CLK_IPU1_DI0_PRE]);
+ clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_SEL], clks[IMX6QDL_CLK_IPU1_DI1_PRE]);
+ clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_SEL], clks[IMX6QDL_CLK_IPU2_DI0_PRE]);
+ clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_SEL], clks[IMX6QDL_CLK_IPU2_DI1_PRE]);
+
+ clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+ clk_set_parent(clks[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+ clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+ clk_set_parent(clks[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
if ((imx_silicon_revision() != IMX_CHIP_REV_1_0) ||
cpu_is_mx6dl()) {
- clk_set_parent(clks[ldb_di0_sel], clks[pll5_video_div]);
- clk_set_parent(clks[ldb_di1_sel], clks[pll5_video_div]);
+ clk_set_parent(clks[IMX6QDL_CLK_LDB_DI0_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
+ clk_set_parent(clks[IMX6QDL_CLK_LDB_DI1_SEL], clks[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
}
}
@@ -322,9 +278,6 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb)
static int imx6_ccm_probe(struct device_d *dev)
{
void __iomem *base, *anatop_base, *ccm_base;
- unsigned long ckil_rate = 32768;
- unsigned long ckih_rate = 0;
- unsigned long osc_rate = 24000000;
anatop_base = (void *)MX6_ANATOP_BASE_ADDR;
ccm_base = dev_request_mem_region(dev, 0);
@@ -333,126 +286,129 @@ static int imx6_ccm_probe(struct device_d *dev)
base = anatop_base;
- clks[dummy] = clk_fixed("dummy", 0);
- clks[ckil] = clk_fixed("ckil", ckil_rate);
- clks[ckih] = clk_fixed("ckih", ckih_rate);
- clks[osc] = clk_fixed("osc", osc_rate);
-
/* type name parent_name base div_mask */
- clks[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
- clks[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
- clks[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
- clks[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
- clks[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
- clks[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
- clks[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
- clks[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
+ clks[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
+ clks[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
+ clks[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
+ clks[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
+ clks[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
+ clks[IMX6QDL_CLK_PLL8_MLB] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
+ clks[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
+ clks[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
- clks[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
- clks[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
+ clks[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
+ clks[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
- clks[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
- clks[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
- clks[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
- clks[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+ clks[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
+ clks[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
+ clks[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
+ clks[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
- clks[enet_ref] = imx_clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table);
+ clks[IMX6QDL_CLK_ENET_REF] = imx_clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table);
/* name parent_name reg idx */
- clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
- clks[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
- clks[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
- clks[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
- clks[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
- clks[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
- clks[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
+ clks[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
+ clks[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
+ clks[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
+ clks[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
+ clks[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
+ clks[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
+ clks[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
/* name parent_name mult div */
- clks[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
- clks[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
- clks[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
- clks[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
- clks[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
+ clks[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
+ clks[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
+ clks[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
+ clks[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
+ clks[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
base = ccm_base;
/* name reg shift width parent_names num_parents */
- clks[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
- clks[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
- clks[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
- clks[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
- clks[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
- clks[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
- clks[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
- clks[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
- clks[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
- clks[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
- clks[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
- clks[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
- clks[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
- clks[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
- clks[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
- clks[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
+ clks[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
+ clks[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
+ clks[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
+ clks[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
+ clks[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
+ clks[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
+ clks[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
+ clks[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+ clks[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+ clks[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+ clks[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+ clks[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
+ clks[IMX6QDL_CLK_EIM_SEL] = imx_clk_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels));
+ clks[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_sels, ARRAY_SIZE(eim_sels));
+ clks[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
+ clks[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
/* name reg shift width busy: reg, shift parent_names num_parents */
- clks[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
- clks[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
-
- clks[enfc_gate] = imx_clk_gate2("enfc_gate", "enfc_sel", base + 0x70, 14);
+ clks[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
+ clks[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
/* name parent_name reg shift width */
- clks[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
- clks[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
- clks[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
- clks[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
- clks[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
- clks[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
- clks[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
- clks[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
- clks[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
- clks[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
- clks[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
- clks[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_gate", base + 0x2c, 18, 3);
- clks[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
- clks[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3);
- clks[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3);
- clks[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
+ clks[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
+ clks[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
+ clks[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
+ clks[IMX6QDL_CLK_IPG_PER] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
+ clks[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
+ clks[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
+ clks[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
+ clks[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
+ clks[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
+ clks[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
+ clks[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
+ clks[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
+ clks[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
+ clks[IMX6QDL_CLK_EIM_PODF] = imx_clk_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3);
+ clks[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
+ clks[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
/* name parent_name reg shift width busy: reg, shift */
- clks[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
- clks[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
- clks[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
- clks[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
- clks[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
-
- clkdev_add_physbase(clks[uart_serial_podf], MX6_UART1_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[uart_serial_podf], MX6_UART2_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[uart_serial_podf], MX6_UART3_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[uart_serial_podf], MX6_UART4_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[uart_serial_podf], MX6_UART5_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI1_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI2_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI3_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI4_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ecspi_root], MX6_ECSPI5_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ipg_per], MX6_GPT_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ipg], MX6_ENET_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ipg], MX6_OCOTP_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[usdhc1_podf], MX6_USDHC1_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[usdhc2_podf], MX6_USDHC2_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[usdhc3_podf], MX6_USDHC3_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[usdhc4_podf], MX6_USDHC4_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ipg_per], MX6_I2C1_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ipg_per], MX6_I2C2_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ipg_per], MX6_I2C3_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ahb], MX6_SATA_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[usbphy1], MX6_USBPHY1_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[usbphy2], MX6_USBPHY2_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[enfc_podf], MX6_GPMI_BASE_ADDR, NULL);
- clkdev_add_physbase(clks[ipg_per], MX6_PWM1_BASE_ADDR, "per");
- clkdev_add_physbase(clks[ipg_per], MX6_PWM2_BASE_ADDR, "per");
- clkdev_add_physbase(clks[ipg_per], MX6_PWM3_BASE_ADDR, "per");
- clkdev_add_physbase(clks[ipg_per], MX6_PWM4_BASE_ADDR, "per");
+ clks[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
+ clks[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
+ clks[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
+ clks[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
+ clks[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
+
+ /* name parent_name reg shift */
+ clks[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
+ clks[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
+ clks[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
+ clks[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
+ clks[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
+ if (cpu_is_mx6dl())
+ clks[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
+ else
+ clks[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
+ clks[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
+ clks[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
+ clks[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
+ clks[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
+ clks[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
+ clks[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
+ clks[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
+ clks[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
+ clks[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
+ clks[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
+ clks[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
+ clks[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
+ clks[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
+ clks[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
+ clks[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
+ clks[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
+ clks[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
+ clks[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
+ clks[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
+ clks[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
+ clks[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
+ clks[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
+ clks[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
+ clks[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
+ clks[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
+ clks[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
+ clks[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
+ clks[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
imx6_add_video_clks(anatop_base, ccm_base);
@@ -469,9 +425,13 @@ static int imx6_ccm_probe(struct device_d *dev)
writel(0xffff3fff, ccm_base + CCGR6); /* gate VPU */
writel(0xffffffff, ccm_base + CCGR7);
- clk_enable(clks[pll6_enet]);
- clk_enable(clks[sata_ref_100m]);
- clk_enable(clks[enfc_podf]);
+ clk_data.clks = clks;
+ clk_data.clk_num = IMX6QDL_CLK_END;
+ of_clk_add_provider(dev->device_node, of_clk_src_onecell_get, &clk_data);
+
+ clk_enable(clks[IMX6QDL_CLK_PLL6_ENET]);
+ clk_enable(clks[IMX6QDL_CLK_SATA_REF_100M]);
+ clk_enable(clks[IMX6QDL_CLK_ENFC_PODF]);
return 0;
}
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index c6479a0e54..0a71db66d7 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -480,7 +480,7 @@ upper_or_coalesced_range(unsigned long base0, unsigned long size0,
}
}
-void __naked __noreturn imx1_barebox_entry(void *boarddata)
+void __noreturn imx1_barebox_entry(void *boarddata)
{
unsigned long base, size;
@@ -493,7 +493,7 @@ void __naked __noreturn imx1_barebox_entry(void *boarddata)
barebox_arm_entry(base, size, boarddata);
}
-void __naked __noreturn imx25_barebox_entry(void *boarddata)
+void __noreturn imx25_barebox_entry(void *boarddata)
{
unsigned long base, size;
@@ -506,7 +506,7 @@ void __naked __noreturn imx25_barebox_entry(void *boarddata)
barebox_arm_entry(base, size, boarddata);
}
-void __naked __noreturn imx27_barebox_entry(void *boarddata)
+void __noreturn imx27_barebox_entry(void *boarddata)
{
unsigned long base, size;
@@ -521,7 +521,7 @@ void __naked __noreturn imx27_barebox_entry(void *boarddata)
barebox_arm_entry(base, size, boarddata);
}
-void __naked __noreturn imx31_barebox_entry(void *boarddata)
+void __noreturn imx31_barebox_entry(void *boarddata)
{
unsigned long base, size;
@@ -536,7 +536,7 @@ void __naked __noreturn imx31_barebox_entry(void *boarddata)
barebox_arm_entry(base, size, boarddata);
}
-void __naked __noreturn imx35_barebox_entry(void *boarddata)
+void __noreturn imx35_barebox_entry(void *boarddata)
{
unsigned long base, size;
@@ -551,7 +551,7 @@ void __naked __noreturn imx35_barebox_entry(void *boarddata)
barebox_arm_entry(base, size, boarddata);
}
-void __naked __noreturn imx51_barebox_entry(void *boarddata)
+void __noreturn imx51_barebox_entry(void *boarddata)
{
unsigned long base, size;
@@ -564,7 +564,7 @@ void __naked __noreturn imx51_barebox_entry(void *boarddata)
barebox_arm_entry(base, size, boarddata);
}
-void __naked __noreturn imx53_barebox_entry(void *boarddata)
+void __noreturn imx53_barebox_entry(void *boarddata)
{
unsigned long base, size;
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 28d44da938..468a9280c7 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -128,14 +128,14 @@
#define ESDCFGx_tRC_16 0x0000000f
#ifndef __ASSEMBLY__
-void __naked __noreturn imx1_barebox_entry(void *boarddata);
-void __naked __noreturn imx25_barebox_entry(void *boarddata);
-void __naked __noreturn imx27_barebox_entry(void *boarddata);
-void __naked __noreturn imx31_barebox_entry(void *boarddata);
-void __naked __noreturn imx35_barebox_entry(void *boarddata);
-void __naked __noreturn imx51_barebox_entry(void *boarddata);
-void __naked __noreturn imx53_barebox_entry(void *boarddata);
-void __naked __noreturn imx6_barebox_entry(void *boarddata);
+void __noreturn imx1_barebox_entry(void *boarddata);
+void __noreturn imx25_barebox_entry(void *boarddata);
+void __noreturn imx27_barebox_entry(void *boarddata);
+void __noreturn imx31_barebox_entry(void *boarddata);
+void __noreturn imx35_barebox_entry(void *boarddata);
+void __noreturn imx51_barebox_entry(void *boarddata);
+void __noreturn imx53_barebox_entry(void *boarddata);
+void __noreturn imx6_barebox_entry(void *boarddata);
void imx_esdctl_disable(void);
#endif