Merge branch 'for-next/tegra'

7 files changed, 98 insertions, 0 deletions

diff --git a/arch/arm/configs/tegra_v7_defconfig b/arch/arm/configs/tegra_v7_defconfig
index 677a955dac..831c13889f 100644
--- a/arch/arm/configs/tegra_v7_defconfig
+++ b/arch/arm/configs/tegra_v7_defconfig
@@ -25,3 +25,5 @@ CONFIG_CMD_TIMEOUT=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_CLK=y
 CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_MCI=y
+CONFIG_MCI_TEGRA=y
diff --git a/arch/arm/dts/tegra20-colibri-iris.dts b/arch/arm/dts/tegra20-colibri-iris.dts
index 804750e421..6b4ee00fd3 100644
--- a/arch/arm/dts/tegra20-colibri-iris.dts
+++ b/arch/arm/dts/tegra20-colibri-iris.dts
@@ -29,4 +29,9 @@
 			};
 		};
 	};
+
+	sdhci@c8000600 {
+		status = "okay";
+		bus-width = <4>;
+	};
 };
diff --git a/arch/arm/dts/tegra20-colibri.dtsi b/arch/arm/dts/tegra20-colibri.dtsi
index 3644e7de4e..1ae5375e94 100644
--- a/arch/arm/dts/tegra20-colibri.dtsi
+++ b/arch/arm/dts/tegra20-colibri.dtsi
@@ -187,4 +187,8 @@
 			};
 		};
 	};
+
+	sdhci@c8000600 {
+		cd-gpios = <&gpio 23 0>; /* gpio PC7 */
+	};
 };
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index f63ead89db..2b333f5774 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -46,4 +46,36 @@
 		compatible = "nvidia,tegra20-pmc";
 		reg = <0x7000e400 0x400>;
 	};
+
+	sdhci@c8000000 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000000 0x200>;
+		interrupts = <0 14 0x04>;
+		clocks = <&tegra_car 14>;
+		status = "disabled";
+	};
+
+	sdhci@c8000200 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000200 0x200>;
+		interrupts = <0 15 0x04>;
+		clocks = <&tegra_car 9>;
+		status = "disabled";
+	};
+
+	sdhci@c8000400 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000400 0x200>;
+		interrupts = <0 19 0x04>;
+		clocks = <&tegra_car 69>;
+		status = "disabled";
+	};
+
+	sdhci@c8000600 {
+		compatible = "nvidia,tegra20-sdhci";
+		reg = <0xc8000600 0x200>;
+		interrupts = <0 31 0x04>;
+		clocks = <&tegra_car 15>;
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/mach-tegra/include/mach/tegra20-car.h b/arch/arm/mach-tegra/include/mach/tegra20-car.h
index d4cb2387f3..64873d79b9 100644
--- a/arch/arm/mach-tegra/include/mach/tegra20-car.h
+++ b/arch/arm/mach-tegra/include/mach/tegra20-car.h
@@ -46,6 +46,38 @@
 #define CRC_CLK_OUT_ENB_L_AC97		(1 << 3)
 #define CRC_CLK_OUT_ENB_L_CPU		(1 << 0)
 
+#define CRC_CCLK_BURST_POLICY		0x020
+#define CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT	28
+#define CRC_CCLK_BURST_POLICY_SYS_STATE_FIQ	8
+#define CRC_CCLK_BURST_POLICY_SYS_STATE_IRQ	4
+#define CRC_CCLK_BURST_POLICY_SYS_STATE_RUN	2
+#define CRC_CCLK_BURST_POLICY_SYS_STATE_IDLE	1
+#define CRC_CCLK_BURST_POLICY_SYS_STATE_STDBY	0
+#define CRC_CCLK_BURST_POLICY_FIQ_SRC_SHIFT	12
+#define CRC_CCLK_BURST_POLICY_IRQ_SRC_SHIFT	8
+#define CRC_CCLK_BURST_POLICY_RUN_SRC_SHIFT	4
+#define CRC_CCLK_BURST_POLICY_IDLE_SRC_SHIFT	0
+#define CRC_CCLK_BURST_POLICY_SRC_CLKM		0
+#define CRC_CCLK_BURST_POLICY_SRC_PLLC_OUT0	1
+#define CRC_CCLK_BURST_POLICY_SRC_CLKS		2
+#define CRC_CCLK_BURST_POLICY_SRC_PLLM_OUT0	3
+#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT0	4
+#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT4	5
+#define CRC_CCLK_BURST_POLICY_SRC_PLLP_OUT3	6
+#define CRC_CCLK_BURST_POLICY_SRC_CLKD		7
+#define CRC_CCLK_BURST_POLICY_SRC_PLLX_OUT0	8
+
+#define CRC_SUPER_CCLK_DIV		0x024
+#define CRC_SUPER_CDIV_ENB		(1 << 31)
+#define CRC_SUPER_CDIV_DIS_FROM_COP_FIQ	(1 << 27)
+#define CRC_SUPER_CDIV_DIS_FROM_CPU_FIQ	(1 << 26)
+#define CRC_SUPER_CDIV_DIS_FROM_COP_IRQ	(1 << 25)
+#define CRC_SUPER_CDIV_DIS_FROM_CPU_IRQ	(1 << 24)
+#define CRC_SUPER_CDIV_DIVIDEND_SHIFT	8
+#define CRC_SUPER_CDIV_DIVIDEND_MASK	(0xff << CRC_SUPER_CDIV_DIVIDEND_SHIFT)
+#define CRC_SUPER_CDIV_DIVISOR_SHIFT	0
+#define CRC_SUPER_CDIV_DIVISOR_MASK	(0xff << CRC_SUPER_CDIV_DIVISOR_SHIFT)
+
 #define CRC_SCLK_BURST_POLICY		0x028
 #define CRC_SCLK_BURST_POLICY_SYS_STATE_SHIFT	28
 #define CRC_SCLK_BURST_POLICY_SYS_STATE_FIQ	8
@@ -53,6 +85,18 @@
 #define CRC_SCLK_BURST_POLICY_SYS_STATE_RUN	2
 #define CRC_SCLK_BURST_POLICY_SYS_STATE_IDLE	1
 #define CRC_SCLK_BURST_POLICY_SYS_STATE_STDBY	0
+#define CRC_SCLK_BURST_POLICY_FIQ_SRC_SHIFT	12
+#define CRC_SCLK_BURST_POLICY_IRQ_SRC_SHIFT	8
+#define CRC_SCLK_BURST_POLICY_RUN_SRC_SHIFT	4
+#define CRC_SCLK_BURST_POLICY_IDLE_SRC_SHIFT	0
+#define CRC_SCLK_BURST_POLICY_SRC_CLKM		0
+#define CRC_SCLK_BURST_POLICY_SRC_PLLC_OUT1	1
+#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT4	2
+#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT3	3
+#define CRC_SCLK_BURST_POLICY_SRC_PLLP_OUT2	4
+#define CRC_SCLK_BURST_POLICY_SRC_CLKD		5
+#define CRC_SCLK_BURST_POLICY_SRC_CLKS		6
+#define CRC_SCLK_BURST_POLICY_SRC_PLLM_OUT1	7
 
 #define CRC_SUPER_SCLK_DIV		0x02c
 #define CRC_SUPER_SDIV_ENB		(1 << 31)
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c
index 6cabdb3b92..2c2d6fc626 100644
--- a/arch/arm/mach-tegra/tegra_avp_init.c
+++ b/arch/arm/mach-tegra/tegra_avp_init.c
@@ -103,6 +103,8 @@ static void init_pllx(void)
 		    CRC_OSC_CTRL_OSC_FREQ_MASK) >> CRC_OSC_CTRL_OSC_FREQ_SHIFT;
 
 	conf = &pllx_config_table[chiptype][osc_freq];
+	/* we are not relocated yet - globals are a bit more tricky here */
+	conf = (struct pll_config *)((char *)conf - get_runtime_offset());
 
 	/* set PLL bypass and frequency parameters */
 	reg = CRC_PLLX_BASE_BYPASS;
diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c
index b3d59abd6b..5aad1dd65e 100644
--- a/arch/arm/mach-tegra/tegra_maincomplex_init.c
+++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c
@@ -20,6 +20,7 @@
 #include <asm/barebox-arm.h>
 #include <mach/lowlevel.h>
 #include <mach/tegra20-pmc.h>
+#include <mach/tegra20-car.h>
 
 void tegra_maincomplex_entry(void)
 {
@@ -27,6 +28,14 @@ void tegra_maincomplex_entry(void)
 
 	arm_cpu_lowlevel_init();
 
+	/* switch to PLLX */
+	writel(CRC_CCLK_BURST_POLICY_SYS_STATE_RUN <<
+	       CRC_CCLK_BURST_POLICY_SYS_STATE_SHIFT |
+	       CRC_CCLK_BURST_POLICY_SRC_PLLX_OUT0 <<
+	       CRC_CCLK_BURST_POLICY_RUN_SRC_SHIFT,
+	       TEGRA_CLK_RESET_BASE + CRC_CCLK_BURST_POLICY);
+	writel(CRC_SUPER_CDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_CCLK_DIV);
+
 	switch (tegra_get_chiptype()) {
 	case TEGRA20:
 		rambase = 0x0;