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| author | Sascha Hauer <s.hauer@pengutronix.de> | 2013-01-09 10:29:08 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-01-09 10:29:08 +0100 |
| commit | 8c46b854f77d13661d43b9b360b08fe2d7714e60 (patch) | |
| tree | 7348b8e3e2dc7b1680860283efc4dd87f0b751c4 /arch | |
| parent | 21a0fc1ce359bf8b4b340ce539d427834d7332fe (diff) | |
| parent | d1104e40a059481f3e04e5502bdc49594b44633e (diff) | |
| download | barebox-8c46b854f77d13661d43b9b360b08fe2d7714e60.tar.gz barebox-8c46b854f77d13661d43b9b360b08fe2d7714e60.tar.xz | |
Merge branch 'for-next/imx'
Diffstat (limited to 'arch')
39 files changed, 1455 insertions, 307 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 3bd645fbfa..478b0d8bc5 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -150,6 +150,7 @@ board-$(CONFIG_MACH_TINY210) := friendlyarm-tiny210 board-$(CONFIG_MACH_SABRELITE) := freescale-mx6-sabrelite board-$(CONFIG_MACH_TX53) := karo-tx53 board-$(CONFIG_MACH_GUF_VINCELL) := guf-vincell +board-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) := efika-mx-smartbook machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/boards/efika-mx-smartbook/Makefile b/arch/arm/boards/efika-mx-smartbook/Makefile new file mode 100644 index 0000000000..d08bb68a5c --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o +obj-y += flash_header.o +pbl-y += flash_header.o diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c new file mode 100644 index 0000000000..a455c55b8d --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/board.c @@ -0,0 +1,510 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <common.h> +#include <net.h> +#include <init.h> +#include <environment.h> +#include <mach/gpio.h> +#include <asm/armlinux.h> +#include <partition.h> +#include <notifier.h> +#include <fs.h> +#include <led.h> +#include <fcntl.h> +#include <nand.h> +#include <usb/ulpi.h> +#include <usb/chipidea-imx.h> +#include <spi/spi.h> +#include <mfd/mc13xxx.h> +#include <mfd/mc13892.h> +#include <asm/io.h> +#include <asm/mmu.h> +#include <mach/imx-nand.h> +#include <mach/spi.h> +#include <mach/generic.h> +#include <mach/imx5.h> +#include <mach/bbu.h> +#include <mach/iomux-mx51.h> +#include <mach/imx51-regs.h> +#include <mach/devices-imx51.h> +#include <mach/imx-flash-header.h> +#include <mach/revision.h> + +#define GPIO_EFIKA_SDHC1_WP IMX_GPIO_NR(1, 1) +#define GPIO_EFIKAMX_SDHC1_CD IMX_GPIO_NR(1, 0) +#define GPIO_EFIKASB_SDHC1_CD IMX_GPIO_NR(2, 27) +#define GPIO_EFIKASB_SDHC2_CD IMX_GPIO_NR(1, 8) +#define GPIO_EFIKASB_SDHC2_WP IMX_GPIO_NR(1, 7) + +#define GPIO_BACKLIGHT_POWER IMX_GPIO_NR(4, 12) +#define GPIO_BACKLIGHT_PWM IMX_GPIO_NR(1, 2) +#define GPIO_LVDS_POWER IMX_GPIO_NR(3, 7) +#define GPIO_LVDS_RESET IMX_GPIO_NR(3, 5) +#define GPIO_LVDS_ENABLE IMX_GPIO_NR(3, 12) +#define GPIO_LCD_ENABLE IMX_GPIO_NR(3, 13) + +#define GPIO_BLUETOOTH IMX_GPIO_NR(2, 11) +#define GPIO_WIFI_ENABLE IMX_GPIO_NR(2, 16) +#define GPIO_WIFI_RESET IMX_GPIO_NR(2, 10) +#define GPIO_HUB_RESET IMX_GPIO_NR(1, 5) +#define GPIO_SMSC3317_RESET IMX_GPIO_NR(2, 9) + +static iomux_v3_cfg_t efika_pads[] = { + /* ECSPI1 */ + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_GPIO1_6__GPIO1_6, + + /* ESDHC1 */ + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + MX51_PAD_GPIO1_1__GPIO1_1, + + /* USB HOST1 */ + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + MX51_PAD_USBH1_STP__GPIO1_27, + MX51_PAD_EIM_A16__GPIO2_10, + + /* USB HOST2 */ + MX51_PAD_EIM_D27__GPIO2_9, + MX51_PAD_GPIO1_5__GPIO1_5, + MX51_PAD_EIM_D16__USBH2_DATA0, + MX51_PAD_EIM_D17__USBH2_DATA1, + MX51_PAD_EIM_D18__USBH2_DATA2, + MX51_PAD_EIM_D19__USBH2_DATA3, + MX51_PAD_EIM_D20__USBH2_DATA4, + MX51_PAD_EIM_D21__USBH2_DATA5, + MX51_PAD_EIM_D22__USBH2_DATA6, + MX51_PAD_EIM_D23__USBH2_DATA7, + MX51_PAD_EIM_A24__USBH2_CLK, + MX51_PAD_EIM_A25__USBH2_DIR, + MX51_PAD_EIM_A26__GPIO2_20, + MX51_PAD_EIM_A27__USBH2_NXT, + + /* PATA */ + MX51_PAD_NANDF_WE_B__PATA_DIOW, + MX51_PAD_NANDF_RE_B__PATA_DIOR, + MX51_PAD_NANDF_ALE__PATA_BUFFER_EN, + MX51_PAD_NANDF_CLE__PATA_RESET_B, + MX51_PAD_NANDF_WP_B__PATA_DMACK, + MX51_PAD_NANDF_RB0__PATA_DMARQ, + MX51_PAD_NANDF_RB1__PATA_IORDY, + MX51_PAD_GPIO_NAND__PATA_INTRQ, + MX51_PAD_NANDF_CS2__PATA_CS_0, + MX51_PAD_NANDF_CS3__PATA_CS_1, + MX51_PAD_NANDF_CS4__PATA_DA_0, + MX51_PAD_NANDF_CS5__PATA_DA_1, + MX51_PAD_NANDF_CS6__PATA_DA_2, + MX51_PAD_NANDF_D15__PATA_DATA15, + MX51_PAD_NANDF_D14__PATA_DATA14, + MX51_PAD_NANDF_D13__PATA_DATA13, + MX51_PAD_NANDF_D12__PATA_DATA12, + MX51_PAD_NANDF_D11__PATA_DATA11, + MX51_PAD_NANDF_D10__PATA_DATA10, + MX51_PAD_NANDF_D9__PATA_DATA9, + MX51_PAD_NANDF_D8__PATA_DATA8, + MX51_PAD_NANDF_D7__PATA_DATA7, + MX51_PAD_NANDF_D6__PATA_DATA6, + MX51_PAD_NANDF_D5__PATA_DATA5, + MX51_PAD_NANDF_D4__PATA_DATA4, + MX51_PAD_NANDF_D3__PATA_DATA3, + MX51_PAD_NANDF_D2__PATA_DATA2, + MX51_PAD_NANDF_D1__PATA_DATA1, + MX51_PAD_NANDF_D0__PATA_DATA0, + + MX51_PAD_EIM_A22__GPIO2_16, /* WLAN enable (1 = on) */ + MX51_PAD_EIM_A17__GPIO2_11, + + /* I2C2 */ + MX51_PAD_KEY_COL4__I2C2_SCL, + MX51_PAD_KEY_COL5__I2C2_SDA, + + MX51_PAD_GPIO1_2__GPIO1_2, /* Backlight (should be pwm) (1 = on) */ + MX51_PAD_CSI2_D19__GPIO4_12, /* Backlight power (0 = on) */ + + MX51_PAD_DISPB2_SER_CLK__GPIO3_7, /* LVDS power (1 = on) */ + MX51_PAD_DISPB2_SER_DIN__GPIO3_5, /* LVDS reset (1 = reset) */ + MX51_PAD_CSI1_D8__GPIO3_12, /* LVDS enable (1 = enable) */ + MX51_PAD_CSI1_D9__GPIO3_13, /* LCD enable (1 = on) */ + + MX51_PAD_DI1_PIN12__GPIO3_1, /* WLAN switch (0 = on) */ + + MX51_PAD_GPIO1_4__WDOG1_WDOG_B, +}; + +static iomux_v3_cfg_t efikasb_pads[] = { + /* LEDs */ + MX51_PAD_EIM_CS0__GPIO2_25, + MX51_PAD_GPIO1_3__GPIO1_3, + + /* ESHC2 */ + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + MX51_PAD_GPIO1_7__GPIO1_7, + MX51_PAD_GPIO1_8__GPIO1_8, + + MX51_PAD_EIM_CS2__GPIO2_27, +}; + +static iomux_v3_cfg_t efikamx_pads[] = { + MX51_PAD_GPIO1_0__GPIO1_0, +}; + +/* + * Generally this should work on the Efika MX smarttop aswell, + * but I do not have the hardware to test it, so hardcode this + * for the smartbook for now. + */ +static inline int machine_is_efikasb(void) +{ + return 1; +} + +static int efikamx_mem_init(void) +{ + arm_add_mem_device("ram0", 0x90000000, SZ_512M); + + return 0; +} +mem_initcall(efikamx_mem_init); + +static int spi_0_cs[] = { IMX_GPIO_NR(4, 24), IMX_GPIO_NR(4, 25) }; + +static struct spi_imx_master spi_0_data = { + .chipselect = spi_0_cs, + .num_chipselect = ARRAY_SIZE(spi_0_cs), +}; + +static const struct spi_board_info efikamx_spi_board_info[] = { + { + .name = "mc13xxx-spi", + .max_speed_hz = 30 * 1000 * 1000, + .bus_num = 0, + .chip_select = 0, + }, { + .name = "m25p80", + .chip_select = 1, + .max_speed_hz = 20 * 1000 * 1000, + .bus_num = 0, + }, +}; + +static void efikamx_power_init(void) +{ + unsigned int val; + struct mc13xxx *mc; + + mc = mc13xxx_get(); + if (!mc) { + printf("could not get mc13892\n"); + return; + } + + /* Write needed to Power Gate 2 register */ + mc13xxx_reg_read(mc, MC13892_REG_POWER_MISC, &val); + val &= ~MC13892_POWER_MISC_PWGT2SPIEN; + mc13xxx_reg_write(mc, MC13892_REG_POWER_MISC, val); + + /* Externally powered */ + mc13xxx_reg_read(mc, MC13892_REG_CHARGE, &val); + val |= MC13782_CHARGE_ICHRG0 | MC13782_CHARGE_ICHRG1 | + MC13782_CHARGE_ICHRG2 | MC13782_CHARGE_ICHRG3 | + MC13782_CHARGE_CHGAUTOB; + mc13xxx_reg_write(mc, MC13892_REG_CHARGE, val); + + /* power up the system first */ + mc13xxx_reg_write(mc, MC13892_REG_POWER_MISC, + MC13892_POWER_MISC_PWUP); + + /* Set core voltage to 1.1V */ + mc13xxx_reg_read(mc, MC13892_REG_SW_0, &val); + val &= ~MC13892_SWx_SWx_VOLT_MASK; + val |= MC13892_SWx_SWx_1_100V; + mc13xxx_reg_write(mc, MC13892_REG_SW_0, val); + + /* Setup VCC (SW2) to 1.25 */ + mc13xxx_reg_read(mc, MC13892_REG_SW_1, &val); + val &= ~MC13892_SWx_SWx_VOLT_MASK; + val |= MC13892_SWx_SWx_1_250V; + mc13xxx_reg_write(mc, MC13892_REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + mc13xxx_reg_read(mc, MC13892_REG_SW_2, &val); + val &= ~MC13892_SWx_SWx_VOLT_MASK; + val |= MC13892_SWx_SWx_1_250V; + mc13xxx_reg_write(mc, MC13892_REG_SW_2, val); + udelay(50); + + /* Raise the core frequency to 800MHz */ + console_flush(); + imx51_init_lowlevel(800); + clock_notifier_call_chain(); + + /* Set switchers in Auto in NORMAL mode & STANDBY mode */ + /* Setup the switcher mode for SW1 & SW2*/ + mc13xxx_reg_read(mc, MC13892_REG_SW_4, &val); + val = (val & ~((MC13892_SWMODE_MASK << MC13892_SWMODE1_SHIFT) | + (MC13892_SWMODE_MASK << MC13892_SWMODE2_SHIFT))); + val |= (MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE1_SHIFT) | + (MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE2_SHIFT); + mc13xxx_reg_write(mc, MC13892_REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + mc13xxx_reg_read(mc, MC13892_REG_SW_5, &val); + val = (val & ~((MC13892_SWMODE_MASK << MC13892_SWMODE3_SHIFT) | + (MC13892_SWMODE_MASK << MC13892_SWMODE4_SHIFT))); + val |= (MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE3_SHIFT) | + (MC13892_SWMODE_AUTO_AUTO << MC13892_SWMODE4_SHIFT); + mc13xxx_reg_write(mc, MC13892_REG_SW_5, val); + + /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ + mc13xxx_reg_read(mc, MC13892_REG_SETTING_0, &val); + val &= ~(MC13892_SETTING_0_VCAM_MASK | + MC13892_SETTING_0_VGEN3_MASK | + MC13892_SETTING_0_VDIG_MASK); + val |= MC13892_SETTING_0_VDIG_1_8 | + MC13892_SETTING_0_VGEN3_1_8 | + MC13892_SETTING_0_VCAM_2_6; + mc13xxx_reg_write(mc, MC13892_REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + mc13xxx_reg_read(mc, MC13892_REG_SETTING_1, &val); + val &= ~(MC13892_SETTING_1_VVIDEO_MASK | + MC13892_SETTING_1_VSD_MASK | + MC13892_SETTING_1_VAUDIO_MASK); + val |= MC13892_SETTING_1_VSD_3_15 | + MC13892_SETTING_1_VAUDIO_3_0 | + MC13892_SETTING_1_VVIDEO_2_775 | + MC13892_SETTING_1_VGEN1_1_2 | + MC13892_SETTING_1_VGEN2_3_15; + mc13xxx_reg_write(mc, MC13892_REG_SETTING_1, val); + + /* Enable VGEN1, VGEN2, VDIG, VPLL */ + mc13xxx_reg_read(mc, MC13892_REG_MODE_0, &val); + val |= MC13892_MODE_0_VGEN1EN | + MC13892_MODE_0_VDIGEN | + MC13892_MODE_0_VGEN2EN | + MC13892_MODE_0_VPLLEN; + mc13xxx_reg_write(mc, MC13892_REG_MODE_0, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = MC13892_MODE_1_VGEN3CONFIG | + MC13892_MODE_1_VCAMCONFIG; + mc13xxx_reg_write(mc, MC13892_REG_MODE_1, val); + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = MC13892_MODE_1_VGEN3EN | + MC13892_MODE_1_VGEN3CONFIG | + MC13892_MODE_1_VCAMEN | + MC13892_MODE_1_VCAMCONFIG | + MC13892_MODE_1_VVIDEOEN | + MC13892_MODE_1_VAUDIOEN | + MC13892_MODE_1_VSDEN; + mc13xxx_reg_write(mc, MC13892_REG_MODE_1, val); + + mc13xxx_reg_read(mc, MC13892_REG_POWER_CTL2, &val); + val |= MC13892_POWER_CONTROL_2_WDIRESET; + mc13xxx_reg_write(mc, MC13892_REG_POWER_CTL2, val); + + udelay(2500); +} + +static struct esdhc_platform_data efikasb_sd2_data = { + .cd_gpio = GPIO_EFIKASB_SDHC2_CD, + .wp_gpio = GPIO_EFIKASB_SDHC2_WP, + .cd_type = ESDHC_CD_GPIO, + .wp_type = ESDHC_WP_GPIO, + .devname = "mmc_left", +}; + +static struct esdhc_platform_data efikamx_sd1_data = { + .cd_gpio = GPIO_EFIKAMX_SDHC1_CD, + .wp_gpio = GPIO_EFIKA_SDHC1_WP, + .cd_type = ESDHC_CD_GPIO, + .wp_type = ESDHC_WP_GPIO, +}; + +static struct esdhc_platform_data efikasb_sd1_data = { + .cd_gpio = GPIO_EFIKASB_SDHC1_CD, + .wp_gpio = GPIO_EFIKA_SDHC1_WP, + .cd_type = ESDHC_CD_GPIO, + .wp_type = ESDHC_WP_GPIO, + .devname = "mmc_back", +}; + +struct imxusb_platformdata efikamx_usbh1_pdata = { + .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI, + .mode = IMX_USB_MODE_HOST, +}; + +static int efikamx_usb_init(void) +{ + gpio_direction_output(GPIO_BLUETOOTH, 0); + gpio_direction_output(GPIO_WIFI_ENABLE, 1); + gpio_direction_output(GPIO_WIFI_RESET, 0); + gpio_direction_output(GPIO_SMSC3317_RESET, 0); + gpio_direction_output(GPIO_HUB_RESET, 0); + + mdelay(10); + + gpio_set_value(GPIO_HUB_RESET, 1); + gpio_set_value(GPIO_SMSC3317_RESET, 1); + gpio_set_value(GPIO_BLUETOOTH, 1); + gpio_set_value(GPIO_WIFI_RESET, 1); + + mxc_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__GPIO1_27); + gpio_set_value(IMX_GPIO_NR(1, 27), 1); + mdelay(1); + mxc_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP); + + if (machine_is_efikasb()) { + mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__GPIO2_20); + gpio_set_value(IMX_GPIO_NR(2, 20), 1); + mdelay(1); + mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__USBH2_STP); + } + + imx51_add_usbh1(&efikamx_usbh1_pdata); + + /* + * At least for the EfikaSB these do not seem to be interesting. + * The external ports are all connected to host1. + * + * imx51_add_usbotg(pdata); + * imx51_add_usbh2(pdate); + */ + + return 0; +} + +static struct gpio_led leds[] = { + { + .gpio = IMX_GPIO_NR(1, 3), + .active_low = 1, + .led.name = "mail", + }, { + .gpio = IMX_GPIO_NR(2, 25), + .led.name = "white", + }, +}; + +#define DCD_NAME static struct imx_dcd_entry dcd_entry + +#include "dcd-data.h" + +static int efikamx_devices_init(void) +{ + int i; + + mxc_iomux_v3_setup_multiple_pads(efika_pads, ARRAY_SIZE(efika_pads)); + if (machine_is_efikasb()) { + gpio_direction_output(GPIO_BACKLIGHT_POWER, 1); + mxc_iomux_v3_setup_multiple_pads(efikasb_pads, + ARRAY_SIZE(efikasb_pads)); + } else { + mxc_iomux_v3_setup_multiple_pads(efikamx_pads, + ARRAY_SIZE(efikamx_pads)); + } + + spi_register_board_info(efikamx_spi_board_info, + ARRAY_SIZE(efikamx_spi_board_info)); + imx51_add_spi0(&spi_0_data); + + efikamx_power_init(); + + if (machine_is_efikasb()) + imx51_add_mmc0(&efikasb_sd1_data); + else + imx51_add_mmc0(&efikamx_sd1_data); + + imx51_add_mmc1(&efikasb_sd2_data); + + for (i = 0; i < ARRAY_SIZE(leds); i++) + led_gpio_register(&leds[i]); + + imx51_add_i2c1(NULL); + + efikamx_usb_init(); + + imx51_add_pata(); + + writew(0x0, MX51_WDOG_BASE_ADDR + 0x8); + + imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc_left", + BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry), + 0); + + armlinux_set_bootparams((void *)0x90000100); + armlinux_set_architecture(2370); + armlinux_set_revision(0x5100 | imx_silicon_revision()); + + return 0; +} +device_initcall(efikamx_devices_init); + +static int efikamx_part_init(void) +{ + if (imx_bootsource() == bootsource_mmc) { + devfs_add_partition("mmc_left", 0x00000, 0x80000, + DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("mmc_left", 0x80000, 0x80000, + DEVFS_PARTITION_FIXED, "env0"); + } + + return 0; +} +late_initcall(efikamx_part_init); + +static iomux_v3_cfg_t efika_uart_pads[] = { + /* UART */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +}; + +static int efikamx_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(efika_uart_pads, + ARRAY_SIZE(efika_uart_pads)); + + imx51_add_uart0(); + + return 0; +} +console_initcall(efikamx_console_init); diff --git a/arch/arm/boards/efika-mx-smartbook/config.h b/arch/arm/boards/efika-mx-smartbook/config.h new file mode 100644 index 0000000000..143adf2552 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/config.h @@ -0,0 +1,17 @@ +/** + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/efika-mx-smartbook/dcd-data.h b/arch/arm/boards/efika-mx-smartbook/dcd-data.h new file mode 100644 index 0000000000..6795e19017 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/dcd-data.h @@ -0,0 +1,56 @@ +DCD_NAME[] = { + { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000000, }, + { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000005, }, + { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000005, }, + { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, + { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, + { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000005, }, + { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000005, }, + { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e5, }, + { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e5, }, + { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e5, }, + { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e5, }, + { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e4, }, + { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0xcaaaf6d0, }, + { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x333574aa, }, + { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x333574aa, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, + { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, +}; diff --git a/arch/arm/boards/efika-mx-smartbook/env/bin/lvds_init b/arch/arm/boards/efika-mx-smartbook/env/bin/lvds_init new file mode 100644 index 0000000000..692392cd6c --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/bin/lvds_init @@ -0,0 +1,22 @@ +#!/bin/sh + +# Initialize lvds and backlight in case your Kernel does not handle this... + +GPIO_BACKLIGHT_POWER=108 +GPIO_BACKLIGHT_PWM=2 +GPIO_LVDS_POWER=71 +GPIO_LVDS_RESET=69 +GPIO_LVDS_ENABLE=76 +GPIO_LCD_ENABLE=77 + +gpio_direction_output $GPIO_BACKLIGHT_PWM 0 +gpio_direction_output $GPIO_LVDS_RESET 1 +gpio_direction_output $GPIO_LVDS_POWER 1 +msleep 5 +gpio_direction_output $GPIO_LVDS_RESET 0 +msleep 5 +gpio_direction_output $GPIO_LVDS_ENABLE 1 +gpio_direction_output $GPIO_BACKLIGHT_POWER 0 +gpio_direction_output $GPIO_LCD_ENABLE 1 +msleep 300 +gpio_direction_output $GPIO_BACKLIGHT_PWM 1 diff --git a/arch/arm/boards/efika-mx-smartbook/env/boot/hd-internal b/arch/arm/boards/efika-mx-smartbook/env/boot/hd-internal new file mode 100644 index 0000000000..ccd0f69bb4 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/boot/hd-internal @@ -0,0 +1,17 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "internal harddisk" + exit +fi + +path="/mnt/internal-hd0.0" + +global.bootm.image="${path}/linuximage" + +oftree=${path}/oftree +if [ -f $oftree ]; then + global.bootm.oftree="$oftree" +fi + +global.linux.bootargs.dyn.root="root=/dev/sda2" diff --git a/arch/arm/boards/efika-mx-smartbook/env/boot/mmc-left b/arch/arm/boards/efika-mx-smartbook/env/boot/mmc-left new file mode 100644 index 0000000000..21935c6fff --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/boot/mmc-left @@ -0,0 +1,19 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "left MMC slot" + exit +fi + +path="/mnt/mmc-left.0" + +global.bootm.image="${path}/linuximage" + +oftree=${path}/oftree +if [ -f $oftree ]; then + global.bootm.oftree="$oftree" +fi + +# The rootdevice may actually be mmcblk1p2 if a card +# is inserted to the back MMC slot +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2" diff --git a/arch/arm/boards/efika-mx-smartbook/env/config b/arch/arm/boards/efika-mx-smartbook/env/config new file mode 100644 index 0000000000..46aff49088 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/config @@ -0,0 +1,29 @@ +#!/bin/sh + +# change network settings in /env/network/eth0 +# change mtd partition settings and automountpoints in /env/init/* + +#global.hostname= + +# set to false if you do not want to have colors +global.allow_color=true + +# user (used for network filenames) +global.user=none + +# timeout in seconds before the default boot entry is started +global.autoboot_timeout=1 + +# default boot entry (one of /env/boot/*) +# (if not overwritten here, the bootdevice barebox comes from +# is used) +#global.boot.default=net + +# base bootargs +global.linux.bootargs.base="console=ttymxc0,115200 console=tty1" + +# suitable for 800MHz +global linux.bootargs.lpj="lpj=3997696" + +# speed up booting by being more quiet +global linux.bootargs.quiet="quiet" diff --git a/arch/arm/boards/efika-mx-smartbook/env/init/automount b/arch/arm/boards/efika-mx-smartbook/env/init/automount new file mode 100644 index 0000000000..8cb5eaf792 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/init/automount @@ -0,0 +1,29 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +# automount nfs server example + +# internal harddisk /boot partition +mkdir -p /mnt/internal-hd0.0 +automount -d /mnt/internal-hd0.0 'mount /dev/ata0.0 /mnt/internal-hd0.0' + +# internal harddisk rootfs +mkdir -p /mnt/internal-hd0.1 +automount -d /mnt/internal-hd0.1 'mount /dev/ata0.1 /mnt/internal-hd0.1' + +# left SD card slot, first partition +mkdir -p /mnt/mmc-left.0 +automount -d /mnt/mmc-left.0 'mount /dev/mmc_left.0 /mnt/mmc-left.0' + +# back SD card slot, first partition +mkdir -p /mnt/mmc-back.0 +automount -d /mnt/mmc-back.0 'mount /dev/mmc_back.0 /mnt/mmc-back.0' diff --git a/arch/arm/boards/efika-mx-smartbook/env/init/bootsource b/arch/arm/boards/efika-mx-smartbook/env/init/bootsource new file mode 100644 index 0000000000..fb084696a3 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/init/bootsource @@ -0,0 +1,10 @@ +#!/bin/sh + +# by default pick kernel from MMC card if booting from +# it, otherwise default to boot from internal harddisk + +if [ $barebox_loc = mmc ]; then + global.boot.default=mmc-left +else + global.boot.default=hd-internal +fi diff --git a/arch/arm/boards/efika-mx-smartbook/env/init/config-board b/arch/arm/boards/efika-mx-smartbook/env/init/config-board new file mode 100644 index 0000000000..22993f9c29 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/init/config-board @@ -0,0 +1,9 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=efikasb +global.linux.bootargs.base="console=ttymxc0,115200" + +[ -f /env/config ] && /env/config diff --git a/arch/arm/boards/efika-mx-smartbook/env/network/eth0-discover b/arch/arm/boards/efika-mx-smartbook/env/network/eth0-discover new file mode 100644 index 0000000000..f8368a5ec6 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/env/network/eth0-discover @@ -0,0 +1,4 @@ +#!/bin/sh + +usb +sleep 3 diff --git a/arch/arm/boards/efika-mx-smartbook/flash_header.c b/arch/arm/boards/efika-mx-smartbook/flash_header.c new file mode 100644 index 0000000000..f3f1e4bfd5 --- /dev/null +++ b/arch/arm/boards/efika-mx-smartbook/flash_header.c @@ -0,0 +1,29 @@ +#include <common.h> +#include <mach/imx-flash-header.h> +#include <asm/barebox-arm-head.h> + +void __naked __flash_header_start go(void) +{ + barebox_arm_head(); +} + +#define DCD_NAME struct imx_dcd_entry __dcd_entry_section dcd_entry + +#include "dcd-data.h" + +#define APP_DEST 0x90000000 + +struct imx_flash_header __flash_header_section flash_header = { + .app_code_jump_vector = APP_DEST + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = APP_DEST, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof (dcd_entry), +}; + +unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE; + diff --git a/arch/arm/boards/pcm037/Makefile b/arch/arm/boards/pcm037/Makefile index fcfa40d3fe..859501ce92 100644 --- a/arch/arm/boards/pcm037/Makefile +++ b/arch/arm/boards/pcm037/Makefile @@ -16,6 +16,6 @@ # # -obj-y += lowlevel_init.o -pbl-y += lowlevel_init.o +obj-y += lowlevel.o +pbl-y += lowlevel.o obj-y += pcm037.o diff --git a/arch/arm/boards/pcm037/env/boot/nand-ubi b/arch/arm/boards/pcm037/env/boot/nand-ubi new file mode 100644 index 0000000000..67b0cb4afe --- /dev/null +++ b/arch/arm/boards/pcm037/env/boot/nand-ubi @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "nand (UBI)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/pcm037/env/config b/arch/arm/boards/pcm037/env/config deleted file mode 100644 index 569bfe4b68..0000000000 --- a/arch/arm/boards/pcm037/env/config +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/sh - -global.hostname=pcm037 -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" -rootfs_mtdblock_nor=3 - -nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" -rootfs_mtdblock_nand=7 -nand_device="mxc_nand" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/pcm037/env/init/config-board b/arch/arm/boards/pcm037/env/init/config-board new file mode 100644 index 0000000000..03f9e97fca --- /dev/null +++ b/arch/arm/boards/pcm037/env/init/config-board @@ -0,0 +1,7 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=pcm037 +global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/pcm037/env/init/mtdparts-nand b/arch/arm/boards/pcm037/env/init/mtdparts-nand new file mode 100644 index 0000000000..84220b77b3 --- /dev/null +++ b/arch/arm/boards/pcm037/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" +kernelname="mxc_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm037/env/init/mtdparts-nor b/arch/arm/boards/pcm037/env/init/mtdparts-nor new file mode 100644 index 0000000000..2ef6ead71a --- /dev/null +++ b/arch/arm/boards/pcm037/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" +kernelname="physmap-flash.0" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c new file mode 100644 index 0000000000..baf63a53b9 --- /dev/null +++ b/arch/arm/boards/pcm037/lowlevel.c @@ -0,0 +1,162 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <common.h> +#include <init.h> +#include <io.h> +#include <mach/imx-nand.h> +#include <asm/barebox-arm.h> +#include <asm/system.h> +#include <asm-generic/memory_layout.h> +#include <asm-generic/sections.h> +#include <asm/barebox-arm-head.h> +#include <mach/imx31-regs.h> +#include <mach/imx-pll.h> +#include <asm/barebox-arm-head.h> +#include <mach/esdctl.h> + +#ifdef CONFIG_NAND_IMX_BOOT +static void __bare_init __naked insdram(void) +{ + /* setup a stack to be able to call imx_nand_load_image() */ + arm_setup_stack(STACK_BASE + STACK_SIZE - 12); + + imx_nand_load_image(_text, barebox_image_size); + + board_init_lowlevel_return(); +} +#endif + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +void __bare_init __naked reset(void) +{ + uint32_t r; + volatile int v; +#ifdef CONFIG_NAND_IMX_BOOT + int i; + unsigned int *trg, *src; +#endif + common_reset(); + + writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); + + writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); + + for (v = 0; v < 0x4000; v++); + + writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + + MX31_CCM_CCMR); + writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, + MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); + + writel(MX31_PDR0_CSI_PODF(0xff1) | \ + MX31_PDR0_PER_PODF(7) | \ + MX31_PDR0_HSP_PODF(3) | \ + MX31_PDR0_NFC_PODF(5) | \ + MX31_PDR0_IPG_PODF(1) | \ + MX31_PDR0_MAX_PODF(3) | \ + MX31_PDR0_MCU_PODF(0), \ + MX31_CCM_BASE_ADDR + MX31_CCM_PDR0); + + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | + IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), + MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL); + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | + IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + + MX31_CCM_SPCTL); + + /* + * Configure IOMUXC + * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), + * 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) + * (behaviour copied by sha, source unknown) + */ + writel(0, 0x43fac26c); + writel(0, 0x43fac270); + writel(0, 0x43fac274); + + writel(0x1000, 0x43fac27c); + + for (r = 0x43fac284; r <= 0x43fac2dc; r += 4) + writel(0, r); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0xa0000000) + board_init_lowlevel_return(); + +#if defined CONFIG_PCM037_SDRAM_BANK0_128MB +#define ROWS0 ESDCTL0_ROW13 +#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB +#define ROWS0 ESDCTL0_ROW14 +#endif + writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00); + writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x12344321, MX31_CSD0_BASE_ADDR); + writel(0x12344321, MX31_CSD0_BASE_ADDR); + writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33); + writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000); + writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR); + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); + +#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE +#if defined CONFIG_PCM037_SDRAM_BANK1_128MB +#define ROWS1 ESDCTL0_ROW13 +#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB +#define ROWS1 ESDCTL0_ROW14 +#endif + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1); + writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00); + writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0x12344321, MX31_CSD1_BASE_ADDR); + writel(0x12344321, MX31_CSD1_BASE_ADDR); + writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33); + writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000); + writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR); + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); +#endif + +#ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); + if (r < MX31_NFC_BASE_ADDR || r > MX31_NFC_BASE_ADDR + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)MX31_NFC_BASE_ADDR; + trg = (unsigned int *)_text; + + /* Move ourselves out of NFC SRAM */ + for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ + r = (unsigned int)&insdram; + __asm__ __volatile__("mov pc, %0" : : "r"(r)); +#else + board_init_lowlevel_return(); +#endif +} diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S deleted file mode 100644 index 9560841bcb..0000000000 --- a/arch/arm/boards/pcm037/lowlevel_init.S +++ /dev/null @@ -1,170 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <mach/imx31-regs.h> -#include <mach/imx-pll.h> -#include <asm/barebox-arm-head.h> -#include <mach/esdctl.h> - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define writeb(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - strb r1, [r0]; - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - - .section ".text_bare_init","ax" - -.globl reset -reset: - - common_reset r0 - - writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR) - - writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) - - DELAY 0x40000 - - writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + - MX31_CCM_CCMR) - writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, - MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) - - writel(MX31_PDR0_CSI_PODF(0xff1) | \ - MX31_PDR0_PER_PODF(7) | \ - MX31_PDR0_HSP_PODF(3) | \ - MX31_PDR0_NFC_PODF(5) | \ - MX31_PDR0_IPG_PODF(1) | \ - MX31_PDR0_MAX_PODF(3) | \ - MX31_PDR0_MCU_PODF(0), \ - MX31_CCM_BASE_ADDR + MX31_CCM_PDR0) - - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | - IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), - MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL) - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | - IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + - MX31_CCM_SPCTL) - - /* Configure IOMUXC - * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) - * (behaviour copied by sha, source unknown) - */ - mov r1, #0; - ldr r0, =0x43FAC26C - str r1, [r0], #4 - str r1, [r0], #4 - str r1, [r0], #0x10 - - ldr r2, =0x43FAC2DC -clear_iomux: - str r1, [r0], #4 - cmp r0, r2 - bls clear_iomux - writel(0x1000, 0x43FAC27C )/* CS2 CSD0) */ - - /* Skip SDRAM initialization if we run from RAM */ - cmp pc, #0x80000000 - blo 1f - cmp pc, #0x90000000 - bhs 1f - - b board_init_lowlevel_return -1: - -#if defined CONFIG_PCM037_SDRAM_BANK0_128MB -#define ROWS0 ESDCTL0_ROW13 -#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB -#define ROWS0 ESDCTL0_ROW14 -#endif - writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) - writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0) - writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writel(0x12344321, MX31_CSD0_BASE_ADDR) - writel(0x12344321, MX31_CSD0_BASE_ADDR) - writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33) - writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) - writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR) - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) - -#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE -#if defined CONFIG_PCM037_SDRAM_BANK1_128MB -#define ROWS1 ESDCTL0_ROW13 -#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB -#define ROWS1 ESDCTL0_ROW14 -#endif - writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1) - writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) - writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) - writel(0x12344321, MX31_CSD1_BASE_ADDR) - writel(0x12344321, MX31_CSD1_BASE_ADDR) - writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) - writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33) - writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) - writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR) - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) -#endif - -#ifdef CONFIG_NAND_IMX_BOOT - ldr sp, =0x80f00000 /* Setup a temporary stack in SDRAM */ - - ldr r0, =MX31_NFC_BASE_ADDR /* start of NFC SRAM */ - ldr r2, =MX31_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */ - - /* skip NAND boot if not running from NFC space */ - cmp pc, r0 - blo ret - cmp pc, r2 - bhs ret - - /* Move ourselves out of NFC SRAM */ - ldr r1, =_text - -copy_loop: - ldmia r0!, {r3-r9} /* copy from source address [r0] */ - stmia r1!, {r3-r9} /* copy to target address [r1] */ - cmp r0, r2 /* until source end address [r2] */ - ble copy_loop - - ldr pc, =1f /* Jump to SDRAM */ -1: - b nand_boot /* Load barebox from NAND Flash */ -ret: -#endif /* CONFIG_NAND_IMX_BOOT */ - - b board_init_lowlevel_return - diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c index 68a6c8d92a..7894ff3bdb 100644 --- a/arch/arm/boards/pcm037/pcm037.c +++ b/arch/arm/boards/pcm037/pcm037.c @@ -163,6 +163,8 @@ static int imx31_devices_init(void) */ add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); + imx31_add_mmc0(NULL); + /* * Create partitions that should be * not touched by any regular user @@ -202,13 +204,49 @@ static int imx31_devices_init(void) device_initcall(imx31_devices_init); +static unsigned int pcm037_iomux[] = { + /* UART1 */ + MX31_PIN_RXD1__RXD1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + /* I2C */ + MX31_PIN_CSPI2_MOSI__SCL, + MX31_PIN_CSPI2_MISO__SDA, + MX31_PIN_CSPI2_SS2__I2C3_SDA, + MX31_PIN_CSPI2_SCLK__I2C3_SCL, + /* SDHC1 */ + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, + IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ + IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ + /* SPI1 */ + MX31_PIN_CSPI1_MOSI__MOSI, + MX31_PIN_CSPI1_MISO__MISO, + MX31_PIN_CSPI1_SCLK__SCLK, + MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI1_SS0__SS0, + MX31_PIN_CSPI1_SS1__SS1, + MX31_PIN_CSPI1_SS2__SS2, + /* UART2 */ + MX31_PIN_TXD2__TXD2, + MX31_PIN_RXD2__RXD2, + MX31_PIN_CTS2__CTS2, + MX31_PIN_RTS2__RTS2, + /* UART3 */ + MX31_PIN_CSPI3_MOSI__RXD3, + MX31_PIN_CSPI3_MISO__TXD3, + MX31_PIN_CSPI3_SCLK__RTS3, + MX31_PIN_CSPI3_SPI_RDY__CTS3, +}; + static int imx31_console_init(void) { - /* init gpios for serial port */ - imx_iomux_mode(MX31_PIN_RXD1__RXD1); - imx_iomux_mode(MX31_PIN_TXD1__TXD1); - imx_iomux_mode(MX31_PIN_CTS1__CTS1); - imx_iomux_mode(MX31_PIN_RTS1__RTS1); + imx_iomux_setup_multiple_pins(pcm037_iomux, ARRAY_SIZE(pcm037_iomux)); imx31_add_uart0(); return 0; diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c index 93a183988a..a50a1f2e97 100644 --- a/arch/arm/boards/pcm038/pcm970.c +++ b/arch/arm/boards/pcm038/pcm970.c @@ -21,34 +21,12 @@ #include <mach/weim.h> #include <mach/gpio.h> #include <mach/devices-imx27.h> -#include <usb/ulpi.h> +#include <usb/chipidea-imx.h> #define GPIO_IDE_POWER (GPIO_PORTE + 18) #define GPIO_IDE_PCOE (GPIO_PORTF + 7) #define GPIO_IDE_RESET (GPIO_PORTF + 10) -#ifdef CONFIG_USB -static void pcm970_usbh2_init(void) -{ - uint32_t temp; - - temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600); - temp &= ~((3 << 21) | 1); - temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); - writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600); - - temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584); - temp &= ~(3 << 30); - temp |= 2 << 30; - writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584); - - mdelay(10); - - if (!ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1)) - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); -} -#endif - #ifdef CONFIG_DISK_INTF_PLATFORM_IDE static struct resource pcm970_ide_resources[] = { { @@ -168,6 +146,11 @@ static void pcm970_mmc_init(void) imx27_add_mmc1(NULL); } +struct imxusb_platformdata pcm970_usbh2_pdata = { + .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI, + .mode = IMX_USB_MODE_HOST, +}; + static int pcm970_init(void) { int i; @@ -177,7 +160,7 @@ static int pcm970_init(void) PA1_PF_USBH2_DIR, PA2_PF_USBH2_DATA7, PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, + 4 | GPIO_PORTA | GPIO_GPIO | GPIO_OUT, PD19_AF_USBH2_DATA4, PD20_AF_USBH2_DATA3, PD21_AF_USBH2_DATA6, @@ -193,9 +176,14 @@ static int pcm970_init(void) /* Configure SJA1000 on cs4 */ imx27_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); -#ifdef CONFIG_USB - pcm970_usbh2_init(); -#endif + if (IS_ENABLED(CONFIG_USB)) { + /* Stop ULPI */ + gpio_direction_output(4, 1); + mdelay(1); + imx_gpio_mode(PA4_PF_USBH2_STP); + + imx27_add_usbh2(&pcm970_usbh2_pdata); + } #ifdef CONFIG_DISK_INTF_PLATFORM_IDE pcm970_ide_init(); diff --git a/arch/arm/configs/efika-mx-smartbook_defconfig b/arch/arm/configs/efika-mx-smartbook_defconfig new file mode 100644 index 0000000000..2ef33b448f --- /dev/null +++ b/arch/arm/configs/efika-mx-smartbook_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX51=y +CONFIG_MACH_EFIKA_MX_SMARTBOOK=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/efika-mx-smartbook/env/" +CONFIG_RESET_SOURCE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_LN=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_OFTREE_PROBE=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_CMD_WD=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y +CONFIG_NET_USB_SMSC95XX=y +CONFIG_DRIVER_SPI_IMX=y +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y +CONFIG_DISK_INTF_PLATFORM_IDE=y +CONFIG_DISK_PATA_IMX=y +CONFIG_USB=y +CONFIG_USB_IMX_CHIPIDEA=y +CONFIG_USB_EHCI=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_MFD_MC13XXX=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_TRIGGERS=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_IMX=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig index 5a527d56a9..7c630a59d2 100644 --- a/arch/arm/configs/pcm037_defconfig +++ b/arch/arm/configs/pcm037_defconfig @@ -11,25 +11,36 @@ CONFIG_MALLOC_SIZE=0x01000000 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y CONFIG_LONGHELP=y -CONFIG_GLOB=y CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y CONFIG_PARTITION=y CONFIG_PARTITION_DISK=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm037/env" +CONFIG_RESET_SOURCE=y CONFIG_CMD_EDIT=y CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y CONFIG_CMD_TIME=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_LN=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y @@ -37,23 +48,24 @@ CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set # CONFIG_CMD_BOOTU is not set CONFIG_CMD_RESET=y CONFIG_CMD_GO=y +CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y CONFIG_CMD_GPIO=y CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_SPI=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y CONFIG_NET=y CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y CONFIG_DRIVER_NET_SMC911X=y CONFIG_NET_USB=y CONFIG_NET_USB_ASIX=y @@ -65,5 +77,11 @@ CONFIG_NAND_IMX=y CONFIG_UBI=y CONFIG_USB=y CONFIG_USB_EHCI=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y CONFIG_ZLIB=y CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig index bab4002a6a..e2f5388d60 100644 --- a/arch/arm/configs/pcm038_defconfig +++ b/arch/arm/configs/pcm038_defconfig @@ -2,7 +2,6 @@ CONFIG_ARCH_IMX=y CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y CONFIG_ARCH_IMX27=y CONFIG_MACH_PCM038=y -CONFIG_IMX_CLKO=y CONFIG_AEABI=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y @@ -16,8 +15,6 @@ CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y -CONFIG_PARTITION=y -CONFIG_PARTITION_DISK=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm038/env" CONFIG_CMD_EDIT=y @@ -32,7 +29,6 @@ CONFIG_CMD_TIME=y CONFIG_CMD_ECHO_E=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_IOMEM=y -CONFIG_CMD_MTEST=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y @@ -40,16 +36,16 @@ CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set # CONFIG_CMD_BOOTU is not set CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_SPLASH=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_MAGICVAR=y CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SPLASH=y CONFIG_CMD_GPIO=y CONFIG_CMD_UNCOMPRESS=y CONFIG_NET=y @@ -68,8 +64,10 @@ CONFIG_NAND=y # CONFIG_NAND_ECC_HW_SYNDROME is not set CONFIG_NAND_IMX=y CONFIG_USB=y +CONFIG_USB_IMX_CHIPIDEA=y CONFIG_USB_EHCI=y CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y CONFIG_VIDEO=y CONFIG_DRIVER_VIDEO_IMX=y CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index ec4f864164..feef9ad1d5 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -29,6 +29,7 @@ config ARCH_TEXT_BASE default 0x4fc00000 if MACH_SABRELITE default 0x8fe00000 if MACH_TX53 default 0x7fc00000 if MACH_GUF_VINCELL + default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK config BOARDINFO default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25 @@ -48,6 +49,7 @@ config BOARDINFO default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK default "Freescale i.MX53 LOCO" if MACH_FREESCALE_MX53_LOCO default "Freescale i.MX53 SMD" if MACH_FREESCALE_MX53_SMD + default "Efika MX smartbook" if MACH_EFIKA_MX_SMARTBOOK default "Garz+Fricke Cupid" if MACH_GUF_CUPID default "Ka-Ro tx25" if MACH_TX25 default "TQ tqma53" if MACH_TQMA53 @@ -333,6 +335,7 @@ config MACH_PCM037 bool "phyCORE-i.MX31" select MACH_HAS_LOWLEVEL_INIT select USB_ULPI if USB + select HAVE_DEFAULT_ENVIRONMENT_NEW select ARCH_HAS_L2X0 help Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped @@ -428,6 +431,12 @@ config MACH_CCMX51_BASEBOARD This adds board specific devices that can be found on Digi evaluation board for CCMX51 module. +config MACH_EFIKA_MX_SMARTBOOK + bool "Efika MX smartbook" + select HAVE_DEFAULT_ENVIRONMENT_NEW + help + Choose this to compile barebox for the Efika MX Smartbook + endchoice endif diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c index d82fbf7e6b..682f39a3ac 100644 --- a/arch/arm/mach-imx/devices.c +++ b/arch/arm/mach-imx/devices.c @@ -72,3 +72,8 @@ struct device_d *imx_add_pata(void *base) { return imx_add_device("imx-pata", -1, base, 0x1000, NULL); } + +struct device_d *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata) +{ + return imx_add_device("imx-usb", id, base, 0x200, pdata); +} diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c index 31117f4501..6d30276284 100644 --- a/arch/arm/mach-imx/imx27.c +++ b/arch/arm/mach-imx/imx27.c @@ -118,6 +118,7 @@ static int imx27_init(void) add_generic_device("imx1-gpio", 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx21-wdt", 0, NULL, MX27_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx27-esdctl", 0, NULL, MX27_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx27-usb-misc", 0, NULL, MX27_USB_OTG_BASE_ADDR + 0x600, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c index 2882675788..f0954b5d54 100644 --- a/arch/arm/mach-imx/imx31.c +++ b/arch/arm/mach-imx/imx31.c @@ -39,6 +39,7 @@ static int imx31_init(void) add_generic_device("imx31-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx21-wdt", 0, NULL, MX31_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-esdctl", 0, NULL, MX31_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx31-usb-misc", 0, NULL, MX31_USB_OTG_BASE_ADDR + 0x600, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index a62daf8480..cffcca3920 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -70,6 +70,7 @@ static int imx51_init(void) add_generic_device("imx31-gpio", 3, NULL, MX51_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx21-wdt", 0, NULL, MX51_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx51-esdctl", 0, NULL, MX51_ESDCTL_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx51-usb-misc", 0, NULL, MX51_OTG_BASE_ADDR + 0x800, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h index 79da93531d..d6c884a30a 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx27.h +++ b/arch/arm/mach-imx/include/mach/devices-imx27.h @@ -70,3 +70,18 @@ static inline struct device_d *imx27_add_mmc2(void *pdata) { return imx_add_mmc((void *)MX27_SDHC3_BASE_ADDR, 2, pdata); } + +static inline struct device_d *imx27_add_usbotg(void *pdata) +{ + return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx27_add_usbh1(void *pdata) +{ + return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR + 0x200, 1, pdata); +} + +static inline struct device_d *imx27_add_usbh2(void *pdata) +{ + return imx_add_usb((void *)MX27_USB_OTG_BASE_ADDR + 0x400, 2, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h index fe719301ad..7cf9114fbd 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx31.h +++ b/arch/arm/mach-imx/include/mach/devices-imx31.h @@ -51,3 +51,28 @@ static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pda { return imx_add_ipufb((void *)MX31_IPU_CTRL_BASE_ADDR, pdata); } + +static inline struct device_d *imx31_add_mmc0(void *pdata) +{ + return imx_add_mmc((void *)MX31_SDHC1_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx31_add_mmc1(void *pdata) +{ + return imx_add_mmc((void *)MX31_SDHC2_BASE_ADDR, 1, pdata); +} + +static inline struct device_d *imx31_add_usbotg(void *pdata) +{ + return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx31_add_usbh1(void *pdata) +{ + return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR + 0x200, 1, pdata); +} + +static inline struct device_d *imx31_add_usbh2(void *pdata) +{ + return imx_add_usb((void *)MX31_USB_OTG_BASE_ADDR + 0x400, 2, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h index 95497fa664..ec8467ae9c 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx51.h +++ b/arch/arm/mach-imx/include/mach/devices-imx51.h @@ -98,3 +98,18 @@ static inline struct device_d *imx51_add_pata(void) { return imx_add_pata((void *)MX51_ATA_BASE_ADDR); } + +static inline struct device_d *imx51_add_usbotg(void *pdata) +{ + return imx_add_usb((void *)MX51_OTG_BASE_ADDR, 0, pdata); +} + +static inline struct device_d *imx51_add_usbh1(void *pdata) +{ + return imx_add_usb((void *)MX51_OTG_BASE_ADDR + 0x200, 1, pdata); +} + +static inline struct device_d *imx51_add_usbh2(void *pdata) +{ + return imx_add_usb((void *)MX51_OTG_BASE_ADDR + 0x400, 2, pdata); +} diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h index 016778a138..59296585af 100644 --- a/arch/arm/mach-imx/include/mach/devices.h +++ b/arch/arm/mach-imx/include/mach/devices.h @@ -7,6 +7,7 @@ #include <mach/imxfb.h> #include <mach/imx-ipu-fb.h> #include <mach/esdhc.h> +#include <usb/chipidea-imx.h> struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata); struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata); @@ -21,3 +22,4 @@ struct device_d *imx_add_mmc(void *base, int id, void *pdata); struct device_d *imx_add_esdhc(void *base, int id, struct esdhc_platform_data *pdata); struct device_d *imx_add_kpp(void *base, struct matrix_keymap_data *pdata); struct device_d *imx_add_pata(void *base); +struct device_d *imx_add_usb(void *base, int id, struct imxusb_platformdata *pdata); diff --git a/arch/arm/mach-imx/include/mach/esdhc.h b/arch/arm/mach-imx/include/mach/esdhc.h index b4c1aa9ebe..06863c8f1b 100644 --- a/arch/arm/mach-imx/include/mach/esdhc.h +++ b/arch/arm/mach-imx/include/mach/esdhc.h @@ -41,5 +41,6 @@ struct esdhc_platform_data { enum wp_types wp_type; enum cd_types cd_type; unsigned caps; + char *devname; }; #endif /* __ASM_ARCH_IMX_ESDHC_H */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx31.h b/arch/arm/mach-imx/include/mach/iomux-mx31.h index afb6fbaffb..258ccee034 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx31.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx31.h @@ -12,12 +12,10 @@ * GNU General Public License for more details. * */ - -#ifndef __MACH_MX31_IOMUX_H__ -#define __MACH_MX31_IOMUX_H__ +#ifndef __MACH_IOMUX_MX3_H__ +#define __MACH_IOMUX_MX3_H__ #include <linux/types.h> - /* * various IOMUX output functions */ @@ -30,7 +28,7 @@ #define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ #define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ #define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ +#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ #define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ #define IOMUX_ICONFIG_FUNC 2 /* used as function */ #define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ @@ -88,7 +86,7 @@ enum iomux_gp_func { MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, MUX_TAMPER_DETECT_EN = 1 << 16, MUX_PGP_USB_4WIRE = 1 << 17, - MUX_PGB_USB_COMMON = 1 << 18, + MUX_PGP_USB_COMMON = 1 << 18, MUX_SDHC_MEMSTICK1 = 1 << 19, MUX_SDHC_MEMSTICK2 = 1 << 20, MUX_PGP_SPLL_BYP = 1 << 21, @@ -105,21 +103,23 @@ enum iomux_gp_func { }; /* - * This function enables/disables the general purpose function for a particular - * signal. + * setups mutliple pins + * convenient way to call the above function with tables */ -void iomux_config_gpr(enum iomux_gp_func , int); +int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count); /* - * set the mode for a IOMUX pin. + * This function enables/disables the general purpose function for a particular + * signal. */ -int mxc_iomux_mode(unsigned int); +void imx_iomux_set_gpr(enum iomux_gp_func, bool en); /* - * This function enables/disables the general purpose function for a particular - * signal. + * This function only configures the iomux hardware. + * It is called by the setup functions and should not be called directly anymore. + * It is here visible for backward compatibility */ -void mxc_iomux_set_gpr(enum iomux_gp_func, int); +int imx_iomux_mode(unsigned int pin_mode); #define IOMUX_PADNUM_MASK 0x1ff #define IOMUX_GPIONUM_SHIFT 9 @@ -135,9 +135,6 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, int); #define IOMUX_TO_GPIO(iomux_pin) \ ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) -#define IOMUX_TO_IRQ(iomux_pin) \ - (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ - MXC_GPIO_INT_BASE) /* * This enumeration is constructed based on the Section @@ -476,6 +473,9 @@ enum iomux_pins { MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), }; +#define PIN_MAX 327 +#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */ + /* * Convenience values for use with mxc_iomux_mode() * @@ -483,14 +483,28 @@ enum iomux_pins { */ #define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI3_SCLK__RTS3 IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1) #define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2) #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2) #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2) #define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) #define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) #define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) #define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) #define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) @@ -503,7 +517,9 @@ enum iomux_pins { #define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1) #define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) #define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) @@ -521,29 +537,192 @@ enum iomux_pins { #define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) #define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) #define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) +#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC) +#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) +#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) +#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_1__GPIO IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_I2C_CLK__SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_I2C_DAT__SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_CSPI2_SS2__I2C3_SDA IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI2_SCLK__I2C3_SCL IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) +#define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) +#define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) +#define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_DCD_DTE1__I2C2_SDA IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_RI_DTE1__I2C2_SCL IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_ATA_CS0__GPIO3_26 IOMUX_MODE(MX31_PIN_ATA_CS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_CS1__GPIO3_27 IOMUX_MODE(MX31_PIN_ATA_CS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_PC_PWRON__SD2_DATA3 IOMUX_MODE(MX31_PIN_PC_PWRON, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_VS1__SD2_DATA2 IOMUX_MODE(MX31_PIN_PC_VS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_READY__SD2_DATA1 IOMUX_MODE(MX31_PIN_PC_READY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_WAIT_B__SD2_DATA0 IOMUX_MODE(MX31_PIN_PC_WAIT_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD2_B__SD2_CLK IOMUX_MODE(MX31_PIN_PC_CD2_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_PC_CD1_B__SD2_CMD IOMUX_MODE(MX31_PIN_PC_CD1_B, IOMUX_CONFIG_ALT1) +#define MX31_PIN_ATA_DIOR__GPIO3_28 IOMUX_MODE(MX31_PIN_ATA_DIOR, IOMUX_CONFIG_GPIO) +#define MX31_PIN_ATA_DIOW__GPIO3_29 IOMUX_MODE(MX31_PIN_ATA_DIOW, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__CSI_D4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D5__CSI_D5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D6__CSI_D6 IOMUX_MODE(MX31_PIN_CSI_D6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D7__CSI_D7 IOMUX_MODE(MX31_PIN_CSI_D7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D8__CSI_D8 IOMUX_MODE(MX31_PIN_CSI_D8, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D9__CSI_D9 IOMUX_MODE(MX31_PIN_CSI_D9, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D10__CSI_D10 IOMUX_MODE(MX31_PIN_CSI_D10, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D11__CSI_D11 IOMUX_MODE(MX31_PIN_CSI_D11, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D12__CSI_D12 IOMUX_MODE(MX31_PIN_CSI_D12, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D13__CSI_D13 IOMUX_MODE(MX31_PIN_CSI_D13, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D14__CSI_D14 IOMUX_MODE(MX31_PIN_CSI_D14, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_D15__CSI_D15 IOMUX_MODE(MX31_PIN_CSI_D15, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_HSYNC__CSI_HSYNC IOMUX_MODE(MX31_PIN_CSI_HSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_MCLK__CSI_MCLK IOMUX_MODE(MX31_PIN_CSI_MCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_PIXCLK__CSI_PIXCLK IOMUX_MODE(MX31_PIN_CSI_PIXCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSI_VSYNC__CSI_VSYNC IOMUX_MODE(MX31_PIN_CSI_VSYNC, IOMUX_CONFIG_FUNC) +#define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_0__GPIO1_0 IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SVEN0__GPIO2_0 IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STX0__GPIO2_1 IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRX0__GPIO2_2 IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SIMPD0__GPIO2_3 IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DTR_DCE1__GPIO2_8 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO) +#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_WATCHDOG_RST__WATCHDOG_RST IOMUX_MODE(MX31_PIN_WATCHDOG_RST, IOMUX_CONFIG_FUNC) -/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 - * cspi1_ss1*/ /* - * This function configures the pad value for a IOMUX pin. + * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, + * cspi2_ss1, cspi1_ss0 cspi1_ss1 */ -int imx_iomux_mode(unsigned int pin_mode); -void imx_iomux_set_pad(enum iomux_pins pin, u32 config); -void imx_iomux_set_gpr(enum iomux_gp_func gp, int en); - -#endif +/* + * This function configures the pad value for a IOMUX pin. + */ +void imx_iomux_set_pad(enum iomux_pins, u32); +#endif /* ifndef __MACH_IOMUX_MX3_H__ */ diff --git a/arch/arm/mach-imx/iomux-v2.c b/arch/arm/mach-imx/iomux-v2.c index dbbb8a26fd..cef0340909 100644 --- a/arch/arm/mach-imx/iomux-v2.c +++ b/arch/arm/mach-imx/iomux-v2.c @@ -88,7 +88,7 @@ EXPORT_SYMBOL(mxc_iomux_set_pad); * This function enables/disables the general purpose function for a particular * signal. */ -void imx_iomux_set_gpr(enum iomux_gp_func gp, int en) +void imx_iomux_set_gpr(enum iomux_gp_func gp, bool en) { u32 l; @@ -105,6 +105,16 @@ void imx_iomux_set_gpr(enum iomux_gp_func gp, int en) } EXPORT_SYMBOL(mxc_iomux_set_gpr); +int imx_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count) +{ + int i; + + for (i = 0; i < count; i++) + imx_iomux_mode(pin_list[i]); + + return 0; +} + static int imx_iomux_probe(struct device_d *dev) { base = dev_request_mem_region(dev, 0); |