diff options
| author | Alexander Shiyan <shc_work@mail.ru> | 2016-06-29 19:26:02 +0300 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2016-07-07 09:48:58 +0200 |
| commit | 9d7abf2792c5bb7d091f3f171a8e3a2fcaad1ea7 (patch) | |
| tree | 3cef794d81bb89b0b6877bd4a1268e85177e5de2 /arch | |
| parent | 8c8b38efbbda75faef904d67ad386ea6679c6453 (diff) | |
| download | barebox-9d7abf2792c5bb7d091f3f171a8e3a2fcaad1ea7.tar.gz barebox-9d7abf2792c5bb7d091f3f171a8e3a2fcaad1ea7.tar.xz | |
mfd: mc13xxx: VGEN1 and VGEN2 voltage bits positioned in "Regulator Setting 0" register
The bits VGEN10-11 and VGEN20-22 is positioned in the Regulator Setting 0
register. This patch fixes these definitions and board (Efika MX), which
uses this voltages.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boards/efika-mx-smartbook/board.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm/boards/efika-mx-smartbook/board.c b/arch/arm/boards/efika-mx-smartbook/board.c index d1d020e762..d7c11dc2fc 100644 --- a/arch/arm/boards/efika-mx-smartbook/board.c +++ b/arch/arm/boards/efika-mx-smartbook/board.c @@ -122,9 +122,13 @@ static void efikamx_power_init(struct mc13xxx *mc) /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ mc13xxx_reg_read(mc, MC13892_REG_SETTING_0, &val); val &= ~(MC13892_SETTING_0_VCAM_MASK | + MC13892_SETTING_0_VGEN1_MASK | + MC13892_SETTING_0_VGEN2_MASK | MC13892_SETTING_0_VGEN3_MASK | MC13892_SETTING_0_VDIG_MASK); val |= MC13892_SETTING_0_VDIG_1_8 | + MC13892_SETTING_0_VGEN1_1_2 | + MC13892_SETTING_0_VGEN2_3_15 | MC13892_SETTING_0_VGEN3_1_8 | MC13892_SETTING_0_VCAM_2_6; mc13xxx_reg_write(mc, MC13892_REG_SETTING_0, val); @@ -136,9 +140,7 @@ static void efikamx_power_init(struct mc13xxx *mc) MC13892_SETTING_1_VAUDIO_MASK); val |= MC13892_SETTING_1_VSD_3_15 | MC13892_SETTING_1_VAUDIO_3_0 | - MC13892_SETTING_1_VVIDEO_2_775 | - MC13892_SETTING_1_VGEN1_1_2 | - MC13892_SETTING_1_VGEN2_3_15; + MC13892_SETTING_1_VVIDEO_2_775; mc13xxx_reg_write(mc, MC13892_REG_SETTING_1, val); /* Enable VGEN1, VGEN2, VDIG, VPLL */ |