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authorSascha Hauer <s.hauer@pengutronix.de>2015-07-16 15:28:36 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2015-07-31 08:49:43 +0200
commita5003e4eff483f79086afade5e4dc12edf1abcb9 (patch)
tree184b23e18bcd5201dde823da81212488c813f3e1 /arch
parent3c9b56e90bb59d83f3fca18682102b992f6e1558 (diff)
downloadbarebox-a5003e4eff483f79086afade5e4dc12edf1abcb9.tar.gz
barebox-a5003e4eff483f79086afade5e4dc12edf1abcb9.tar.xz
ARM: imx6-mmdc: Fix cs0_end calculation
The current calculation does not take the 0x10000000 offset where SDRAM starts into account. For example with a 1GiB chip density the current code calculates cs1 start to 0x40000000, but it has to be 0x10000000 + 0x40000000 = 0x50000000. Add the missing 8 32MiB chunks. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-imx/imx6-mmdc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx6-mmdc.c b/arch/arm/mach-imx/imx6-mmdc.c
index fb81a15a12..64fb62401d 100644
--- a/arch/arm/mach-imx/imx6-mmdc.c
+++ b/arch/arm/mach-imx/imx6-mmdc.c
@@ -1199,7 +1199,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
trcd = trp;
trtp = twtr;
- cs0_end = 4 * sysinfo->cs_density - 1;
+ cs0_end = 4 * sysinfo->cs_density - 1 + 8;
debug("density:%d Gb (%d Gb per chip)\n",
sysinfo->cs_density, ddr3_cfg->density);