diff options
| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-10-22 14:21:25 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-10-22 14:21:25 +0200 |
| commit | f6a579da9c6c3e2d776f9251bcc727f6e17c0a11 (patch) | |
| tree | ee85d7902996c70bffe668b5d7172dee24c46574 /arch | |
| parent | 9956bdf77d7dbc61fe0f923917d2cdce3e2b40e5 (diff) | |
| download | barebox-f6a579da9c6c3e2d776f9251bcc727f6e17c0a11.tar.gz barebox-f6a579da9c6c3e2d776f9251bcc727f6e17c0a11.tar.xz | |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'arch')
100 files changed, 9080 insertions, 112 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 93e3588518..5105d63dec 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -32,6 +32,14 @@ board-$(CONFIG_MACH_EUKREA_CPUIMX27) := eukrea_cpuimx27 cpu-$(CONFIG_ARM920T) := arm920t cpu-$(CONFIG_ARM926EJS) := arm926ejs +machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) + +ifeq ($(KBUILD_SRC),) +CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) +else +CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) +endif + TEXT_BASE = $(CONFIG_TEXT_BASE) CPPFLAGS += -mabi=apcs-gnu -DTEXT_BASE=$(TEXT_BASE) -P @@ -42,25 +50,6 @@ CPPFLAGS += -fdata-sections -ffunction-sections LDFLAGS_uboot += -static --gc-sections endif -ifeq ($(incdir-y),) -incdir-y := $(machine-y) -endif -INCDIR := arch-$(incdir-y) - -# Update machine arch and proc symlinks if something which affects -# them changed. We use .arch to indicate when they were updated -# last, otherwise make uses the target directory mtime. - -include/asm-arm/.arch: $(wildcard include/config/arch/*.h) include/config/auto.conf - @echo ' SYMLINK include/asm-arm/arch -> include/asm-arm/$(INCDIR)' -ifneq ($(KBUILD_SRC),) - $(Q)mkdir -p include/asm-arm - $(Q)ln -fsn $(srctree)/include/asm-arm/$(INCDIR) include/asm-arm/arch -else - $(Q)ln -fsn $(INCDIR) include/asm-arm/arch -endif - @touch $@ - uboot.netx: uboot.bin $(Q)scripts/gen_netx_image -i uboot.bin -o uboot.netx \ --sdramctrl=$(CONFIG_NETX_SDRAM_CTRL) \ @@ -78,7 +67,6 @@ all: $(KBUILD_IMAGE) archprepare: maketools PHONY += maketools -maketools: include/asm-arm/.arch # Add architecture specific flags ifeq ($(CONFIG_ARMCORTEXA8),y) @@ -104,4 +92,3 @@ lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/arm/lib/u-boot.lds lds-$(CONFIG_BOARD_LINKER_SCRIPT) := $(BOARD)/u-boot.lds CLEAN_FILES += arch/arm/lib/u-boot.lds -MRPROPER_FILES += include/asm-arm/arch diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index fff4f800ee..166a7a3e28 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -2,6 +2,6 @@ #define _ARCH_ARM_GPIO_H /* not all ARM platforms necessarily support this API ... */ -#include <asm/arch/gpio.h> +#include <mach/gpio.h> #endif /* _ARCH_ARM_GPIO_H */ diff --git a/arch/arm/include/asm/hardware.h b/arch/arm/include/asm/hardware.h index 1fd1a5b650..c71c2aeab2 100644 --- a/arch/arm/include/asm/hardware.h +++ b/arch/arm/include/asm/hardware.h @@ -13,6 +13,6 @@ #ifndef __ASM_HARDWARE_H #define __ASM_HARDWARE_H -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #endif diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 5e321c1e7b..0cfe913f72 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c @@ -12,11 +12,11 @@ #include <common.h> #include <asm/armlinux.h> #include <asm/hardware.h> -#include <asm/arch/board.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91sam9260_matrix.h> -#include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <mach/board.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9260_matrix.h> +#include <mach/gpio.h> +#include <mach/io.h> static struct memory_platform_data sram_pdata = { .name = "sram0", diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 83b733f58b..50a63488f4 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -12,11 +12,11 @@ #include <common.h> #include <asm/armlinux.h> #include <asm/hardware.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91sam9263_matrix.h> -#include <asm/arch/board.h> -#include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <mach/at91_pmc.h> +#include <mach/at91sam9263_matrix.h> +#include <mach/board.h> +#include <mach/gpio.h> +#include <mach/io.h> static struct memory_platform_data ram_pdata = { .name = "ram0", diff --git a/arch/arm/mach-at91/clocksource.c b/arch/arm/mach-at91/clocksource.c index d937e49c38..b5886f938e 100644 --- a/arch/arm/mach-at91/clocksource.c +++ b/arch/arm/mach-at91/clocksource.c @@ -33,10 +33,10 @@ #include <init.h> #include <clock.h> #include <asm/hardware.h> -#include <asm/arch/at91_pit.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/io.h> +#include <mach/at91_pit.h> +#include <mach/at91_pmc.h> +#include <mach/at91_rstc.h> +#include <mach/io.h> #include <asm/io.h> uint64_t at91sam9_clocksource_read(void) diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index b479a4f83a..1cafaf7e29 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c @@ -24,7 +24,7 @@ #include <common.h> #include <errno.h> #include <asm/io.h> -#include <asm/arch/gpio.h> +#include <mach/gpio.h> #include <gpio.h> static int gpio_banks; diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h new file mode 100644 index 0000000000..f6ce1f924e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_pio.h @@ -0,0 +1,49 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91_pio.h] + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Parallel I/O Controller (PIO) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PIO_H +#define AT91_PIO_H + +#define PIO_PER 0x00 /* Enable Register */ +#define PIO_PDR 0x04 /* Disable Register */ +#define PIO_PSR 0x08 /* Status Register */ +#define PIO_OER 0x10 /* Output Enable Register */ +#define PIO_ODR 0x14 /* Output Disable Register */ +#define PIO_OSR 0x18 /* Output Status Register */ +#define PIO_IFER 0x20 /* Glitch Input Filter Enable */ +#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ +#define PIO_IFSR 0x28 /* Glitch Input Filter Status */ +#define PIO_SODR 0x30 /* Set Output Data Register */ +#define PIO_CODR 0x34 /* Clear Output Data Register */ +#define PIO_ODSR 0x38 /* Output Data Status Register */ +#define PIO_PDSR 0x3c /* Pin Data Status Register */ +#define PIO_IER 0x40 /* Interrupt Enable Register */ +#define PIO_IDR 0x44 /* Interrupt Disable Register */ +#define PIO_IMR 0x48 /* Interrupt Mask Register */ +#define PIO_ISR 0x4c /* Interrupt Status Register */ +#define PIO_MDER 0x50 /* Multi-driver Enable Register */ +#define PIO_MDDR 0x54 /* Multi-driver Disable Register */ +#define PIO_MDSR 0x58 /* Multi-driver Status Register */ +#define PIO_PUDR 0x60 /* Pull-up Disable Register */ +#define PIO_PUER 0x64 /* Pull-up Enable Register */ +#define PIO_PUSR 0x68 /* Pull-up Status Register */ +#define PIO_ASR 0x70 /* Peripheral A Select Register */ +#define PIO_BSR 0x74 /* Peripheral B Select Register */ +#define PIO_ABSR 0x78 /* AB Status Register */ +#define PIO_OWER 0xa0 /* Output Write Enable Register */ +#define PIO_OWDR 0xa4 /* Output Write Disable Register */ +#define PIO_OWSR 0xa8 /* Output Write Status Register */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h new file mode 100644 index 0000000000..94dd242a5f --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_pit.h @@ -0,0 +1,32 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91_pit.h] + * + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * Periodic Interval Timer (PIT) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PIT_H +#define AT91_PIT_H + +#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ +#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ +#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ +#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ + +#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ +#define AT91_PIT_PITS (1 << 0) /* Timer Status */ + +#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ +#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ +#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ +#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h new file mode 100644 index 0000000000..ed40b8bf6a --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -0,0 +1,133 @@ +/* + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Power Management Controller (PMC) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_PMC_H +#define AT91_PMC_H + +#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ +#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ + +#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ +#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ +#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [CAP9 revC & some SAM9 only] */ +#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ +#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ +#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ +#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ +#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ + +#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ + +#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */ +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ + +#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ +#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ +#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ + +#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ +#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ + +#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ +#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ +#define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ +#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ +#define AT91_PMC_USBDIV_1 (0 << 28) +#define AT91_PMC_USBDIV_2 (1 << 28) +#define AT91_PMC_USBDIV_4 (2 << 28) +#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ +#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ + +#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ +#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ +#define AT91_PMC_CSS_SLOW (0 << 0) +#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_PLLA (2 << 0) +#define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ +#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ +#define AT91_PMC_PRES_1 (0 << 2) +#define AT91_PMC_PRES_2 (1 << 2) +#define AT91_PMC_PRES_4 (2 << 2) +#define AT91_PMC_PRES_8 (3 << 2) +#define AT91_PMC_PRES_16 (4 << 2) +#define AT91_PMC_PRES_32 (5 << 2) +#define AT91_PMC_PRES_64 (6 << 2) +#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ +#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) +#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ +#define AT91_PMC_PLLADIV2_OFF (0 << 12) +#define AT91_PMC_PLLADIV2_ON (1 << 12) + +#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */ +#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ +#define AT91_PMC_USBS_PLLA (0 << 0) +#define AT91_PMC_USBS_UPLL (1 << 0) +#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ + +#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ +#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ +#define AT91_PMC_CSSMCK_CSS (0 << 8) +#define AT91_PMC_CSSMCK_MCK (1 << 8) + +#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ +#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ +#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ +#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ +#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ +#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ +#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */ +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ +#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ + +#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ + +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h new file mode 100644 index 0000000000..e49caef921 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_rstc.h @@ -0,0 +1,41 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91_rstc.h] + * + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * Reset Controller (RSTC) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_RSTC_H +#define AT91_RSTC_H + +#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ +#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ +#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ +#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ +#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ + +#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ +#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ +#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ +#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) +#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) +#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) +#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) +#define AT91_RSTC_RSTTYP_USER (4 << 8) +#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ +#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ + +#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ +#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ +#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ +#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h new file mode 100644 index 0000000000..7e18537cfb --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h @@ -0,0 +1,38 @@ +/* + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] + * + * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * Watchdog Timer (WDT) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_WDT_H +#define AT91_WDT_H + +#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ +#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ +#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ + +#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ +#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ +#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ +#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ +#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ +#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ +#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ +#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ +#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ + +#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ +#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ +#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h new file mode 100644 index 0000000000..7d166b7a89 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h @@ -0,0 +1,138 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9260.h] + * + * (C) 2006 Andrew Victor + * + * Common definitions. + * Based on AT91SAM9260 datasheet revision A (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9260_H +#define AT91SAM9260_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ +#define AT91SAM9260_ID_US0 6 /* USART 0 */ +#define AT91SAM9260_ID_US1 7 /* USART 1 */ +#define AT91SAM9260_ID_US2 8 /* USART 2 */ +#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ +#define AT91SAM9260_ID_UDP 10 /* USB Device Port */ +#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ +#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ +#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ +#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ +#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ +#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ +#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ +#define AT91SAM9260_ID_UHP 20 /* USB Host port */ +#define AT91SAM9260_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ +#define AT91SAM9260_ID_US3 23 /* USART 3 */ +#define AT91SAM9260_ID_US4 24 /* USART 4 */ +#define AT91SAM9260_ID_US5 25 /* USART 5 */ +#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ +#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ +#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ +#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9260_BASE_TCB0 0xfffa0000 +#define AT91SAM9260_BASE_TC0 0xfffa0000 +#define AT91SAM9260_BASE_TC1 0xfffa0040 +#define AT91SAM9260_BASE_TC2 0xfffa0080 +#define AT91SAM9260_BASE_UDP 0xfffa4000 +#define AT91SAM9260_BASE_MCI 0xfffa8000 +#define AT91SAM9260_BASE_TWI 0xfffac000 +#define AT91SAM9260_BASE_US0 0xfffb0000 +#define AT91SAM9260_BASE_US1 0xfffb4000 +#define AT91SAM9260_BASE_US2 0xfffb8000 +#define AT91SAM9260_BASE_SSC 0xfffbc000 +#define AT91SAM9260_BASE_ISI 0xfffc0000 +#define AT91SAM9260_BASE_EMAC 0xfffc4000 +#define AT91SAM9260_BASE_SPI0 0xfffc8000 +#define AT91SAM9260_BASE_SPI1 0xfffcc000 +#define AT91SAM9260_BASE_US3 0xfffd0000 +#define AT91SAM9260_BASE_US4 0xfffd4000 +#define AT91SAM9260_BASE_US5 0xfffd8000 +#define AT91SAM9260_BASE_TCB1 0xfffdc000 +#define AT91SAM9260_BASE_TC3 0xfffdc000 +#define AT91SAM9260_BASE_TC4 0xfffdc040 +#define AT91SAM9260_BASE_TC5 0xfffdc080 +#define AT91SAM9260_BASE_ADC 0xfffe0000 +#define AT91_BASE_SYS 0xffffe800 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9260_BASE_US0 +#define AT91_USART1 AT91SAM9260_BASE_US1 +#define AT91_USART2 AT91SAM9260_BASE_US2 +#define AT91_USART3 AT91SAM9260_BASE_US3 +#define AT91_USART4 AT91SAM9260_BASE_US4 +#define AT91_USART5 AT91SAM9260_BASE_US5 + +#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0 +#define AT91_BASE_TWI AT91SAM9260_BASE_TWI +#define AT91_ID_UHP AT91SAM9260_ID_UHP +#define AT91_PMC_UHP AT91SAM926x_PMC_UHP + +/* + * Internal Memory. + */ +#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ +#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ + +#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ +#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ +#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ +#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ + +#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ + +#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ +#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ + +/* + * Cpu Name + */ +#if defined(CONFIG_AT91SAM9260) +#define AT91_CPU_NAME "AT91SAM9260" +#elif defined(CONFIG_AT91SAM9G20) +#define AT91_CPU_NAME "AT91SAM9G20" +#endif + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h new file mode 100644 index 0000000000..020f02ed92 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h @@ -0,0 +1,80 @@ +/* + * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h + * + * Copyright (C) 2007 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9260 datasheet revision B. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9260_MATRIX_H +#define AT91SAM9260_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h new file mode 100644 index 0000000000..7bab1a4b10 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h @@ -0,0 +1,137 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263.h] + * + * (C) 2007 Atmel Corporation. + * + * Common definitions. + * Based on AT91SAM9263 datasheet revision B (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9263_H +#define AT91SAM9263_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ +#define AT91SAM9263_ID_US0 7 /* USART 0 */ +#define AT91SAM9263_ID_US1 8 /* USART 1 */ +#define AT91SAM9263_ID_US2 9 /* USART 2 */ +#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ +#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ +#define AT91SAM9263_ID_CAN 12 /* CAN */ +#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ +#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ +#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ +#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ +#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ +#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ +#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ +#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ +#define AT91SAM9263_ID_EMAC 21 /* Ethernet */ +#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ +#define AT91SAM9263_ID_UDP 24 /* USB Device Port */ +#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ +#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ +#define AT91SAM9263_ID_DMA 27 /* DMA Controller */ +#define AT91SAM9263_ID_UHP 29 /* USB Host port */ +#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9263_BASE_UDP 0xfff78000 +#define AT91SAM9263_BASE_TCB0 0xfff7c000 +#define AT91SAM9263_BASE_TC0 0xfff7c000 +#define AT91SAM9263_BASE_TC1 0xfff7c040 +#define AT91SAM9263_BASE_TC2 0xfff7c080 +#define AT91SAM9263_BASE_MCI0 0xfff80000 +#define AT91SAM9263_BASE_MCI1 0xfff84000 +#define AT91SAM9263_BASE_TWI 0xfff88000 +#define AT91SAM9263_BASE_US0 0xfff8c000 +#define AT91SAM9263_BASE_US1 0xfff90000 +#define AT91SAM9263_BASE_US2 0xfff94000 +#define AT91SAM9263_BASE_SSC0 0xfff98000 +#define AT91SAM9263_BASE_SSC1 0xfff9c000 +#define AT91SAM9263_BASE_AC97C 0xfffa0000 +#define AT91SAM9263_BASE_SPI0 0xfffa4000 +#define AT91SAM9263_BASE_SPI1 0xfffa8000 +#define AT91SAM9263_BASE_CAN 0xfffac000 +#define AT91SAM9263_BASE_PWMC 0xfffb8000 +#define AT91SAM9263_BASE_EMAC 0xfffbc000 +#define AT91SAM9263_BASE_ISI 0xfffc4000 +#define AT91SAM9263_BASE_2DGE 0xfffc8000 +#define AT91_BASE_SYS 0xffffe000 + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) +#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) +#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) +#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) +#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) +#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) +#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) + +#define AT91_USART0 AT91SAM9263_BASE_US0 +#define AT91_USART1 AT91SAM9263_BASE_US1 +#define AT91_USART2 AT91SAM9263_BASE_US2 + +#define AT91_SMC AT91_SMC0 +#define AT91_SDRAMC AT91_SDRAMC0 + +#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0 +#define AT91_BASE_TWI AT91SAM9263_BASE_TWI +#define AT91_ID_UHP AT91SAM9263_ID_UHP +#define AT91_PMC_UHP AT91SAM926x_PMC_UHP + +/* + * Internal Memory. + */ +#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ +#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ + +#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ + +#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ +#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ + +#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ +#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ +#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ + +/* + * Cpu Name + */ +#define AT91_CPU_NAME "AT91SAM9263" + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h new file mode 100644 index 0000000000..83aaaab773 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h @@ -0,0 +1,129 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9263_matrix.h] + * + * Copyright (C) 2006 Atmel Corporation. + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9263 datasheet revision B (Preliminary). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9263_MATRIX_H +#define AT91SAM9263_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ +#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ +#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ +#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ +#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ +#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ +#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ +#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ +#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ +#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ +#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ +#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ +#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) +#define AT91_MATRIX_RCB6 (1 << 6) +#define AT91_MATRIX_RCB7 (1 << 7) +#define AT91_MATRIX_RCB8 (1 << 8) + +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) + +#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ +#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) +#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) +#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) +#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) + +#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ +#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) +#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) +#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h new file mode 100644 index 0000000000..58cafd8527 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H +#define __ASM_ARCH_AT91SAM9_MATRIX_H + +#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) +#include <mach/at91sam9260_matrix.h> +#elif defined(CONFIG_ARCH_AT91SAM9261) +#include <mach/at91sam9261_matrix.h> +#elif defined(CONFIG_ARCH_AT91SAM9263) +#include <mach/at91sam9263_matrix.h> +#elif defined(CONFIG_ARCH_AT91SAM9RL) +#include <mach/at91sam9rl_matrix.h> +#elif defined(CONFIG_ARCH_AT91CAP9) +#include <mach/at91cap9_matrix.h> +#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9M10G45) +#include <mach/at91sam9g45_matrix.h> +#else +#error "Unsupported AT91SAM9/CAP9 processor" +#endif + +#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */ diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h new file mode 100644 index 0000000000..5af2b54b12 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h @@ -0,0 +1,87 @@ +/* + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] + * + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * SDRAM Controllers (SDRAMC) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9_SDRAMC_H +#define AT91SAM9_SDRAMC_H + +/* SDRAM Controller (SDRAMC) registers */ +#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ +#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ +#define AT91_SDRAMC_MODE_NORMAL 0 +#define AT91_SDRAMC_MODE_NOP 1 +#define AT91_SDRAMC_MODE_PRECHARGE 2 +#define AT91_SDRAMC_MODE_LMR 3 +#define AT91_SDRAMC_MODE_REFRESH 4 +#define AT91_SDRAMC_MODE_EXT_LMR 5 +#define AT91_SDRAMC_MODE_DEEP 6 + +#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ +#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ + +#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ +#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ +#define AT91_SDRAMC_NC_8 (0 << 0) +#define AT91_SDRAMC_NC_9 (1 << 0) +#define AT91_SDRAMC_NC_10 (2 << 0) +#define AT91_SDRAMC_NC_11 (3 << 0) +#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ +#define AT91_SDRAMC_NR_11 (0 << 2) +#define AT91_SDRAMC_NR_12 (1 << 2) +#define AT91_SDRAMC_NR_13 (2 << 2) +#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ +#define AT91_SDRAMC_NB_2 (0 << 4) +#define AT91_SDRAMC_NB_4 (1 << 4) +#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ +#define AT91_SDRAMC_CAS_1 (1 << 5) +#define AT91_SDRAMC_CAS_2 (2 << 5) +#define AT91_SDRAMC_CAS_3 (3 << 5) +#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ +#define AT91_SDRAMC_DBW_32 (0 << 7) +#define AT91_SDRAMC_DBW_16 (1 << 7) +#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ +#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ +#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ +#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ +#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ +#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ + +#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ +#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ +#define AT91_SDRAMC_LPCB_DISABLE 0 +#define AT91_SDRAMC_LPCB_SELF_REFRESH 1 +#define AT91_SDRAMC_LPCB_POWER_DOWN 2 +#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 +#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ +#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ +#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ +#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ +#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) +#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) +#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) + +#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ +#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ +#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ +#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ +#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ + +#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ +#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ +#define AT91_SDRAMC_MD_SDRAM 0 +#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 + + +#endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h new file mode 100644 index 0000000000..d64511b36d --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -0,0 +1,76 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] + * + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * Static Memory Controllers (SMC) - System peripherals registers. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91SAM9_SMC_H +#define AT91SAM9_SMC_H + +#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ +#define AT91_SMC_NWESETUP_(x) ((x) << 0) +#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ +#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) +#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ +#define AT91_SMC_NRDSETUP_(x) ((x) << 16) +#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ +#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) + +#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ +#define AT91_SMC_NWEPULSE_(x) ((x) << 0) +#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ +#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) +#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ +#define AT91_SMC_NRDPULSE_(x) ((x) << 16) +#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ +#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) + +#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ +#define AT91_SMC_NWECYCLE_(x) ((x) << 0) +#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ +#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) + +#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ +#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ +#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ +#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) +#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) +#define AT91_SMC_EXNWMODE_READY (3 << 4) +#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ +#define AT91_SMC_BAT_SELECT (0 << 8) +#define AT91_SMC_BAT_WRITE (1 << 8) +#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ +#define AT91_SMC_DBW_8 (0 << 12) +#define AT91_SMC_DBW_16 (1 << 12) +#define AT91_SMC_DBW_32 (2 << 12) +#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ +#define AT91_SMC_TDF_(x) ((x) << 16) +#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ +#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ +#define AT91_SMC_PS (3 << 28) /* Page Size */ +#define AT91_SMC_PS_4 (0 << 28) +#define AT91_SMC_PS_8 (1 << 28) +#define AT91_SMC_PS_16 (2 << 28) +#define AT91_SMC_PS_32 (3 << 28) + +#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ +#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ +#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ +#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ +#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ +#endif + +#endif diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h new file mode 100644 index 0000000000..1ab05ade87 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/board.h @@ -0,0 +1,66 @@ +/* + * [origin Linux: arch/arm/mach-at91/include/mach/board.h] + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_BOARD_H +#define __ASM_ARCH_BOARD_H + +#include <linux/mtd/mtd.h> + +void atmel_nand_load_image(void *dest, int size, int pagesize, int blocksize); + + /* NAND / SmartMedia */ +struct atmel_nand_data { + void __iomem *ecc_base; + u8 enable_pin; /* chip enable */ + u8 det_pin; /* card detect */ + u8 rdy_pin; /* ready/busy */ + u8 ale; /* address line number connected to ALE */ + u8 cle; /* address line number connected to CLE */ + u8 bus_width_16; /* buswidth is 16 bit */ + u8 ecc_mode; /* NAND_ECC_* */ +}; + +void at91_add_device_nand(struct atmel_nand_data *data); + + /* Ethernet (EMAC & MACB) */ +#define AT91SAM_ETHER_MII (0 << 0) +#define AT91SAM_ETHER_RMII (1 << 0) +#define AT91SAM_ETHER_FORCE_LINK (1 << 1) + +struct at91_ether_platform_data { + unsigned int flags; + int phy_addr; +}; + +void at91_add_device_eth(struct at91_ether_platform_data *data); + +/* SDRAM */ +void at91_add_device_sdram(u32 size); + + /* Serial */ +#define ATMEL_UART_CTS 0x01 +#define ATMEL_UART_RTS 0x02 +#define ATMEL_UART_DSR 0x04 +#define ATMEL_UART_DTR 0x08 +#define ATMEL_UART_DCD 0x10 +#define ATMEL_UART_RI 0x20 + +void at91_register_uart(unsigned id, unsigned pins); +#endif diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h new file mode 100644 index 0000000000..a9c06836b8 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/clk.h @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2007 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_CLK_H__ +#define __ASM_ARM_ARCH_CLK_H__ + +#include <mach/hardware.h> + +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return AT91_MASTER_CLOCK; +} + +static inline unsigned long get_usart_clk_rate(unsigned int dev_id) +{ + return AT91_MASTER_CLOCK; +} + +#endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h new file mode 100644 index 0000000000..76d53ba248 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -0,0 +1,262 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/gpio.h] + * + * Copyright (C) 2005 HP Labs + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_AT91_GPIO_H +#define __ASM_ARCH_AT91_GPIO_H + +#include <asm/io.h> +#include <asm-generic/errno.h> +#include <mach/at91_pio.h> +#include <mach/hardware.h> + +#define PIN_BASE 32 + +/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ + +#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) +#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) +#define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) +#define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) +#define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) +#define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) +#define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) +#define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) +#define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) +#define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) +#define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) +#define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) +#define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) +#define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) +#define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) +#define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) +#define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) +#define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) +#define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) +#define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) +#define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) +#define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) +#define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) +#define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) +#define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) +#define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) +#define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) +#define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) +#define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) +#define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) +#define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) +#define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) + +#define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) +#define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) +#define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) +#define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) +#define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) +#define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) +#define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) +#define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) +#define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) +#define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) +#define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) +#define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) +#define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) +#define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) +#define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) +#define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) +#define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) +#define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) +#define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) +#define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) +#define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) +#define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) +#define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) +#define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) +#define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) +#define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) +#define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) +#define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) +#define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) +#define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) +#define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) +#define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) + +#define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) +#define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) +#define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) +#define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) +#define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) +#define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) +#define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) +#define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) +#define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) +#define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) +#define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) +#define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) +#define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) +#define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) +#define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) +#define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) +#define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) +#define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) +#define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) +#define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) +#define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) +#define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) +#define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) +#define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) +#define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) +#define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) +#define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) +#define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) +#define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) +#define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) +#define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) +#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) + +#define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) +#define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) +#define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) +#define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) +#define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) +#define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) +#define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) +#define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) +#define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) +#define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) +#define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) +#define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) +#define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) +#define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) +#define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) +#define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) +#define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) +#define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) +#define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) +#define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) +#define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) +#define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) +#define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) +#define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) +#define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) +#define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) +#define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) +#define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) +#define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) +#define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) +#define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) +#define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) + +#define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) +#define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) +#define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) +#define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) +#define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) +#define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) +#define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) +#define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) +#define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) +#define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) +#define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) +#define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) +#define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) +#define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) +#define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) +#define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) +#define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) +#define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) +#define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) +#define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) +#define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) +#define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) +#define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) +#define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) +#define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) +#define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) +#define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) +#define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) +#define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) +#define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) +#define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) +#define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) + +/* + * mux the pin to the "GPIO" peripheral role. + */ +int at91_set_GPIO_periph(unsigned pin, int use_pullup); + + +/* + * mux the pin to the "A" internal peripheral role. + */ +int at91_set_A_periph(unsigned pin, int use_pullup); + +/* + * mux the pin to the "B" internal peripheral role. + */ +int at91_set_B_periph(unsigned pin, int use_pullup); +/* + * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and + * configure it for an input. + */ +int at91_set_gpio_input(unsigned pin, int use_pullup); + +/* + * mux the pin to the gpio controller (instead of "A" or "B" peripheral), + * and configure it for an output. + */ +int at91_set_gpio_output(unsigned pin, int value); + +/* + * enable/disable the glitch filter; mostly used with IRQ handling. + */ +int at91_set_deglitch(unsigned pin, int is_on); + +/* + * enable/disable the multi-driver; This is only valid for output and + * allows the output pin to run as an open collector output. + */ +int at91_set_multi_drive(unsigned pin, int is_on); + +/* + * assuming the pin is muxed as a gpio output, set its value. + */ +int at91_set_gpio_value(unsigned pin, int value); + +/* + * read the pin's value (works even if it's not muxed as a gpio). + */ +int at91_get_gpio_value(unsigned pin); + +struct at91_gpio_bank { + unsigned chipbase; /* bank's first GPIO number */ + void __iomem *regbase; /* base of register bank */ + struct at91_gpio_bank *next; /* bank sharing same IRQ/clock/... */ + unsigned short id; /* peripheral ID */ + unsigned long offset; /* offset from system peripheral base */ +}; + +extern int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks); + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); +#define gpio_get_value at91_get_gpio_value +#define gpio_set_value at91_set_gpio_value + +#endif /* __ASM_ARCH_AT91SAM9_GPIO_H */ diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h new file mode 100644 index 0000000000..82b574eb0a --- /dev/null +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -0,0 +1,57 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/hardware.h] + * + * Copyright (C) 2003 SAN People + * Copyright (C) 2003 ATMEL + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#if defined(CONFIG_ARCH_AT91RM9200) +#include <mach/at91rm9200.h> +#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) +#include <mach/at91sam9260.h> +#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) +#include <mach/at91sam9261.h> +#elif defined(CONFIG_ARCH_AT91SAM9263) +#include <mach/at91sam9263.h> +#elif defined(CONFIG_ARCH_AT91SAM9RL) +#include <mach/at91sam9rl.h> +#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9M10G45) +#include <mach/at91sam9g45.h> +#elif defined(CONFIG_ARCH_AT91CAP9) +#include <mach/at91cap9.h> +#elif defined(CONFIG_ARCH_AT91X40) +#include <mach/at91x40.h> +#else +#error "Unsupported AT91 processor" +#endif + +/* External Memory Map */ +#define AT91_CHIPSELECT_0 0x10000000 +#define AT91_CHIPSELECT_1 0x20000000 +#define AT91_CHIPSELECT_2 0x30000000 +#define AT91_CHIPSELECT_3 0x40000000 +#define AT91_CHIPSELECT_4 0x50000000 +#define AT91_CHIPSELECT_5 0x60000000 +#define AT91_CHIPSELECT_6 0x70000000 +#define AT91_CHIPSELECT_7 0x80000000 + +/* SDRAM */ +#ifdef CONFIG_DRAM_BASE +#define AT91_SDRAM_BASE CONFIG_DRAM_BASE +#else +#define AT91_SDRAM_BASE AT91_CHIPSELECT_1 +#endif + +/* Clocks */ +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + +#endif diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h new file mode 100644 index 0000000000..f09b2df0e3 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/io.h @@ -0,0 +1,40 @@ +/* + * [origin: Linux kernel include/asm-arm/arch-at91/io.h] + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include <asm/io.h> + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void *addr = (void *)AT91_BASE_SYS; + + return __raw_readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void *addr = (void *)AT91_BASE_SYS; + + __raw_writel(value, addr + reg_offset); +} + +#endif diff --git a/arch/arm/mach-at91/include/mach/sam9_smc.h b/arch/arm/mach-at91/include/mach/sam9_smc.h new file mode 100644 index 0000000000..bf72cfb345 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sam9_smc.h @@ -0,0 +1,33 @@ +/* + * linux/arch/arm/mach-at91/sam9_smc. + * + * Copyright (C) 2008 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +struct sam9_smc_config { + /* Setup register */ + u8 ncs_read_setup; + u8 nrd_setup; + u8 ncs_write_setup; + u8 nwe_setup; + + /* Pulse register */ + u8 ncs_read_pulse; + u8 nrd_pulse; + u8 ncs_write_pulse; + u8 nwe_pulse; + + /* Cycle register */ + u16 read_cycle; + u16 write_cycle; + + /* Mode register */ + u32 mode; + u8 tdf_cycles:4; +}; + +extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config); diff --git a/arch/arm/mach-at91/lowlevel_init.S b/arch/arm/mach-at91/lowlevel_init.S index fa6577a6ab..5bd32e89b0 100644 --- a/arch/arm/mach-at91/lowlevel_init.S +++ b/arch/arm/mach-at91/lowlevel_init.S @@ -28,14 +28,14 @@ #include <linux/autoconf.h> #include <config.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/at91_wdt.h> -#include <asm/arch/at91sam9_matrix.h> -#include <asm/arch/at91sam9_sdramc.h> -#include <asm/arch/at91sam9_smc.h> +#include <mach/hardware.h> +#include <mach/at91_pmc.h> +#include <mach/at91_pio.h> +#include <mach/at91_rstc.h> +#include <mach/at91_wdt.h> +#include <mach/at91sam9_matrix.h> +#include <mach/at91sam9_sdramc.h> +#include <mach/at91sam9_smc.h> _TEXT_BASE: .word TEXT_BASE diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index f3f885c72b..3e7de2fc58 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -10,11 +10,11 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/io.h> +#include <mach/hardware.h> +#include <mach/io.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/sam9_smc.h> +#include <mach/at91sam9_smc.h> +#include <mach/sam9_smc.h> void sam9_smc_configure(int cs, struct sam9_smc_config* config) { diff --git a/arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h b/arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h new file mode 100644 index 0000000000..97d470484c --- /dev/null +++ b/arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h @@ -0,0 +1,762 @@ +/* + * (C) Copyright 2003 + * AT91RM9200 definitions + * Author : ATMEL AT91 application group + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef AT91RM9200_H +#define AT91RM9200_H + +typedef volatile unsigned int AT91_REG; /* Hardware register definition */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ +/******************************************************************************/ +typedef struct _AT91S_TC +{ + AT91_REG TC_CCR; /* Channel Control Register */ + AT91_REG TC_CMR; /* Channel Mode Register */ + AT91_REG Reserved0[2]; /* */ + AT91_REG TC_CV; /* Counter Value */ + AT91_REG TC_RA; /* Register A */ + AT91_REG TC_RB; /* Register B */ + AT91_REG TC_RC; /* Register C */ + AT91_REG TC_SR; /* Status Register */ + AT91_REG TC_IER; /* Interrupt Enable Register */ + AT91_REG TC_IDR; /* Interrupt Disable Register */ + AT91_REG TC_IMR; /* Interrupt Mask Register */ +} AT91S_TC, *AT91PS_TC; + +#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ +#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ +#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ +#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ +#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ +#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ +#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ +#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ +#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ +#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ +#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ +#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ +#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ +#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Usart */ +/******************************************************************************/ +typedef struct _AT91S_USART +{ + AT91_REG US_CR; /* Control Register */ + AT91_REG US_MR; /* Mode Register */ + AT91_REG US_IER; /* Interrupt Enable Register */ + AT91_REG US_IDR; /* Interrupt Disable Register */ + AT91_REG US_IMR; /* Interrupt Mask Register */ + AT91_REG US_CSR; /* Channel Status Register */ + AT91_REG US_RHR; /* Receiver Holding Register */ + AT91_REG US_THR; /* Transmitter Holding Register */ + AT91_REG US_BRGR; /* Baud Rate Generator Register */ + AT91_REG US_RTOR; /* Receiver Time-out Register */ + AT91_REG US_TTGR; /* Transmitter Time-guard Register */ + AT91_REG Reserved0[5]; /* */ + AT91_REG US_FIDI; /* FI_DI_Ratio Register */ + AT91_REG US_NER; /* Nb Errors Register */ + AT91_REG US_XXR; /* XON_XOFF Register */ + AT91_REG US_IF; /* IRDA_FILTER Register */ + AT91_REG Reserved1[44]; /* */ + AT91_REG US_RPR; /* Receive Pointer Register */ + AT91_REG US_RCR; /* Receive Counter Register */ + AT91_REG US_TPR; /* Transmit Pointer Register */ + AT91_REG US_TCR; /* Transmit Counter Register */ + AT91_REG US_RNPR; /* Receive Next Pointer Register */ + AT91_REG US_RNCR; /* Receive Next Counter Register */ + AT91_REG US_TNPR; /* Transmit Next Pointer Register */ + AT91_REG US_TNCR; /* Transmit Next Counter Register */ + AT91_REG US_PTCR; /* PDC Transfer Control Register */ + AT91_REG US_PTSR; /* PDC Transfer Status Register */ +} AT91S_USART, *AT91PS_USART; + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Clock Generator Controler */ +/******************************************************************************/ +typedef struct _AT91S_CKGR +{ + AT91_REG CKGR_MOR; /* Main Oscillator Register */ + AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */ + AT91_REG CKGR_PLLAR; /* PLL A Register */ + AT91_REG CKGR_PLLBR; /* PLL B Register */ +} AT91S_CKGR, *AT91PS_CKGR; + +/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */ +#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */ +#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */ +#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */ + +/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */ +#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */ +#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */ + +/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */ +#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */ +#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */ +#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */ +#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */ +#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */ + +/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */ +#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */ +#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */ +#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */ +#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */ +#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */ +#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */ +#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */ +#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */ +#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ +/******************************************************************************/ +typedef struct _AT91S_PIO +{ + AT91_REG PIO_PER; /* PIO Enable Register */ + AT91_REG PIO_PDR; /* PIO Disable Register */ + AT91_REG PIO_PSR; /* PIO Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PIO_OER; /* Output Enable Register */ + AT91_REG PIO_ODR; /* Output Disable Registerr */ + AT91_REG PIO_OSR; /* Output Status Register */ + AT91_REG Reserved1[1]; /* */ + AT91_REG PIO_IFER; /* Input Filter Enable Register */ + AT91_REG PIO_IFDR; /* Input Filter Disable Register */ + AT91_REG PIO_IFSR; /* Input Filter Status Register */ + AT91_REG Reserved2[1]; /* */ + AT91_REG PIO_SODR; /* Set Output Data Register */ + AT91_REG PIO_CODR; /* Clear Output Data Register */ + AT91_REG PIO_ODSR; /* Output Data Status Register */ + AT91_REG PIO_PDSR; /* Pin Data Status Register */ + AT91_REG PIO_IER; /* Interrupt Enable Register */ + AT91_REG PIO_IDR; /* Interrupt Disable Register */ + AT91_REG PIO_IMR; /* Interrupt Mask Register */ + AT91_REG PIO_ISR; /* Interrupt Status Register */ + AT91_REG PIO_MDER; /* Multi-driver Enable Register */ + AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ + AT91_REG PIO_MDSR; /* Multi-driver Status Register */ + AT91_REG Reserved3[1]; /* */ + AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ + AT91_REG PIO_PPUER; /* Pull-up Enable Register */ + AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ + AT91_REG Reserved4[1]; /* */ + AT91_REG PIO_ASR; /* Select A Register */ + AT91_REG PIO_BSR; /* Select B Register */ + AT91_REG PIO_ABSR; /* AB Select Status Register */ + AT91_REG Reserved5[9]; /* */ + AT91_REG PIO_OWER; /* Output Write Enable Register */ + AT91_REG PIO_OWDR; /* Output Write Disable Register */ + AT91_REG PIO_OWSR; /* Output Write Status Register */ +} AT91S_PIO, *AT91PS_PIO; + + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Debug Unit */ +/******************************************************************************/ +typedef struct _AT91S_DBGU +{ + AT91_REG DBGU_CR; /* Control Register */ + AT91_REG DBGU_MR; /* Mode Register */ + AT91_REG DBGU_IER; /* Interrupt Enable Register */ + AT91_REG DBGU_IDR; /* Interrupt Disable Register */ + AT91_REG DBGU_IMR; /* Interrupt Mask Register */ + AT91_REG DBGU_CSR; /* Channel Status Register */ + AT91_REG DBGU_RHR; /* Receiver Holding Register */ + AT91_REG DBGU_THR; /* Transmitter Holding Register */ + AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ + AT91_REG Reserved0[7]; /* */ + AT91_REG DBGU_C1R; /* Chip ID1 Register */ + AT91_REG DBGU_C2R; /* Chip ID2 Register */ + AT91_REG DBGU_FNTR; /* Force NTRST Register */ + AT91_REG Reserved1[45]; /* */ + AT91_REG DBGU_RPR; /* Receive Pointer Register */ + AT91_REG DBGU_RCR; /* Receive Counter Register */ + AT91_REG DBGU_TPR; /* Transmit Pointer Register */ + AT91_REG DBGU_TCR; /* Transmit Counter Register */ + AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ + AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ + AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ + AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ + AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ + AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ +} AT91S_DBGU, *AT91PS_DBGU; + +/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ +#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ +#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ +#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ +#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ +#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ +#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ +#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ +#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ +#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ +#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ + +/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ + +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ +/******************************************************************************/ +typedef struct _AT91S_SMC2 +{ + AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ +} AT91S_SMC2, *AT91PS_SMC2; + +/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */ +#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */ +#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ +#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ +#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ +#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ +#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ +#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ +#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */ +#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ +#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */ +#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ +#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ +#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ +#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Power Management Controler */ +/******************************************************************************/ +typedef struct _AT91S_PMC +{ + AT91_REG PMC_SCER; /* System Clock Enable Register */ + AT91_REG PMC_SCDR; /* System Clock Disable Register */ + AT91_REG PMC_SCSR; /* System Clock Status Register */ + AT91_REG Reserved0[1]; /* */ + AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */ + AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */ + AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */ + AT91_REG Reserved1[5]; /* */ + AT91_REG PMC_MCKR; /* Master Clock Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ + AT91_REG PMC_IER; /* Interrupt Enable Register */ + AT91_REG PMC_IDR; /* Interrupt Disable Register */ + AT91_REG PMC_SR; /* Status Register */ + AT91_REG PMC_IMR; /* Interrupt Mask Register */ +} AT91S_PMC, *AT91PS_PMC; + +/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/ +#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */ +#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */ +#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */ +#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */ +#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */ +#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */ +/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/ +/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/ +/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/ +#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */ +#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */ +#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */ +#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */ +#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */ +#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */ +#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */ +#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */ +#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */ +#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */ +#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */ +#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */ +#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */ +#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */ +#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */ +#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */ +#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */ +#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */ +/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/ +/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/ +#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */ +#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */ +#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */ +#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */ +/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/ +/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/ +/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Ethernet MAC */ +/******************************************************************************/ +typedef struct _AT91S_EMAC +{ + AT91_REG EMAC_CTL; /* Network Control Register */ + AT91_REG EMAC_CFG; /* Network Configuration Register */ + AT91_REG EMAC_SR; /* Network Status Register */ + AT91_REG EMAC_TAR; /* Transmit Address Register */ + AT91_REG EMAC_TCR; /* Transmit Control Register */ + AT91_REG EMAC_TSR; /* Transmit Status Register */ + AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ + AT91_REG Reserved0[1]; /* */ + AT91_REG EMAC_RSR; /* Receive Status Register */ + AT91_REG EMAC_ISR; /* Interrupt Status Register */ + AT91_REG EMAC_IER; /* Interrupt Enable Register */ + AT91_REG EMAC_IDR; /* Interrupt Disable Register */ + AT91_REG EMAC_IMR; /* Interrupt Mask Register */ + AT91_REG EMAC_MAN; /* PHY Maintenance Register */ + AT91_REG Reserved1[2]; /* */ + AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ + AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ + AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ + AT91_REG EMAC_OK; /* Frames Received OK Register */ + AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ + AT91_REG EMAC_ALE; /* Alignment Error Register */ + AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ + AT91_REG EMAC_LCOL; /* Late Collision Register */ + AT91_REG EMAC_ECOL; /* Excessive Collision Register */ + AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ + AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ + AT91_REG EMAC_CDE; /* Code Error Register */ + AT91_REG EMAC_ELR; /* Excessive Length Error Register */ + AT91_REG EMAC_RJB; /* Receive Jabber Register */ + AT91_REG EMAC_USF; /* Undersize Frame Register */ + AT91_REG EMAC_SQEE; /* SQE Test Error Register */ + AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ + AT91_REG Reserved2[3]; /* */ + AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ + AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ + AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ + AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ + AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ + AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ + AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ + AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ + AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ + AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ +} AT91S_EMAC, *AT91PS_EMAC; + +/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */ +#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */ +#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */ +#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ +#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ +#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ +#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ +#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */ +#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */ +#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */ + +/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */ +#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ +#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ +#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */ +#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ +#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ +#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */ +#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */ +#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */ +#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */ +#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ +#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */ +#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */ +#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */ +#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */ +#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */ +#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ + +/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */ +#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */ + +/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */ +#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */ +#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */ + +/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */ +#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */ +#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */ +#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ +#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ +#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */ + +/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */ +#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ + +/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */ +#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */ +#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */ +#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */ +#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */ +#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */ +#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */ +#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */ +#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */ +#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */ +#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */ +#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */ +#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */ + +/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */ +/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ +/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */ +/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */ +#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */ +#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */ +#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */ +#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */ +#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */ +#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */ +#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */ +#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */ +#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */ +#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */ +/******************************************************************************/ +typedef struct _AT91S_SPI +{ + AT91_REG SPI_CR; /* Control Register */ + AT91_REG SPI_MR; /* Mode Register */ + AT91_REG SPI_RDR; /* Receive Data Register */ + AT91_REG SPI_TDR; /* Transmit Data Register */ + AT91_REG SPI_SR; /* Status Register */ + AT91_REG SPI_IER; /* Interrupt Enable Register */ + AT91_REG SPI_IDR; /* Interrupt Disable Register */ + AT91_REG SPI_IMR; /* Interrupt Mask Register */ + AT91_REG Reserved0[4]; /* */ + AT91_REG SPI_CSR[4]; /* Chip Select Register */ + AT91_REG Reserved1[48]; /* */ + AT91_REG SPI_RPR; /* Receive Pointer Register */ + AT91_REG SPI_RCR; /* Receive Counter Register */ + AT91_REG SPI_TPR; /* Transmit Pointer Register */ + AT91_REG SPI_TCR; /* Transmit Counter Register */ + AT91_REG SPI_RNPR; /* Receive Next Pointer Register */ + AT91_REG SPI_RNCR; /* Receive Next Counter Register */ + AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */ + AT91_REG SPI_TNCR; /* Transmit Next Counter Register */ + AT91_REG SPI_PTCR; /* PDC Transfer Control Register */ + AT91_REG SPI_PTSR; /* PDC Transfer Status Register */ +} AT91S_SPI, *AT91PS_SPI; + +/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */ +#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */ +#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */ +#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */ + +/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */ +#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */ +#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */ +#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */ +#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */ +#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */ +#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */ +#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */ +#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */ +#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */ +#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */ + +/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */ +#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */ +#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ + +/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */ +#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */ +#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */ + +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */ +#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */ +#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */ +#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */ +#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */ +#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */ +#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */ +#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */ + +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */ +/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */ +#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */ +#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */ +#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */ +#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */ +#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */ +#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */ +#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */ +#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */ +#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */ +#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */ +#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */ +#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */ +#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */ +#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */ + +/******************************************************************************/ +/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */ +/******************************************************************************/ +typedef struct _AT91S_PDC +{ + AT91_REG PDC_RPR; /* Receive Pointer Register */ + AT91_REG PDC_RCR; /* Receive Counter Register */ + AT91_REG PDC_TPR; /* Transmit Pointer Register */ + AT91_REG PDC_TCR; /* Transmit Counter Register */ + AT91_REG PDC_RNPR; /* Receive Next Pointer Register */ + AT91_REG PDC_RNCR; /* Receive Next Counter Register */ + AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */ + AT91_REG PDC_TNCR; /* Transmit Next Counter Register */ + AT91_REG PDC_PTCR; /* PDC Transfer Control Register */ + AT91_REG PDC_PTSR; /* PDC Transfer Status Register */ +} AT91S_PDC, *AT91PS_PDC; + +/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */ +#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */ +#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */ +#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */ +#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */ +/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */ + +/* ========== Register definition ==================================== */ +#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */ +#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */ +#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */ +#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ +#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */ +#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */ +#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */ +#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */ +#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */ +#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */ +#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */ +#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */ +#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */ +#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */ +#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */ +#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */ +#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */ +#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */ +#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */ +#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */ +#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */ +#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */ +#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */ +#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */ +#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */ +#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */ +#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */ +#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */ +#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */ +#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */ +#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */ +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ + +#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ +#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ +#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ +#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ +#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ +#define AT91C_PA25_TWD ((unsigned int) 1 << 25) +#define AT91C_PA26_TWCK ((unsigned int) 1 << 26) +#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ +#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */ +#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */ +#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */ +#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */ +#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */ +#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */ +#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */ +#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */ + +#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ +#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */ +#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */ +#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */ +#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */ +#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */ +#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */ +#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */ +#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ +#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */ +#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ + +#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ +#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ +#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ +#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ +#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ +#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ +#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ + +#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ +#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */ + +#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ +#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */ +#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ +#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */ +#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ +#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */ +#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */ +#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */ +#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ +#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */ +#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ +#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */ +#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ +#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */ + +#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ +#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ +#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ +#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ +#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ +#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ +#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ +#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ +#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ +#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ +#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ +#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ +#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ +#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ +#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ +#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ +#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ +#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ +#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ +#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ + +#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */ +#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */ +#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */ +#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ +#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */ +#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ +#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ +#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ +#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ +#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ +#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ +#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ +#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ +#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ +#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ +#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ +#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ +#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ +#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ +#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ +#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ +#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ +#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ +#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ +#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ +#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ +#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ +#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ +#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ +#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ +#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ +#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ + +#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ +#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ + +#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ +#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ +#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ +#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ +#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ +#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ +#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */ + +#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */ +#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ +#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */ +#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ +#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ +#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */ +#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */ +#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */ +#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ +#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ +#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ +#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */ +#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ +#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ +#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ +#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ +#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ +#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ +#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ +#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ +#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ + +#endif diff --git a/arch/arm/mach-at91rm9200/include/mach/hardware.h b/arch/arm/mach-at91rm9200/include/mach/hardware.h new file mode 100644 index 0000000000..a84c60a992 --- /dev/null +++ b/arch/arm/mach-at91rm9200/include/mach/hardware.h @@ -0,0 +1,78 @@ +/* + * linux/include/asm-arm/arch-at91/hardware.h + * + * Copyright (C) 2003 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <sizes.h> + +#ifndef __ASSEMBLY__ +#include "AT91RM9200.h" +#else +#include "AT91RM9200_inc.h" +#endif + +/* Virtual and Physical base address for system peripherals */ +#define AT91_SYS_BASE 0xFFFFF000 /*4K */ + +/* Virtual and Physical base addresses of user peripherals */ +#define AT91_SPI_BASE 0xFFFE0000 /*16K */ +#define AT91_SSC2_BASE 0xFFFD8000 /*16K */ +#define AT91_SSC1_BASE 0xFFFD4000 /*16K */ +#define AT91_SSC0_BASE 0xFFFD0000 /*16K */ +#define AT91_USART3_BASE 0xFFFCC000 /*16K */ +#define AT91_USART2_BASE 0xFFFC8000 /*16K */ +#define AT91_USART1_BASE 0xFFFC4000 /*16K */ +#define AT91_USART0_BASE 0xFFFC0000 /*16K */ +#define AT91_EMAC_BASE 0xFFFBC000 /*16K */ +#define AT91_TWI_BASE 0xFFFB8000 /*16K */ +#define AT91_MCI_BASE 0xFFFB4000 /*16K */ +#define AT91_UDP_BASE 0xFFFB0000 /*16K */ +#define AT91_TCB1_BASE 0xFFFA4000 /*16K */ +#define AT91_TCB0_BASE 0xFFFA0000 /*16K */ + +#define AT91_USB_HOST_BASE 0x00300000 +#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE + +/* + * Where in virtual memory the IO devices (timers, system controllers + * and so on) + */ +#define AT91_IO_BASE 0xF0000000 /* Virt/Phys Address of IO */ + +/* FLASH */ +#define AT91_FLASH_BASE 0x10000000 /* NCS0 */ + +/* SDRAM */ +#define AT91_SDRAM_BASE 0x20000000 /* NCS1 */ + +/* SmartMedia */ +#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3 */ + +/* Definition of interrupt priority levels */ +#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST +#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1) +#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2) +#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3) +#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4) +#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5) +#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6) +#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST + +#endif diff --git a/arch/arm/mach-imx/clko.c b/arch/arm/mach-imx/clko.c index 11edfb5ed2..6a8072213c 100644 --- a/arch/arm/mach-imx/clko.c +++ b/arch/arm/mach-imx/clko.c @@ -1,8 +1,8 @@ #include <common.h> #include <command.h> #include <getopt.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> +#include <mach/imx-regs.h> +#include <mach/clock.h> static int do_clko (cmd_tbl_t *cmdtp, int argc, char *argv[]) { diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index 6c5cc11410..09d43183b8 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -33,8 +33,8 @@ #include <init.h> #include <clock.h> #include <notifier.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> +#include <mach/imx-regs.h> +#include <mach/clock.h> #define GPT(x) __REG(IMX_TIM1_BASE + (x)) diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c index 49566e41c3..2e1362c965 100644 --- a/arch/arm/mach-imx/gpio.c +++ b/arch/arm/mach-imx/gpio.c @@ -24,7 +24,7 @@ */ #include <common.h> -#include <asm/arch/imx-regs.h> +#include <mach/imx-regs.h> void imx_gpio_mode(int gpio_mode) { diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c index 90b1eef99c..0741f112a3 100644 --- a/arch/arm/mach-imx/imx21.c +++ b/arch/arm/mach-imx/imx21.c @@ -16,7 +16,7 @@ */ #include <common.h> -#include <asm/arch/imx-regs.h> +#include <mach/imx-regs.h> int imx_silicon_revision(void) { diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c index 7255a77704..c33346aaf6 100644 --- a/arch/arm/mach-imx/imx27.c +++ b/arch/arm/mach-imx/imx27.c @@ -16,7 +16,7 @@ */ #include <common.h> -#include <asm/arch/imx-regs.h> +#include <mach/imx-regs.h> int imx_silicon_revision(void) { diff --git a/arch/arm/mach-imx/include/mach/clock-imx1.h b/arch/arm/mach-imx/include/mach/clock-imx1.h new file mode 100644 index 0000000000..8d456b84b2 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/clock-imx1.h @@ -0,0 +1,5 @@ +#ifndef ASM_ARCH_CLOCK_IMX1_H +#define ASM_ARCH_CLOCK_IMX1_H + +#endif /* ASM_ARCH_CLOCK_IMX1_H */ + diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h new file mode 100644 index 0000000000..c60417922b --- /dev/null +++ b/arch/arm/mach-imx/include/mach/clock.h @@ -0,0 +1,34 @@ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); + +ulong imx_get_mpllclk(void); + +#ifdef CONFIG_ARCH_IMX27 +ulong imx_get_armclk(void); +#endif +#ifdef CONFIG_ARCH_IMX1 +static inline ulong imx_get_armclk(void) +{ + return imx_get_mpllclk(); +} +#endif + +ulong imx_get_spllclk(void); +ulong imx_get_fclk(void); +ulong imx_get_hclk(void); +ulong imx_get_bclk(void); +ulong imx_get_perclk1(void); +ulong imx_get_perclk2(void); +ulong imx_get_perclk3(void); +ulong imx_get_ahbclk(void); +ulong imx_get_fecclk(void); +ulong imx_get_gptclk(void); +ulong imx_get_uartclk(void); +ulong imx_get_lcdclk(void); + +int imx_clko_set_div(int div); +void imx_clko_set_src(int src); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h new file mode 100644 index 0000000000..7f3c66fc62 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -0,0 +1,34 @@ + +/* SDRAM Controller registers */ +#define ESDCTL0 __REG(IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */ +#define ESDCFG0 __REG(IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */ +#define ESDCTL1 __REG(IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */ +#define ESDCFG1 __REG(IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */ +#define ESDMISC __REG(IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */ + +#define ESDCTL0_SDE (1 << 31) +#define ESDCTL0_SMODE_NORMAL (0 << 28) +#define ESDCTL0_SMODE_PRECHARGE (1 << 28) +#define ESDCTL0_SMODE_AUTO_REFRESH (2 << 28) +#define ESDCTL0_SMODE_LOAD_MODE (3 << 28) +#define ESDCTL0_SMODE_MANUAL_SELF_REFRESH (4 << 28) +#define ESDCTL0_SP (1 << 27) +#define ESDCTL0_ROW11 (0 << 24) +#define ESDCTL0_ROW12 (1 << 24) +#define ESDCTL0_ROW13 (2 << 24) +#define ESDCTL0_ROW14 (3 << 24) +#define ESDCTL0_ROW15 (4 << 24) +#define ESDCTL0_COL8 (0 << 20) +#define ESDCTL0_COL9 (1 << 20) +#define ESDCTL0_COL10 (2 << 20) +#define ESDCTL0_DSIZ_31_16 (0 << 16) +#define ESDCTL0_DSIZ_15_0 (1 << 16) +#define ESDCTL0_DSIZ_31_0 (2 << 16) +#define ESDCTL0_REF1 (1 << 13) +#define ESDCTL0_REF2 (2 << 13) +#define ESDCTL0_REF4 (3 << 13) +#define ESDCTL0_REF8 (4 << 13) +#define ESDCTL0_REF16 (5 << 13) +#define ESDCTL0_FP (1 << 8) +#define ESDCTL0_BL (1 << 7) + diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h new file mode 100644 index 0000000000..99a53a49a4 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -0,0 +1,41 @@ + +int imx_silicon_revision(void); +#define IMX27_CHIP_REVISION_1_0 0 +#define IMX27_CHIP_REVISION_2_0 1 + +#ifdef CONFIG_ARCH_IMX1 +#define cpu_is_mx1() (1) +#else +#define cpu_is_mx1() (0) +#endif + +#ifdef CONFIG_ARCH_IMX21 +#define cpu_is_mx21() (1) +#else +#define cpu_is_mx21() (0) +#endif + +#ifdef CONFIG_ARCH_IMX25 +#define cpu_is_mx25() (1) +#else +#define cpu_is_mx25() (0) +#endif + +#ifdef CONFIG_ARCH_IMX27 +#define cpu_is_mx27() (1) +#else +#define cpu_is_mx27() (0) +#endif + +#ifdef CONFIG_ARCH_IMX31 +#define cpu_is_mx31() (1) +#else +#define cpu_is_mx31() (0) +#endif + +#ifdef CONFIG_ARCH_IMX35 +#define cpu_is_mx35() (1) +#else +#define cpu_is_mx35() (0) +#endif + diff --git a/arch/arm/mach-imx/include/mach/gpio.h b/arch/arm/mach-imx/include/mach/gpio.h new file mode 100644 index 0000000000..71298f4e54 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/gpio.h @@ -0,0 +1,10 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +void imx_gpio_mode(int gpio_mode); +void gpio_set_value(unsigned gpio, int value); +int gpio_direction_output(unsigned gpio, int value); +int gpio_direction_input(unsigned gpio); + +#endif /* __ASM_ARCH_GPIO_H */ + diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h new file mode 100644 index 0000000000..500bb1a9e4 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx-nand.h @@ -0,0 +1,14 @@ +#ifndef __ASM_ARCH_NAND_H +#define __ASM_ARCH_NAND_H + +#include <linux/mtd/mtd.h> + +void imx_nand_load_image(void *dest, int size, int pagesize, int blocksize); + +struct imx_nand_platform_data { + int width; + int hw_ecc; + int is2k; + }; +#endif /* __ASM_ARCH_NAND_H */ + diff --git a/arch/arm/mach-imx/include/mach/imx-pll.h b/arch/arm/mach-imx/include/mach/imx-pll.h new file mode 100644 index 0000000000..df7e73efea --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx-pll.h @@ -0,0 +1,18 @@ +#ifndef __INCLUDE_ASM_ARCH_IMX_PLL_H +#define __INCLUDE_ASM_ARCH_IMX_PLL_H + +/* + * This can be used for various PLLs found on + * i.MX SoCs. + * + * mfi + mfn / (mfd + 1) + * fpll = 2 * fref * --------------------- + * pd + 1 + */ +#define IMX_PLL_PD(x) (((x) & 0xf) << 26) +#define IMX_PLL_MFD(x) (((x) & 0x3ff) << 16) +#define IMX_PLL_MFI(x) (((x) & 0xf) << 10) +#define IMX_PLL_MFN(x) (((x) & 0x3ff) << 0) +#define IMX_PLL_BRMO (1 << 31) + +#endif /* __INCLUDE_ASM_ARCH_IMX_PLL_H*/ diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h new file mode 100644 index 0000000000..459714e9b4 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx-regs.h @@ -0,0 +1,125 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_REGS_H +#define _IMX_REGS_H + +/* ------------------------------------------------------------------------ + * Motorola IMX system registers + * ------------------------------------------------------------------------ + */ + +# ifndef __ASSEMBLY__ +# define __REG(x) (*((volatile u32 *)(x))) +# define __REG16(x) (*(volatile u16 *)(x)) +# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) +# else +# define __REG(x) (x) +# define __REG16(x) (x) +# define __REG2(x,y) ((x)+(y)) +#endif + +#ifdef CONFIG_ARCH_IMX1 +# include <mach/imx1-regs.h> +#elif defined CONFIG_ARCH_IMX21 +# include <mach/imx21-regs.h> +#elif defined CONFIG_ARCH_IMX27 +# include <mach/imx27-regs.h> +#elif defined CONFIG_ARCH_IMX31 +# include <mach/imx31-regs.h> +#elif defined CONFIG_ARCH_IMX35 +# include <mach/imx35-regs.h> +#elif defined CONFIG_ARCH_IMX25 +# include <mach/imx25-regs.h> +#else +# error "unknown i.MX soc type" +#endif + +/* + * GPIO Module and I/O Multiplexer + * x = 0..3 for reg_A, reg_B, reg_C, reg_D + * + * i.MX1 and i.MXL: 0 <= x <= 3 + * i.MX27 : 0 <= x <= 5 + */ +#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8) +#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8) +#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8) +#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8) +#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8) +#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8) +#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8) +#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8) +#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8) +#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8) +#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8) +#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8) +#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8) +#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8) +#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8) +#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8) +#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8) + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + +#define GPIO_OUT (1 << 8) +#define GPIO_IN (0 << 8) +#define GPIO_PUEN (1 << 9) + +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) + +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) + +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + +#define GPIO_GIUS (1<<16) + +#endif /* _IMX_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h new file mode 100644 index 0000000000..0d6fd9200e --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx1-regs.h @@ -0,0 +1,241 @@ +#ifndef _IMX1_REGS_H +#define _IMX1_REGS_H + +#ifndef _IMX_REGS_H +#error "Please do not include directly" +#endif + +#define IMX_IO_BASE 0x00200000 + +/* + * Register BASEs, based on OFFSETs + */ +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) +#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) +#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) +#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) +#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) +#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) +#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) +#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) +#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) +#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) +#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) +#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) +#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) +#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) +#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) +#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) +#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) +#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) +#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) +#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) +#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) + +/* Watchdog Registers*/ +#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ +#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x01 + +/* SYSCTRL Registers */ +#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */ +#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */ +#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */ + +/* SDRAM controller registers */ + +#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */ +#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */ +#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */ +#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */ + +/* PLL registers */ +#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ +#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ +#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ +#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ + +#define CSCR_MPLL_RESTART (1<<21) + +/* Chip Select Registers */ +#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */ +#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */ +#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */ +#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */ +#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ +#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ +#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ +#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */ +#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ +#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ +#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ +#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */ +#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ + +/* assignements for GPIO alternate/primary functions */ + +/* FIXME: This list is not completed. The correct directions are + * missing on some (many) pins + */ +#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) +#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) +#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) +#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) +#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) +#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) +#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) +#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) +#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) +#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) +#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) +#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) +#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) +#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) +#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) +#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) +#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) +#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) +#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) +#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) +#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) +#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) +#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) +#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) +#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) +#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) +#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) +#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) +#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) +#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) +#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) +#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) +#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) +#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) +#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) +#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) +#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) +#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) +#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) +#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) +#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) +#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) +#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) +#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) +#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) +#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) +#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) +#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) +#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) +#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) +#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) +#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) +#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) +#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) +#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) +#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) +#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) +#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) +#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) +#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) +#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) +#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) +#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) +#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) +#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) +#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) +#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) +#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) +#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) +#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) +#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) +#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) +#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) +#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) +#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) +#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) +#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) +#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) +#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) +#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) +#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) +#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) +#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) +#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) +#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) +#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) +#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) +#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) +#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) +#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) +#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) +#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) +#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) +#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) +#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) +#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) +#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) +#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) +#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) +#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) +#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) +#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) +#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) +#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) +#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) +#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) +#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) +#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) +#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) +#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) +#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) +#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) +#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) +#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) +#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) +#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) +#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) +#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) +#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) +#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) +#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) +#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) +#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) +#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) + +/* + * Definitions for the clocksource driver + */ +/* Part 1: Registers */ +# define GPT_TCTL 0x00 +# define GPT_TPRER 0x04 +# define GPT_TCMP 0x08 +# define GPT_TCR 0x0c +# define GPT_TCN 0x10 +# define GPT_TSTAT 0x14 + +/* Part 2: Bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_FRR (1<<8) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_OM (1<<5) /* output mode */ +#define TCTL_IRQEN (1<<4) /* interrupt enable */ +#define TCTL_CLKSOURCE (1) /* Clock source bit position */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +#endif /* _IMX1_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h new file mode 100644 index 0000000000..b8cb06075f --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx21-regs.h @@ -0,0 +1,150 @@ +#ifndef _IMX21_REGS_H +#define _IMX21_REGS_H + +#ifndef _IMX_REGS_H +#error "Please do not include directly" +#endif + +#define IMX_IO_BASE 0x10000000 + +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) +#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) +#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) +#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) +#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) + +#define IMX_SDRAM_BASE (0xdf000000) +#define IMX_EIM_BASE (0xdf001000) +#define IMX_NFC_BASE (0xdf003000) + +/* AIPI */ +#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00) +#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04) +#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00) +#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04) + +/* System Control */ +#define SUID0 __REG(IMX_SYSTEM_CTL_BASE + 0x4) /* Silicon ID Register (12 bytes) */ +#define SUID1 __REG(IMX_SYSTEM_CTL_BASE + 0x8) /* Silicon ID Register (12 bytes) */ +#define CID __REG(IMX_SYSTEM_CTL_BASE + 0xC) /* Silicon ID Register (12 bytes) */ +#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */ +#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */ +#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */ +#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ + +#define GPCR_BOOT_SHIFT 16 +#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) +#define GPCR_BOOT_UART_USB 0 +#define GPCR_BOOT_8BIT_NAND_2k 2 +#define GPCR_BOOT_16BIT_NAND_2k 3 +#define GPCR_BOOT_16BIT_NAND_512 4 +#define GPCR_BOOT_16BIT_CS0 5 +#define GPCR_BOOT_32BIT_CS0 6 +#define GPCR_BOOT_8BIT_NAND_512 7 + +/* SDRAM Controller registers bitfields */ +#define SDCTL0 __REG(IMX_SDRAM_BASE + 0x00) /* SDRAM 0 Control Register */ +#define SDCTL1 __REG(IMX_SDRAM_BASE + 0x04) /* SDRAM 0 Control Register */ +#define SDRST __REG(IMX_SDRAM_BASE + 0x18) /* SDRAM Reset Register */ +#define SDMISC __REG(IMX_SDRAM_BASE + 0x14) /* SDRAM Miscellaneous Register */ + + +/* Chip Select Registers */ +#define CS0U __REG(IMX_EIM_BASE + 0x00) /* Chip Select 0 Upper Register */ +#define CS0L __REG(IMX_EIM_BASE + 0x04) /* Chip Select 0 Lower Register */ +#define CS1U __REG(IMX_EIM_BASE + 0x08) /* Chip Select 1 Upper Register */ +#define CS1L __REG(IMX_EIM_BASE + 0x0C) /* Chip Select 1 Lower Register */ +#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ +#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ +#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ +#define CS3L __REG(IMX_EIM_BASE + 0x1C) /* Chip Select 3 Lower Register */ +#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ +#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ +#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ +#define CS5L __REG(IMX_EIM_BASE + 0x2C) /* Chip Select 5 Lower Register */ +#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ + +/* Watchdog Registers*/ +#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +#define WRSR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Reset Status Register */ + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +/* PLL registers */ +#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ +#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */ +#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ +#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */ +#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */ +#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */ +#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */ +#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */ +#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */ + +#define CSCR_MPEN (1 << 0) +#define CSCR_SPEN (1 << 1) +#define CSCR_FPM_EN (1 << 2) +#define CSCR_OSC26M_DIS (1 << 3) +#define CSCR_OSC26M_DIV1P5 (1 << 4) +#define CSCR_MCU_SEL (1 << 16) +#define CSCR_SP_SEL (1 << 17) +#define CSCR_SD_CNT(d) (((d) & 0x3) << 24) +#define CSCR_USB_DIV(d) (((d) & 0x7) << 26) +#define CSCR_PRESC(d) (((d) & 0x7) << 29) + +#define MPCTL1_BRMO (1 << 6) +#define MPCTL1_LF (1 << 15) + +#define PCCR1_GPT1_EN (1 << 25) + +#define CCSR_32K_SR (1 << 15) + +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) + +/* + * Definitions for the clocksource driver + */ +/* Part 1: Registers */ +# define GPT_TCTL 0x00 +# define GPT_TPRER 0x04 +# define GPT_TCMP 0x08 +# define GPT_TCR 0x0c +# define GPT_TCN 0x10 +# define GPT_TSTAT 0x14 + +/* Part 2: Bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_CC (1<<10) /* counter clear */ +#define TCTL_FRR (1<<8) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_CAPEN (1<<5) /* compare interrupt enable */ +#define TCTL_COMPEN (1<<4) /* compare interrupt enable */ +#define TCTL_CLKSOURCE (1) /* Clock source bit position */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +#define IMX_CS0_BASE 0xC8000000 +#define IMX_CS1_BASE 0xCC000000 +#define IMX_CS2_BASE 0xD0000000 +#define IMX_CS3_BASE 0xD1000000 +#define IMX_CS4_BASE 0xD2000000 +#define IMX_CS5_BASE 0xD3000000 + +#endif /* _IMX21_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx25-flash-header.h b/arch/arm/mach-imx/include/mach/imx25-flash-header.h new file mode 100644 index 0000000000..59860dbda7 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx25-flash-header.h @@ -0,0 +1,44 @@ + +#define __flash_header_start __section(.flash_header_start) +#define __flash_header __section(.flash_header) +#define __dcd_entry __section(.dcd_entry) +#define __image_len __section(.image_len) + +struct mx25_dcd_entry { + unsigned long ptr_type; + unsigned long addr; + unsigned long val; +}; + +#define DCD_BARKER 0xb17219e9 + +struct mx25_dcd_header { + unsigned long barker; + unsigned long block_len; +}; + +struct mx25_rsa_public_key { + unsigned char rsa_exponent[4]; + unsigned char *rsa_modululs; + unsigned short *exponent_size; + unsigned short modulus_size; + unsigned char init_flag; +}; + +#define APP_CODE_BARKER 0x000000b1 + +struct mx25_flash_header { + void *app_code_jump_vector; + unsigned long app_code_barker; + void *app_code_csf; + struct mx25_dcd_header **dcd_ptr_ptr; + struct mx25_rsa_public_key *super_root_key; + struct mx25_dcd_header *dcd; + void *app_dest; +}; + +struct mx25_nand_flash_header { + struct mx25_flash_header flash_header; + struct mx25_dcd_header dcd_header; +}; + diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h new file mode 100644 index 0000000000..efbdbaad9b --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -0,0 +1,142 @@ +/* + * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX25_REGS_H +#define __ASM_ARCH_MX35_REGS_H + +/* + * sanity check + */ +#ifndef _IMX_REGS_H +# error "Please do not include directly. Use imx-regs.h instead." +#endif + +#define IMX_L2CC_BASE 0x30000000 +#define IMX_UART1_BASE 0x43F90000 +#define IMX_UART2_BASE 0x43F94000 +#define IMX_TIM1_BASE 0x53F90000 +#define IMX_IOMUXC_BASE 0x43FAC000 +#define IMX_WDT_BASE 0x53FDC000 +#define IMX_MAX_BASE 0x43F04000 +#define IMX_ESD_BASE 0xb8001000 +#define IMX_AIPS1_BASE 0x43F00000 +#define IMX_AIPS2_BASE 0x53F00000 +#define IMX_CCM_BASE 0x53F80000 +#define IMX_IIM_BASE 0x53FF0000 +#define IMX_OTG_BASE 0x53FF4000 +#define IMX_M3IF_BASE 0xB8003000 +#define IMX_NAND_BASE 0xBB000000 + +/* + * Clock Controller Module (CCM) + */ +#define CCM_MPCTL 0x00 +#define CCM_UPCTL 0x04 +#define CCM_CCTL 0x08 +#define CCM_CGCR0 0x0C +#define CCM_CGCR1 0x10 +#define CCM_CGCR2 0x14 +#define CCM_PCDR0 0x18 +#define CCM_PCDR1 0x1C +#define CCM_PCDR2 0x20 +#define CCM_PCDR3 0x24 +#define CCM_RCSR 0x28 +#define CCM_CRDR 0x2C +#define CCM_DCVR0 0x30 +#define CCM_DCVR1 0x34 +#define CCM_DCVR2 0x38 +#define CCM_DCVR3 0x3c +#define CCM_LTR0 0x40 +#define CCM_LTR1 0x44 +#define CCM_LTR2 0x48 +#define CCM_LTR3 0x4c + +#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) +#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) +#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) +#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20) +#define PDR0_AUTO_CON (1 << 0) +#define PDR0_PER_SEL (1 << 26) + +/* + * Adresses and ranges of the external chip select lines + */ +#define IMX_CS0_BASE 0xA0000000 +#define IMX_CS0_RANGE (128 * 1024 * 1024) +#define IMX_CS1_BASE 0xA8000000 +#define IMX_CS1_RANGE (128 * 1024 * 1024) +#define IMX_CS2_BASE 0xB0000000 +#define IMX_CS2_RANGE (32 * 1024 * 1024) +#define IMX_CS3_BASE 0xB2000000 +#define IMX_CS3_RANGE (32 * 1024 * 1024) +#define IMX_CS4_BASE 0xB4000000 +#define IMX_CS4_RANGE (32 * 1024 * 1024) +#define IMX_CS5_BASE 0xB6000000 +#define IMX_CS5_RANGE (32 * 1024 * 1024) + +#define IMX_SDRAM_CS0 0x80000000 +#define IMX_SDRAM_CS1 0x90000000 + +#define WEIM_BASE 0xb8002000 +#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) +#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) +#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) + +/* + * Definitions for the clocksource driver + * + * These defines are using the i.MX1/27 notation + * to reuse the clocksource code for these CPUs + * on the i.MX35 + */ +/* Part 1: Registers */ +#define GPT_TCTL 0x00 +#define GPT_TPRER 0x04 +#define GPT_TCMP 0x10 +#define GPT_TCR 0x1c +#define GPT_TCN 0x24 +#define GPT_TSTAT 0x08 + +/* Part 2: Bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_FRR (1<<9) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_OM (1<<5) /* output mode */ +#define TCTL_IRQEN (1<<4) /* interrupt enable */ +#define TCTL_CLKSOURCE (6) /* Clock source bit position */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +/* + * Watchdog Registers + */ +#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +#endif /* __ASM_ARCH_MX25_REGS_H */ + diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h new file mode 100644 index 0000000000..33d67d6f50 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx27-regs.h @@ -0,0 +1,354 @@ +#ifndef _IMX27_REGS_H +#define _IMX27_REGS_H + +#ifndef _IMX_REGS_H +#error "Please do not include directly" +#endif + +#define IMX_IO_BASE 0x10000000 + +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) +#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) +#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) +#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) +#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) +#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) +#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) +#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) +#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) +#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) +#define IMX_OTG_BASE (0x24000 + IMX_IO_BASE) + +#define IMX_NFC_BASE (0xd8000000) +#define IMX_ESD_BASE (0xd8001000) +#define IMX_WEIM_BASE (0xd8002000) + +/* AIPI */ +#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00) +#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04) +#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00) +#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04) + +/* System Control */ +#define CID __REG(IMX_SYSTEM_CTL_BASE + 0x0) /* Chip ID Register */ +#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */ +#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */ +#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */ +#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ + +#define GPCR_BOOT_SHIFT 16 +#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) +#define GPCR_BOOT_UART_USB 0 +#define GPCR_BOOT_8BIT_NAND_2k 2 +#define GPCR_BOOT_16BIT_NAND_2k 3 +#define GPCR_BOOT_16BIT_NAND_512 4 +#define GPCR_BOOT_16BIT_CS0 5 +#define GPCR_BOOT_32BIT_CS0 6 +#define GPCR_BOOT_8BIT_NAND_512 7 + +/* Chip Select Registers */ +#define CS0U __REG(IMX_WEIM_BASE + 0x00) /* Chip Select 0 Upper Register */ +#define CS0L __REG(IMX_WEIM_BASE + 0x04) /* Chip Select 0 Lower Register */ +#define CS0A __REG(IMX_WEIM_BASE + 0x08) /* Chip Select 0 Addition Register */ +#define CS1U __REG(IMX_WEIM_BASE + 0x10) /* Chip Select 1 Upper Register */ +#define CS1L __REG(IMX_WEIM_BASE + 0x14) /* Chip Select 1 Lower Register */ +#define CS1A __REG(IMX_WEIM_BASE + 0x18) /* Chip Select 1 Addition Register */ +#define CS2U __REG(IMX_WEIM_BASE + 0x20) /* Chip Select 2 Upper Register */ +#define CS2L __REG(IMX_WEIM_BASE + 0x24) /* Chip Select 2 Lower Register */ +#define CS2A __REG(IMX_WEIM_BASE + 0x28) /* Chip Select 2 Addition Register */ +#define CS3U __REG(IMX_WEIM_BASE + 0x30) /* Chip Select 3 Upper Register */ +#define CS3L __REG(IMX_WEIM_BASE + 0x34) /* Chip Select 3 Lower Register */ +#define CS3A __REG(IMX_WEIM_BASE + 0x38) /* Chip Select 3 Addition Register */ +#define CS4U __REG(IMX_WEIM_BASE + 0x40) /* Chip Select 4 Upper Register */ +#define CS4L __REG(IMX_WEIM_BASE + 0x44) /* Chip Select 4 Lower Register */ +#define CS4A __REG(IMX_WEIM_BASE + 0x48) /* Chip Select 4 Addition Register */ +#define CS5U __REG(IMX_WEIM_BASE + 0x50) /* Chip Select 5 Upper Register */ +#define CS5L __REG(IMX_WEIM_BASE + 0x54) /* Chip Select 5 Lower Register */ +#define CS5A __REG(IMX_WEIM_BASE + 0x58) /* Chip Select 5 Addition Register */ +#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */ + +#include "esdctl.h" + +/* Watchdog Registers*/ +#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ +#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +/* PLL registers */ +#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ +#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ +#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */ +#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */ +#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ +#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */ +#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */ +#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */ +#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */ +#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */ +#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */ + +#define CSCR_MPEN (1 << 0) +#define CSCR_SPEN (1 << 1) +#define CSCR_FPM_EN (1 << 2) +#define CSCR_OSC26M_DIS (1 << 3) +#define CSCR_OSC26M_DIV1P5 (1 << 4) +#define CSCR_AHB_DIV(d) (((d) & 0x3) << 8) +#define CSCR_ARM_DIV(d) (((d) & 0x3) << 12) +#define CSCR_ARM_SRC_MPLL (1 << 15) +#define CSCR_MCU_SEL (1 << 16) +#define CSCR_SP_SEL (1 << 17) +#define CSCR_MPLL_RESTART (1 << 18) +#define CSCR_SPLL_RESTART (1 << 19) +#define CSCR_MSHC_SEL (1 << 20) +#define CSCR_H264_SEL (1 << 21) +#define CSCR_SSI1_SEL (1 << 22) +#define CSCR_SSI2_SEL (1 << 23) +#define CSCR_SD_CNT(d) (((d) & 0x3) << 24) +#define CSCR_USB_DIV(d) (((d) & 0x7) << 28) +#define CSCR_UPDATE_DIS (1 << 31) + +#define MPCTL1_BRMO (1 << 6) +#define MPCTL1_LF (1 << 15) + +#define PCCR0_SSI2_EN (1 << 0) +#define PCCR0_SSI1_EN (1 << 1) +#define PCCR0_SLCDC_EN (1 << 2) +#define PCCR0_SDHC3_EN (1 << 3) +#define PCCR0_SDHC2_EN (1 << 4) +#define PCCR0_SDHC1_EN (1 << 5) +#define PCCR0_SDC_EN (1 << 6) +#define PCCR0_SAHARA_EN (1 << 7) +#define PCCR0_RTIC_EN (1 << 8) +#define PCCR0_RTC_EN (1 << 9) +#define PCCR0_PWM_EN (1 << 11) +#define PCCR0_OWIRE_EN (1 << 12) +#define PCCR0_MSHC_EN (1 << 13) +#define PCCR0_LCDC_EN (1 << 14) +#define PCCR0_KPP_EN (1 << 15) +#define PCCR0_IIM_EN (1 << 16) +#define PCCR0_I2C2_EN (1 << 17) +#define PCCR0_I2C1_EN (1 << 18) +#define PCCR0_GPT6_EN (1 << 19) +#define PCCR0_GPT5_EN (1 << 20) +#define PCCR0_GPT4_EN (1 << 21) +#define PCCR0_GPT3_EN (1 << 22) +#define PCCR0_GPT2_EN (1 << 23) +#define PCCR0_GPT1_EN (1 << 24) +#define PCCR0_GPIO_EN (1 << 25) +#define PCCR0_FEC_EN (1 << 26) +#define PCCR0_EMMA_EN (1 << 27) +#define PCCR0_DMA_EN (1 << 28) +#define PCCR0_CSPI3_EN (1 << 29) +#define PCCR0_CSPI2_EN (1 << 30) +#define PCCR0_CSPI1_EN (1 << 31) + +#define PCCR1_MSHC_BAUDEN (1 << 2) +#define PCCR1_NFC_BAUDEN (1 << 3) +#define PCCR1_SSI2_BAUDEN (1 << 4) +#define PCCR1_SSI1_BAUDEN (1 << 5) +#define PCCR1_H264_BAUDEN (1 << 6) +#define PCCR1_PERCLK4_EN (1 << 7) +#define PCCR1_PERCLK3_EN (1 << 8) +#define PCCR1_PERCLK2_EN (1 << 9) +#define PCCR1_PERCLK1_EN (1 << 10) +#define PCCR1_HCLK_USB (1 << 11) +#define PCCR1_HCLK_SLCDC (1 << 12) +#define PCCR1_HCLK_SAHARA (1 << 13) +#define PCCR1_HCLK_RTIC (1 << 14) +#define PCCR1_HCLK_LCDC (1 << 15) +#define PCCR1_HCLK_H264 (1 << 16) +#define PCCR1_HCLK_FEC (1 << 17) +#define PCCR1_HCLK_EMMA (1 << 18) +#define PCCR1_HCLK_EMI (1 << 19) +#define PCCR1_HCLK_DMA (1 << 20) +#define PCCR1_HCLK_CSI (1 << 21) +#define PCCR1_HCLK_BROM (1 << 22) +#define PCCR1_HCLK_ATA (1 << 23) +#define PCCR1_WDT_EN (1 << 24) +#define PCCR1_USB_EN (1 << 25) +#define PCCR1_UART6_EN (1 << 26) +#define PCCR1_UART5_EN (1 << 27) +#define PCCR1_UART4_EN (1 << 28) +#define PCCR1_UART3_EN (1 << 29) +#define PCCR1_UART2_EN (1 << 30) +#define PCCR1_UART1_EN (1 << 31) + +#define CCSR_32K_SR (1 << 15) + +/* SDRAM Controller registers bitfields */ +#define ESDCTL_PRCT(x) (((x) & 3f) << 0) +#define ESDCTL_BL (1 << 7) +#define ESDCTL_FP (1 << 8) +#define ESDCTL_PWDT(x) (((x) & 3) << 10) +#define ESDCTL_SREFR(x) (((x) & 7) << 13) +#define ESDCTL_DSIZ_16_UPPER (0 << 16) +#define ESDCTL_DSIZ_16_LOWER (0 << 16) +#define ESDCTL_DSIZ_32 (0 << 16) +#define ESDCTL_COL8 (0 << 20) +#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL10 (2 << 20) +#define ESDCTL_ROW11 (0 << 24) +#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW13 (2 << 24) +#define ESDCTL_ROW14 (3 << 24) +#define ESDCTL_ROW15 (4 << 24) +#define ESDCTL_SP (1 << 27) +#define ESDCTL_SMODE_NORMAL (0 << 28) +#define ESDCTL_SMODE_PRECHAGRE (1 << 28) +#define ESDCTL_SMODE_AUTO_REF (2 << 28) +#define ESDCTL_SMODE_LOAD_MODE (3 << 28) +#define ESDCTL_SMODE_MAN_REF (4 << 28) +#define ESDCTL_SDE (1 << 31) + +#define ESDCFG_TRC(x) (((x) & 0xf) << 0) +#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) +#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) +#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) +#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) +#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) +#define ESDCFG_TRP(x) (((x) & 0x3) << 18) +#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TXP(x) (((x) & 0x3) << 21) + +#define ESDMISC_RST (1 << 1) +#define ESDMISC_MDDREN (1 << 2) +#define ESDMISC_MDDR_DL_RST (1 << 3) +#define ESDMISC_MDDR_MDIS (1 << 4) +#define ESDMISC_LHD (1 << 5) +#define ESDMISC_MA10_SHARE (1 << 6) +#define ESDMISC_SDRAM_RDY (1 << 6) + +#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) +#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) +#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) +#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) +#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) +#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) +#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) +#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) +#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) +#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) +#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) +#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) +#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) +#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) +#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) +#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) +#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) +#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) +#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) +#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) +#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) +#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) +#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) +#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) +#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) +#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) +#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) +#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) +#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) +#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) +#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) +#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) +#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) +#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) +#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) +#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) +#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) +#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) +#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) +#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) +#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) +#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) +#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) +#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) +#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) +#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) +#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) +#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) +#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) +#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) +#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) +#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) +#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) +#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) +#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) +#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) +#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) +#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) +#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) +#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) +#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) +#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) +#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) +#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30) +#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31) +#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) +#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) +#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) +#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) +#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) +#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) +#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) +#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) +#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) + +/* + * Definitions for the clocksource driver + */ +/* Part 1: Registers */ +# define GPT_TCTL 0x00 +# define GPT_TPRER 0x04 +# define GPT_TCMP 0x08 +# define GPT_TCR 0x0c +# define GPT_TCN 0x10 +# define GPT_TSTAT 0x14 + +/* Part 2: Bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_FRR (1<<8) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_OM (1<<5) /* output mode */ +#define TCTL_IRQEN (1<<4) /* interrupt enable */ +#define TCTL_CLKSOURCE (1) /* Clock source bit position */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +#define IMX_CS0_BASE 0xC0000000 +#define IMX_CS1_BASE 0xC8000000 +#define IMX_CS2_BASE 0xD0000000 +#define IMX_CS3_BASE 0xD2000000 +#define IMX_CS4_BASE 0xD4000000 +#define IMX_CS5_BASE 0xD6000000 + +#endif /* _IMX27_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h new file mode 100644 index 0000000000..3cae3a21db --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx31-regs.h @@ -0,0 +1,258 @@ +/* + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX31_REGS_H +#define __ASM_ARCH_MX31_REGS_H + +/* + * sanity check + */ +#ifndef _IMX_REGS_H +# error "Please do not include directly. Use imx-regs.h instead." +#endif + +#define IMX_OTG_BASE 0x43F88000 +#define IMX_UART1_BASE 0x43F90000 +#define IMX_UART2_BASE 0x43F94000 +#define IMX_WDT_BASE 0x53FDC000 +#define IMX_RTC_BASE 0x53FD8000 +#define IMX_TIM1_BASE 0x53F90000 +#define IMX_IIM_BASE 0x5001C000 + +#define IMX_SDRAM_CS0 0x80000000 +#define IMX_SDRAM_CS1 0x90000000 + +/* + * Adresses and ranges of the external chip select lines + */ +#define IMX_CS0_BASE 0xA0000000 +#define IMX_CS0_RANGE (128 * 1024 * 1024) +#define IMX_CS1_BASE 0xA8000000 +#define IMX_CS1_RANGE (128 * 1024 * 1024) +#define IMX_CS2_BASE 0xB0000000 +#define IMX_CS2_RANGE (32 * 1024 * 1024) +#define IMX_CS3_BASE 0xB2000000 +#define IMX_CS3_RANGE (32 * 1024 * 1024) +#define IMX_CS4_BASE 0xB4000000 +#define IMX_CS4_RANGE (32 * 1024 * 1024) +#define IMX_CS5_BASE 0xB6000000 +#define IMX_CS5_RANGE (32 * 1024 * 1024) + +/* + * Definitions for the clocksource driver + * + * These defines are using the i.MX1/27 notation + * to reuse the clocksource code for these CPUs + * on the i.MX31 + */ +/* Part 1: Registers */ +#define GPT_TCTL 0x00 +#define GPT_TPRER 0x04 +#define GPT_TCMP 0x10 +#define GPT_TCR 0x1c +#define GPT_TCN 0x24 +#define GPT_TSTAT 0x08 + +/* Part 2: Bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_FRR (1<<9) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_OM (1<<5) /* output mode */ +#define TCTL_IRQEN (1<<4) /* interrupt enable */ +#define TCTL_CLKSOURCE (6) /* Clock source bit position */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +#if 0 +#define IMX_IO_BASE 0x00200000 + +/* + * Register BASEs, based on OFFSETs + */ +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define (0x01000 + IMX_IO_BASE) + (0x02000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) + (0x04000 + IMX_IO_BASE) +#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) +#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) +#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) +#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) +#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) +#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) +#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) +#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) +#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) +#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) +#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) +#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) +#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) +#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) +#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) +#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) +#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) +#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) +#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) +#endif + +/* + * Watchdog Registers + */ +#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +/* + * Clock Controller Module (CCM) + */ +#define IMX_CCM_BASE 0x53f80000 +#define CCM_CCMR 0x00 +#define CCM_PDR0 0x04 +#define CCM_PDR1 0x08 +#define CCM_RCSR 0x0c +#define CCM_MPCTL 0x10 +#define CCM_UPCTL 0x10 +#define CCM_SPCTL 0x18 +#define CCM_COSR 0x1C + +/* + * ????????????? + */ +#define CCMR_MDS (1 << 7) +#define CCMR_SBYCS (1 << 4) +#define CCMR_MPE (1 << 3) +#define CCMR_PRCS_MASK (3 << 1) +#define CCMR_FPM (1 << 1) +#define CCMR_CKIH (2 << 1) + +#define RCSR_NFMS (1 << 30) + +/* + * ????????????? + */ +#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) +#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) +#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) +#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) +#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) +#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) +#define PDR0_MCU_PODF(x) ((x) & 0x7) + +#define IMX_ESD_BASE 0xb8001000 +#include "esdctl.h" + +/* + * NFC Registers + */ +#define IMX_NFC_BASE (0xb8000000) + +/* + * Chip Select Registers + */ +#define WEIM_BASE 0xb8002000 +#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) +#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) +#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) + +/* + * ??????????? + */ +#define IOMUXC_BASE 0x43FAC000 +#define IOMUXC_GPR (IOMUXC_BASE + 0x8) +#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) +#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) + +#define IPU_BASE 0x53fc0000 +#define IPU_CONF IPU_BASE + +#define IPU_CONF_PXL_ENDIAN (1<<8) +#define IPU_CONF_DU_EN (1<<7) +#define IPU_CONF_DI_EN (1<<6) +#define IPU_CONF_ADC_EN (1<<5) +#define IPU_CONF_SDC_EN (1<<4) +#define IPU_CONF_PF_EN (1<<3) +#define IPU_CONF_ROT_EN (1<<2) +#define IPU_CONF_IC_EN (1<<1) +#define IPU_CONF_SCI_EN (1<<0) + +#define WDOG_BASE 0x53FDC000 + +/* + * Signal Multiplexing (IOMUX) + */ + +/* bits in the SW_MUX_CTL registers */ +#define MUX_CTL_OUT_GPIO_DR (0 << 4) +#define MUX_CTL_OUT_FUNC (1 << 4) +#define MUX_CTL_OUT_ALT1 (2 << 4) +#define MUX_CTL_OUT_ALT2 (3 << 4) +#define MUX_CTL_OUT_ALT3 (4 << 4) +#define MUX_CTL_OUT_ALT4 (5 << 4) +#define MUX_CTL_OUT_ALT5 (6 << 4) +#define MUX_CTL_OUT_ALT6 (7 << 4) +#define MUX_CTL_IN_NONE (0 << 0) +#define MUX_CTL_IN_GPIO (1 << 0) +#define MUX_CTL_IN_FUNC (2 << 0) +#define MUX_CTL_IN_ALT1 (4 << 0) +#define MUX_CTL_IN_ALT2 (8 << 0) + +#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) +#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) +#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) +#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) + +/* Register offsets based on IOMUXC_BASE */ +/* 0x00 .. 0x7b */ +#define MUX_CTL_RTS1 0x7c +#define MUX_CTL_CTS1 0x7d +#define MUX_CTL_DTR_DCE1 0x7e +#define MUX_CTL_DSR_DCE1 0x7f +#define MUX_CTL_CSPI2_SCLK 0x80 +#define MUX_CTL_CSPI2_SPI_RDY 0x81 +#define MUX_CTL_RXD1 0x82 +#define MUX_CTL_TXD1 0x83 +#define MUX_CTL_CSPI2_MISO 0x84 +/* 0x85 .. 0x8a */ +#define MUX_CTL_CSPI2_MOSI 0x8b + +/* The modes a specific pin can be in + * these macros can be used in mx31_gpio_mux() and have the form + * MUX_[contact name]__[pin function] + */ +#define MUX_RXD1_UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1) +#define MUX_TXD1_UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1) +#define MUX_RTS1_UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1) +#define MUX_RTS1_UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1) + +#define MUX_CSPI2_MOSI_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) +#define MUX_CSPI2_MISO_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) + +#endif /* __ASM_ARCH_MX31_REGS_H */ + diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h new file mode 100644 index 0000000000..db1eeba70d --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -0,0 +1,136 @@ +/* + * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX35_REGS_H +#define __ASM_ARCH_MX35_REGS_H + +/* + * sanity check + */ +#ifndef _IMX_REGS_H +# error "Please do not include directly. Use imx-regs.h instead." +#endif + +#define IMX_L2CC_BASE 0x30000000 +#define IMX_UART1_BASE 0x43F90000 +#define IMX_UART2_BASE 0x43F94000 +#define IMX_TIM1_BASE 0x53F90000 +#define IMX_IOMUXC_BASE 0x43FAC000 +#define IMX_WDT_BASE 0x53FDC000 +#define IMX_MAX_BASE 0x43F04000 +#define IMX_ESD_BASE 0xb8001000 +#define IMX_AIPS1_BASE 0x43F00000 +#define IMX_AIPS2_BASE 0x53F00000 +#define IMX_CCM_BASE 0x53F80000 +#define IMX_IIM_BASE 0x53FF0000 +#define IMX_M3IF_BASE 0xB8003000 +#define IMX_NAND_BASE 0xBB000000 + +/* + * Clock Controller Module (CCM) + */ +#define CCM_CCMR 0x00 +#define CCM_PDR0 0x04 +#define CCM_PDR1 0x08 +#define CCM_PDR2 0x0C +#define CCM_PDR3 0x10 +#define CCM_PDR4 0x14 +#define CCM_RCSR 0x18 +#define CCM_MPCTL 0x1C +#define CCM_PPCTL 0x20 +#define CCM_ACMR 0x24 +#define CCM_COSR 0x28 +#define CCM_CGR0 0x2C +#define CCM_CGR1 0x30 +#define CCM_CGR2 0x34 +#define CCM_CGR3 0x38 + +#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) +#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) +#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) +#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20) +#define PDR0_AUTO_CON (1 << 0) +#define PDR0_PER_SEL (1 << 26) + +/* + * Adresses and ranges of the external chip select lines + */ +#define IMX_CS0_BASE 0xA0000000 +#define IMX_CS0_RANGE (128 * 1024 * 1024) +#define IMX_CS1_BASE 0xA8000000 +#define IMX_CS1_RANGE (128 * 1024 * 1024) +#define IMX_CS2_BASE 0xB0000000 +#define IMX_CS2_RANGE (32 * 1024 * 1024) +#define IMX_CS3_BASE 0xB2000000 +#define IMX_CS3_RANGE (32 * 1024 * 1024) +#define IMX_CS4_BASE 0xB4000000 +#define IMX_CS4_RANGE (32 * 1024 * 1024) +#define IMX_CS5_BASE 0xB6000000 +#define IMX_CS5_RANGE (32 * 1024 * 1024) + +#define IMX_SDRAM_CS0 0x80000000 +#define IMX_SDRAM_CS1 0x90000000 + +#define WEIM_BASE 0xb8002000 +#define CSCR_U(x) (WEIM_BASE + (x) * 0x10) +#define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) +#define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10) + +/* + * Definitions for the clocksource driver + * + * These defines are using the i.MX1/27 notation + * to reuse the clocksource code for these CPUs + * on the i.MX35 + */ +/* Part 1: Registers */ +#define GPT_TCTL 0x00 +#define GPT_TPRER 0x04 +#define GPT_TCMP 0x10 +#define GPT_TCR 0x1c +#define GPT_TCN 0x24 +#define GPT_TSTAT 0x08 + +/* Part 2: Bitfields */ +#define TCTL_SWR (1<<15) /* Software reset */ +#define TCTL_FRR (1<<9) /* Freerun / restart */ +#define TCTL_CAP (3<<6) /* Capture Edge */ +#define TCTL_OM (1<<5) /* output mode */ +#define TCTL_IRQEN (1<<4) /* interrupt enable */ +#define TCTL_CLKSOURCE (6) /* Clock source bit position */ +#define TCTL_TEN (1) /* Timer enable */ +#define TPRER_PRES (0xff) /* Prescale */ +#define TSTAT_CAPT (1<<1) /* Capture event */ +#define TSTAT_COMP (1) /* Compare event */ + +/* + * Watchdog Registers + */ +#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +#endif /* __ASM_ARCH_MX35_REGS_H */ + diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h new file mode 100644 index 0000000000..ca7ea32fb4 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/imxfb.h @@ -0,0 +1,75 @@ +/* + * This structure describes the machine which we are running on. + */ + +#include <fb.h> + +#define PCR_TFT (1 << 31) +#define PCR_COLOR (1 << 30) +#define PCR_PBSIZ_1 (0 << 28) +#define PCR_PBSIZ_2 (1 << 28) +#define PCR_PBSIZ_4 (2 << 28) +#define PCR_PBSIZ_8 (3 << 28) +#define PCR_BPIX_1 (0 << 25) +#define PCR_BPIX_2 (1 << 25) +#define PCR_BPIX_4 (2 << 25) +#define PCR_BPIX_8 (3 << 25) +#define PCR_BPIX_12 (4 << 25) +#define PCR_BPIX_16 (5 << 25) +#define PCR_BPIX_18 (6 << 25) +#define PCR_PIXPOL (1 << 24) +#define PCR_FLMPOL (1 << 23) +#define PCR_LPPOL (1 << 22) +#define PCR_CLKPOL (1 << 21) +#define PCR_OEPOL (1 << 20) +#define PCR_SCLKIDLE (1 << 19) +#define PCR_END_SEL (1 << 18) +#define PCR_END_BYTE_SWAP (1 << 17) +#define PCR_REV_VS (1 << 16) +#define PCR_ACD_SEL (1 << 15) +#define PCR_ACD(x) (((x) & 0x7f) << 8) +#define PCR_SCLK_SEL (1 << 7) +#define PCR_SHARP (1 << 6) +#define PCR_PCD(x) ((x) & 0x3f) + +#define PWMR_CLS(x) (((x) & 0x1ff) << 16) +#define PWMR_LDMSK (1 << 15) +#define PWMR_SCR1 (1 << 10) +#define PWMR_SCR0 (1 << 9) +#define PWMR_CC_EN (1 << 8) +#define PWMR_PW(x) ((x) & 0xff) + +#define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26) +#define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16) +#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8) +#define LSCR1_GRAY2(x) (((x) & 0xf) << 4) +#define LSCR1_GRAY1(x) (((x) & 0xf)) + +#define DMACR_BURST (1 << 31) +#define DMACR_HM(x) (((x) & 0xf) << 16) +#define DMACR_TM(x) ((x) & 0xf) + +struct imx_fb_videomode { + struct fb_videomode mode; + u32 pcr; + unsigned char bpp; +}; + +struct imx_fb_platform_data { + struct imx_fb_videomode *mode; + + u_int cmap_greyscale:1, + cmap_inverse:1, + cmap_static:1, + unused:29; + + u_int pwmr; + u_int lscr1; + u_int dmacr; + + void *framebuffer; + void *framebuffer_ovl; +}; + +void set_imx_fb_info(struct imx_fb_platform_data *); + diff --git a/arch/arm/mach-imx/include/mach/iomux-mx25.h b/arch/arm/mach-imx/include/mach/iomux-mx25.h new file mode 100644 index 0000000000..020b7f214f --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx25.h @@ -0,0 +1,773 @@ +#ifndef __MACH_IOMUX_MX25_H__ +#define __MACH_IOMUX_MX25_H__ + +#include <mach/iomux-v3.h> + +#define SRE (1 << 0) +#define DSE_STD (0 << 1) +#define DSE_HIGH (1 << 1) +#define DSE_MAX (2 << 1) +#define ODE (1 << 3) +#define PUS_100K_DOWN (0 << 4) +#define PUS_47K_UP (1 << 4) +#define PUS_100K_UP (2 << 4) +#define PUS_22K_UP (3 << 4) +#define PUE (1 << 6) +#define PKE (1 << 7) +#define HYS (1 << 8) +#define DVS (1 << 13) + +#define MX25_PAD_A10__EIM_DA_H10 IOMUX_PAD(0x000, 0x8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A10__GPIO0 IOMUX_PAD(0x000, 0x8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A13__EIM_DA_H13 IOMUX_PAD(0x22c, 0xc, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A13__GPIO1 IOMUX_PAD(0x22c, 0xc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A13__LCDC_CLS IOMUX_PAD(0x22c, 0xc, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A14__EIM_DA_H214 IOMUX_PAD(0x230, 0x10, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A14__GPIO0 IOMUX_PAD(0x230, 0x10, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A14__CLK1 IOMUX_PAD(0x230, 0x10, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A14__LCDC_SPL IOMUX_PAD(0x230, 0x10, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A15__EIM_DA_H215 IOMUX_PAD(0x234, 0x14, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A15__GPIO1 IOMUX_PAD(0x234, 0x14, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A15__RST1 IOMUX_PAD(0x234, 0x14, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A15__LCDC_PS IOMUX_PAD(0x234, 0x14, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A16__EIM_A16 IOMUX_PAD(0x000, 0x18, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A16__GPIO2 IOMUX_PAD(0x000, 0x18, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A16__VEN1 IOMUX_PAD(0x000, 0x18, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A16__LCDC_REV IOMUX_PAD(0x000, 0x18, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A17__EIM_A17 IOMUX_PAD(0x238, 0x1c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A17__GPIO3 IOMUX_PAD(0x238, 0x1c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A17__TX1 IOMUX_PAD(0x238, 0x1c, 6, 0x554, 0, NO_PAD_CTRL) +#define MX25_PAD_A17__TX_ERR IOMUX_PAD(0x238, 0x1c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A18__EIM_A18 IOMUX_PAD(0x23c, 0x20, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A18__GPIO4 IOMUX_PAD(0x23c, 0x20, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A18__PD1 IOMUX_PAD(0x23c, 0x20, 6, 0x550, 0, NO_PAD_CTRL) +#define MX25_PAD_A18__COL IOMUX_PAD(0x23c, 0x20, 7, 0x504, 0, NO_PAD_CTRL) +#define MX25_PAD_A19__EIM_A19 IOMUX_PAD(0x240, 0x24, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A19__GPIO5 IOMUX_PAD(0x240, 0x24, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A19__RX1 IOMUX_PAD(0x240, 0x24, 6, 0x54c, 0, NO_PAD_CTRL) +#define MX25_PAD_A19__RX_ERR IOMUX_PAD(0x240, 0x24, 7, 0x518, 0, NO_PAD_CTRL) +#define MX25_PAD_A20__EIM_A20 IOMUX_PAD(0x244, 0x28, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A20__GPIO6 IOMUX_PAD(0x244, 0x28, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A20__CLK1 IOMUX_PAD(0x244, 0x28, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A20__RDATA2 IOMUX_PAD(0x244, 0x28, 7, 0x50c, 0, NO_PAD_CTRL) +#define MX25_PAD_A21__EIM_A21 IOMUX_PAD(0x248, 0x2c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A21__GPIO7 IOMUX_PAD(0x248, 0x2c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A21__RST1 IOMUX_PAD(0x248, 0x2c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A21__RDATA3 IOMUX_PAD(0x248, 0x2c, 7, 0x510, 0, NO_PAD_CTRL) +#define MX25_PAD_A22__EIM_A22 IOMUX_PAD(0x000, 0x30, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A22__GPIO8 IOMUX_PAD(0x000, 0x30, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A22__VEN1 IOMUX_PAD(0x000, 0x30, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A22__TDATA2 IOMUX_PAD(0x000, 0x30, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A23__EIM_A23 IOMUX_PAD(0x24c, 0x34, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A23__GPIO9 IOMUX_PAD(0x24c, 0x34, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A23__TX1 IOMUX_PAD(0x24c, 0x34, 6, 0x560, 0, NO_PAD_CTRL) +#define MX25_PAD_A23__TDATA3 IOMUX_PAD(0x24c, 0x34, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A24__EIM_A24 IOMUX_PAD(0x250, 0x38, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A24__GPIO10 IOMUX_PAD(0x250, 0x38, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A24__PD1 IOMUX_PAD(0x250, 0x38, 6, 0x55c, 0, NO_PAD_CTRL) +#define MX25_PAD_A24__RX_CLK IOMUX_PAD(0x250, 0x38, 7, 0x514, 0, NO_PAD_CTRL) +#define MX25_PAD_A25__EIM_A25 IOMUX_PAD(0x254, 0x3c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A25__GPIO11 IOMUX_PAD(0x254, 0x3c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_A25__RX1 IOMUX_PAD(0x254, 0x3c, 6, 0x558, 0, NO_PAD_CTRL) +#define MX25_PAD_A25__CRS IOMUX_PAD(0x254, 0x3c, 7, 0x508, 0, NO_PAD_CTRL) +#define MX25_PAD_BCLK__EIM_BCLK IOMUX_PAD(0x000, 0x68, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BCLK__GPIO4 IOMUX_PAD(0x000, 0x68, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE0__GPIO30 IOMUX_PAD(0x000, 0x224, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_BOOT_MODE1__GPIO31 IOMUX_PAD(0x000, 0x228, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CLKO__CLKO IOMUX_PAD(0x414, 0x220, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CLKO__GPIO21 IOMUX_PAD(0x414, 0x220, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__LCDC_CONTRAST IOMUX_PAD(0x310, 0x118, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__CAPIN1 IOMUX_PAD(0x310, 0x118, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__SS1 IOMUX_PAD(0x310, 0x118, 2, 0x4a8, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__DA_2 IOMUX_PAD(0x310, 0x118, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__PWMO IOMUX_PAD(0x310, 0x118, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__CRS IOMUX_PAD(0x310, 0x118, 5, 0x508, 1, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__USBH2_PWR IOMUX_PAD(0x310, 0x118, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CONTRAST__WDOG_B IOMUX_PAD(0x310, 0x118, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS0__EIM_CS0 IOMUX_PAD(0x000, 0x4c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS0__GPIO2 IOMUX_PAD(0x000, 0x4c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS1__EIM_CS1 IOMUX_PAD(0x000, 0x50, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS1__NANDF_CE3 IOMUX_PAD(0x000, 0x50, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS1__GPIO3 IOMUX_PAD(0x000, 0x50, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__EIM_CS4 IOMUX_PAD(0x264, 0x54, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__NANDF_CE1 IOMUX_PAD(0x264, 0x54, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__CTS IOMUX_PAD(0x264, 0x54, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__AUD4_RXC IOMUX_PAD(0x264, 0x54, 4, 0x468, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__GPIO20 IOMUX_PAD(0x264, 0x54, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__MOSI IOMUX_PAD(0x264, 0x54, 6, 0x4b8, 0, NO_PAD_CTRL) +#define MX25_PAD_CS4__TRSYNC IOMUX_PAD(0x264, 0x54, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__EIM_CS5 IOMUX_PAD(0x268, 0x58, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__NANDF_CE2 IOMUX_PAD(0x268, 0x58, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__DTACK_B IOMUX_PAD(0x268, 0x58, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__RTS IOMUX_PAD(0x268, 0x58, 3, 0x574, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__AUD4_RXFS IOMUX_PAD(0x268, 0x58, 4, 0x46c, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__GPIO21 IOMUX_PAD(0x268, 0x58, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__MISO IOMUX_PAD(0x268, 0x58, 6, 0x4b4, 0, NO_PAD_CTRL) +#define MX25_PAD_CS5__TRCLK IOMUX_PAD(0x268, 0x58, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__CSI_D2 IOMUX_PAD(0x318, 0x120, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__RXD_MUX IOMUX_PAD(0x318, 0x120, 1, 0x578, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__DAT4 IOMUX_PAD(0x318, 0x120, 2, 0x4f4, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__SCKR IOMUX_PAD(0x318, 0x120, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__CLK0 IOMUX_PAD(0x318, 0x120, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__GPIO27 IOMUX_PAD(0x318, 0x120, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__MOSI IOMUX_PAD(0x318, 0x120, 7, 0x4b8, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D2__USBOTG_DATA0 IOMUX_PAD(0x318, 0x120, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__CSI_D3 IOMUX_PAD(0x31c, 0x124, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__TXD_MUX IOMUX_PAD(0x31c, 0x124, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__DAT5 IOMUX_PAD(0x31c, 0x124, 2, 0x4f8, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__FSR IOMUX_PAD(0x31c, 0x124, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__RST0 IOMUX_PAD(0x31c, 0x124, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__GPIO28 IOMUX_PAD(0x31c, 0x124, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__MISO IOMUX_PAD(0x31c, 0x124, 7, 0x4b4, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D3__USBOTG_DATA1 IOMUX_PAD(0x31c, 0x124, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__CSI_D4 IOMUX_PAD(0x320, 0x128, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__RTS IOMUX_PAD(0x320, 0x128, 1, 0x574, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__DAT6 IOMUX_PAD(0x320, 0x128, 2, 0x4fc, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__HCKR IOMUX_PAD(0x320, 0x128, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__VEN0 IOMUX_PAD(0x320, 0x128, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__GPIO29 IOMUX_PAD(0x320, 0x128, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__USBOTG_DATA2 IOMUX_PAD(0x320, 0x128, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D4__SCLK IOMUX_PAD(0x320, 0x128, 7, 0x4ac, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__CSI_D5 IOMUX_PAD(0x324, 0x12c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__CTS IOMUX_PAD(0x324, 0x12c, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__DAT7 IOMUX_PAD(0x324, 0x12c, 2, 0x500, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__SCKT IOMUX_PAD(0x324, 0x12c, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__TX0 IOMUX_PAD(0x324, 0x12c, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__GPIO30 IOMUX_PAD(0x324, 0x12c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__USBOTG_DATA3 IOMUX_PAD(0x324, 0x12c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D5__RDY IOMUX_PAD(0x324, 0x12c, 7, 0x4b0, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__CSI_D6 IOMUX_PAD(0x328, 0x130, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__ROW6 IOMUX_PAD(0x328, 0x130, 1, 0x544, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__CMD IOMUX_PAD(0x328, 0x130, 2, 0x4e0, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__FST IOMUX_PAD(0x328, 0x130, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__PD0 IOMUX_PAD(0x328, 0x130, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__GPIO31 IOMUX_PAD(0x328, 0x130, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__USBOTG_DATA4 IOMUX_PAD(0x328, 0x130, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D6__SS0 IOMUX_PAD(0x328, 0x130, 7, 0x4bc, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__CSI_D7 IOMUX_PAD(0x32c, 0x134, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__ROW7 IOMUX_PAD(0x32c, 0x134, 1, 0x548, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__CLK IOMUX_PAD(0x32c, 0x134, 2, 0x4dc, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__HCKT IOMUX_PAD(0x32c, 0x134, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__RX0 IOMUX_PAD(0x32c, 0x134, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__GPIO6 IOMUX_PAD(0x32c, 0x134, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__USBOTG_DATA5 IOMUX_PAD(0x32c, 0x134, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D7__SS1 IOMUX_PAD(0x32c, 0x134, 7, 0x4c0, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__CSI_D8 IOMUX_PAD(0x330, 0x138, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__COL6 IOMUX_PAD(0x330, 0x138, 1, 0x534, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__AUD6_RXC IOMUX_PAD(0x330, 0x138, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__TX5_RX0 IOMUX_PAD(0x330, 0x138, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__CLK0 IOMUX_PAD(0x330, 0x138, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__GPIO7 IOMUX_PAD(0x330, 0x138, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__USBOTG_DATA6 IOMUX_PAD(0x330, 0x138, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D8__SS2 IOMUX_PAD(0x330, 0x138, 7, 0x4c4, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__CSI_D9 IOMUX_PAD(0x334, 0x13c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__COL7 IOMUX_PAD(0x334, 0x13c, 1, 0x538, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__AUD6_RXFS IOMUX_PAD(0x334, 0x13c, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__TX4_RX1 IOMUX_PAD(0x334, 0x13c, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__RST0 IOMUX_PAD(0x334, 0x13c, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__GPIO21 IOMUX_PAD(0x334, 0x13c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__USBOTG_DATA7 IOMUX_PAD(0x334, 0x13c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_D9__SS3 IOMUX_PAD(0x334, 0x13c, 7, 0x4c8, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__CSI_HSYNC IOMUX_PAD(0x340, 0x148, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__AUD6_TXC IOMUX_PAD(0x340, 0x148, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__DAT2 IOMUX_PAD(0x340, 0x148, 2, 0x4ec, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__TX1 IOMUX_PAD(0x340, 0x148, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__PD0 IOMUX_PAD(0x340, 0x148, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__GPIO10 IOMUX_PAD(0x340, 0x148, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__USBOTG_NXT IOMUX_PAD(0x340, 0x148, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_HSYNC__BT_RES2 IOMUX_PAD(0x340, 0x148, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__CSI_MCLK IOMUX_PAD(0x338, 0x140, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__AUD6_TXD IOMUX_PAD(0x338, 0x140, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__DAT0 IOMUX_PAD(0x338, 0x140, 2, 0x4e4, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__TX3_RX2 IOMUX_PAD(0x338, 0x140, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__VEN0 IOMUX_PAD(0x338, 0x140, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__GPIO8 IOMUX_PAD(0x338, 0x140, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__USBOTG_DIR IOMUX_PAD(0x338, 0x140, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_MCLK__BT_RES0 IOMUX_PAD(0x338, 0x140, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS IOMUX_PAD(0x344, 0x14c, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__DAT3 IOMUX_PAD(0x344, 0x14c, 2, 0x4f0, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__TX0 IOMUX_PAD(0x344, 0x14c, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__RX0 IOMUX_PAD(0x344, 0x14c, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__GPIO11 IOMUX_PAD(0x344, 0x14c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__USBOTG_CLK IOMUX_PAD(0x344, 0x14c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_PIXCLK__BT_RES3 IOMUX_PAD(0x344, 0x14c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__CSI_VSYNC IOMUX_PAD(0x33c, 0x144, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__AUD6_RXD IOMUX_PAD(0x33c, 0x144, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__DAT1 IOMUX_PAD(0x33c, 0x144, 2, 0x4e8, 1, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__TX2_RX3 IOMUX_PAD(0x33c, 0x144, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__TX0 IOMUX_PAD(0x33c, 0x144, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__GPIO9 IOMUX_PAD(0x33c, 0x144, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__USBOTG_STP IOMUX_PAD(0x33c, 0x144, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSI_VSYNC__BT_RES1 IOMUX_PAD(0x33c, 0x144, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MISO__MISO IOMUX_PAD(0x354, 0x15c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MISO__TXD_MUX IOMUX_PAD(0x354, 0x15c, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MISO__SDMA_DBG_EVT_1 IOMUX_PAD(0x354, 0x15c, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MISO__GPIO15 IOMUX_PAD(0x354, 0x15c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MISO__SLCDC_DATA13 IOMUX_PAD(0x354, 0x15c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MISO__TRACE5 IOMUX_PAD(0x354, 0x15c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MOSI__MOSI IOMUX_PAD(0x350, 0x158, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MOSI__RXD_MUX IOMUX_PAD(0x350, 0x158, 2, 0x568, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MOSI__SDMA_DBG_EVT_0 IOMUX_PAD(0x350, 0x158, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MOSI__GPIO14 IOMUX_PAD(0x350, 0x158, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MOSI__SLCDC_DATA12 IOMUX_PAD(0x350, 0x158, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_MOSI__TRACE4 IOMUX_PAD(0x350, 0x158, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_RDY__RDY IOMUX_PAD(0x364, 0x16c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_RDY__SDMA_DBG_EVT_5 IOMUX_PAD(0x364, 0x16c, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_RDY__GPIO22 IOMUX_PAD(0x364, 0x16c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_RDY__SLCDC_DATA15 IOMUX_PAD(0x364, 0x16c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_RDY__TRACE9 IOMUX_PAD(0x364, 0x16c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SCLK__SCLK IOMUX_PAD(0x360, 0x168, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SCLK__CTS IOMUX_PAD(0x360, 0x168, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SCLK__SDMA_DBG_EVT_4 IOMUX_PAD(0x360, 0x168, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SCLK__GPIO18 IOMUX_PAD(0x360, 0x168, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SCLK__SLCDC_DATA14 IOMUX_PAD(0x360, 0x168, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SCLK__TRACE8 IOMUX_PAD(0x360, 0x168, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__SS0 IOMUX_PAD(0x358, 0x160, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__LCDC_LD16 IOMUX_PAD(0x358, 0x160, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__PWMO IOMUX_PAD(0x358, 0x160, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__SDMA_DBG_EVT_2 IOMUX_PAD(0x358, 0x160, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__GPIO16 IOMUX_PAD(0x358, 0x160, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__SLCDC_CS IOMUX_PAD(0x358, 0x160, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS0__TRACE6 IOMUX_PAD(0x358, 0x160, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__SS1 IOMUX_PAD(0x35c, 0x164, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__SDA IOMUX_PAD(0x35c, 0x164, 1, 0x528, 1, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__RTS IOMUX_PAD(0x35c, 0x164, 2, 0x564, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__SDMA_DBG_EVT_3 IOMUX_PAD(0x35c, 0x164, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__GPIO17 IOMUX_PAD(0x35c, 0x164, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__SLCDC_RS IOMUX_PAD(0x35c, 0x164, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_CSPI1_SS1__TRACE7 IOMUX_PAD(0x35c, 0x164, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D0__EIM_D0 IOMUX_PAD(0x2bc, 0xc4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D0__GPIO20 IOMUX_PAD(0x2bc, 0xc4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D10__EIM_D10 IOMUX_PAD(0x294, 0x9c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D10__LCDC_LD21 IOMUX_PAD(0x294, 0x9c, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D10__GPIO10 IOMUX_PAD(0x294, 0x9c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D10__USBOTG_OC IOMUX_PAD(0x294, 0x9c, 6, 0x57c, 0, NO_PAD_CTRL) +#define MX25_PAD_D11__EIM_D11 IOMUX_PAD(0x290, 0x98, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D11__LCDC_LD20 IOMUX_PAD(0x290, 0x98, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D11__GPIO9 IOMUX_PAD(0x290, 0x98, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D11__USBOTG_PWR IOMUX_PAD(0x290, 0x98, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D12__EIM_D12 IOMUX_PAD(0x28c, 0x94, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D12__GPIO8 IOMUX_PAD(0x28c, 0x94, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D12__DAT4 IOMUX_PAD(0x28c, 0x94, 6, 0x4cc, 0, NO_PAD_CTRL) +#define MX25_PAD_D12__LCDC_LD19 IOMUX_PAD(0x28c, 0x94, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D13__EIM_D13 IOMUX_PAD(0x288, 0x90, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D13__LCDC_LD18 IOMUX_PAD(0x288, 0x90, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D13__GPIO7 IOMUX_PAD(0x288, 0x90, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D13__DAT5 IOMUX_PAD(0x288, 0x90, 6, 0x4d0, 0, NO_PAD_CTRL) +#define MX25_PAD_D14__EIM_D14 IOMUX_PAD(0x284, 0x8c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D14__LCDC_LD17 IOMUX_PAD(0x284, 0x8c, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D14__GPIO6 IOMUX_PAD(0x284, 0x8c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D14__DAT6 IOMUX_PAD(0x284, 0x8c, 6, 0x4d4, 0, NO_PAD_CTRL) +#define MX25_PAD_D15__EIM_D15 IOMUX_PAD(0x280, 0x88, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D15__LCDC_LD16 IOMUX_PAD(0x280, 0x88, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D15__GPIO5 IOMUX_PAD(0x280, 0x88, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D15__DAT7 IOMUX_PAD(0x280, 0x88, 6, 0x4d8, 0, NO_PAD_CTRL) +#define MX25_PAD_D1__EIM_D1 IOMUX_PAD(0x2b8, 0xc0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D1__GPIO19 IOMUX_PAD(0x2b8, 0xc0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D2__EIM_D2 IOMUX_PAD(0x2b4, 0xbc, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D2__GPIO18 IOMUX_PAD(0x2b4, 0xbc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D3__EIM_D3 IOMUX_PAD(0x2b0, 0xb8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D3__GPIO17 IOMUX_PAD(0x2b0, 0xb8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D4__EIM_D4 IOMUX_PAD(0x2ac, 0xb4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D4__GPIO16 IOMUX_PAD(0x2ac, 0xb4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D5__EIM_D5 IOMUX_PAD(0x2a8, 0xb0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D5__GPIO15 IOMUX_PAD(0x2a8, 0xb0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D6__EIM_D6 IOMUX_PAD(0x2a4, 0xac, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D6__GPIO14 IOMUX_PAD(0x2a4, 0xac, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D7__EIM_D7 IOMUX_PAD(0x2a0, 0xa8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D7__GPIO13 IOMUX_PAD(0x2a0, 0xa8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D8__EIM_D8 IOMUX_PAD(0x29c, 0xa4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D8__LCDC_LD23 IOMUX_PAD(0x29c, 0xa4, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D8__GPIO12 IOMUX_PAD(0x29c, 0xa4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D8__USBH2_OC IOMUX_PAD(0x29c, 0xa4, 6, 0x580, 0, 0x1c0) +#define MX25_PAD_D9__EIM_D9 IOMUX_PAD(0x298, 0xa0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D9__LCDC_LD22 IOMUX_PAD(0x298, 0xa0, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D9__GPIO11 IOMUX_PAD(0x298, 0xa0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_D9__USBH2_PWR IOMUX_PAD(0x298, 0xa0, 6, 0, 0, 0x60) +#define MX25_PAD_DE_B__DE_B IOMUX_PAD(0x3ec, 0x1f0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_DE_B__GPIO20 IOMUX_PAD(0x3ec, 0x1f0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB0__EIM_EB0_B IOMUX_PAD(0x258, 0x40, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB0__AUD4_TXD IOMUX_PAD(0x258, 0x40, 4, 0x464, 0, NO_PAD_CTRL) +#define MX25_PAD_EB0__GPIO12 IOMUX_PAD(0x258, 0x40, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB0__SS0 IOMUX_PAD(0x258, 0x40, 6, 0x4bc, 0, NO_PAD_CTRL) +#define MX25_PAD_EB1__EIM_EB1_B IOMUX_PAD(0x25c, 0x44, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB1__AUD4_RXD IOMUX_PAD(0x25c, 0x44, 4, 0x460, 0, NO_PAD_CTRL) +#define MX25_PAD_EB1__GPIO13 IOMUX_PAD(0x25c, 0x44, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EB1__SS1 IOMUX_PAD(0x25c, 0x44, 6, 0x4c0, 0, NO_PAD_CTRL) +#define MX25_PAD_ECB__EIM_ECB IOMUX_PAD(0x270, 0x60, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_ECB__TXD_MUX IOMUX_PAD(0x270, 0x60, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_ECB__GPIO23 IOMUX_PAD(0x270, 0x60, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_ECB__SCLK IOMUX_PAD(0x270, 0x60, 6, 0x4ac, 0, NO_PAD_CTRL) +#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_EXT_ARMCLK__GPIO15 IOMUX_PAD(0x000, 0x20c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__MDC IOMUX_PAD(0x3c0, 0x1c8, 0, 0, 0, PUE) +#define MX25_PAD_FEC_MDC__CMD IOMUX_PAD(0x3c0, 0x1c8, 1, 0x4e0, 2, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__AUD4_TXD IOMUX_PAD(0x3c0, 0x1c8, 2, 0x464, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__DIOR IOMUX_PAD(0x3c0, 0x1c8, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__GPIO5 IOMUX_PAD(0x3c0, 0x1c8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__SDMA_DBG_PC_8 IOMUX_PAD(0x3c0, 0x1c8, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDC__LCDC_LD16 IOMUX_PAD(0x3c0, 0x1c8, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDIO__MDIO IOMUX_PAD(0x3c4, 0x1cc, 0, 0, 0, (HYS | PKE | PUE | PUS_22K_UP)) +#define MX25_PAD_FEC_MDIO__CLK IOMUX_PAD(0x3c4, 0x1cc, 1, 0x4dc, 2, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDIO__AUD4_RXD IOMUX_PAD(0x3c4, 0x1cc, 2, 0x460, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDIO__DIOW IOMUX_PAD(0x3c4, 0x1cc, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDIO__GPIO6 IOMUX_PAD(0x3c4, 0x1cc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDIO__SDMA_DBG_PC_9 IOMUX_PAD(0x3c4, 0x1cc, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_MDIO__LCDC_LD17 IOMUX_PAD(0x3c4, 0x1cc, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA0__RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0, 0, 0, (HYS | PKE | PUE)) +#define MX25_PAD_FEC_RDATA0__DAT3 IOMUX_PAD(0x3d4, 0x1dc, 1, 0x4f0, 2, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA0__AUD4_RXFS IOMUX_PAD(0x3d4, 0x1dc, 2, 0x46c, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA0__INTRQ IOMUX_PAD(0x3d4, 0x1dc, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA0__RXCAN IOMUX_PAD(0x3d4, 0x1dc, 4, 0x480, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA0__GPIO10 IOMUX_PAD(0x3d4, 0x1dc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA0__ROW5 IOMUX_PAD(0x3d4, 0x1dc, 6, 0x540, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA0__LCDC_LD21 IOMUX_PAD(0x3d4, 0x1dc, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA1__RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0, 0, 0, (HYS | PKE | PUE)) +#define MX25_PAD_FEC_RDATA1__SCL IOMUX_PAD(0x3d8, 0x1e0, 1, 0x51c, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA1__DAT4 IOMUX_PAD(0x3d8, 0x1e0, 2, 0x4f4, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA1__CS0 IOMUX_PAD(0x3d8, 0x1e0, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA1__TXCAN IOMUX_PAD(0x3d8, 0x1e0, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA1__GPIO11 IOMUX_PAD(0x3d8, 0x1e0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA1__COL4 IOMUX_PAD(0x3d8, 0x1e0, 6, 0x52c, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RDATA1__LCDC_LD22 IOMUX_PAD(0x3d8, 0x1e0, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RX_DV__RX_DV IOMUX_PAD(0x3dc, 0x1e4, 0, 0, 0, (HYS | PKE | PUE)) +#define MX25_PAD_FEC_RX_DV__SDA IOMUX_PAD(0x3dc, 0x1e4, 1, 0x520, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RX_DV__DAT5 IOMUX_PAD(0x3dc, 0x1e4, 2, 0x4f8, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_RX_DV__CS1 IOMUX_PAD(0x3dc, 0x1e4, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RX_DV__RXCAN IOMUX_PAD(0x3dc, 0x1e4, 4, 0x484, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RX_DV__GPIO12 IOMUX_PAD(0x3dc, 0x1e4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RX_DV__COL5 IOMUX_PAD(0x3dc, 0x1e4, 6, 0x530, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_RX_DV__LCDC_LD23 IOMUX_PAD(0x3dc, 0x1e4, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA0__TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0, 0, 0, PUE) +#define MX25_PAD_FEC_TDATA0__DAT0 IOMUX_PAD(0x3c8, 0x1d0, 1, 0x4e4, 2, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA0__AUD4_TXC IOMUX_PAD(0x3c8, 0x1d0, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA0__DMACK IOMUX_PAD(0x3c8, 0x1d0, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA0__GPIO7 IOMUX_PAD(0x3c8, 0x1d0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA0__SDMA_DBG_PC_10 IOMUX_PAD(0x3c8, 0x1d0, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA0__LCDC_LD18 IOMUX_PAD(0x3c8, 0x1d0, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0, 0, 0, PUE) +#define MX25_PAD_FEC_TDATA1__DAT1 IOMUX_PAD(0x3cc, 0x1d4, 1, 0x4e8, 2, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__AUD4_TXFS IOMUX_PAD(0x3cc, 0x1d4, 2, 0x474, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__RESET_B IOMUX_PAD(0x3cc, 0x1d4, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__GPIO8 IOMUX_PAD(0x3cc, 0x1d4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__SDMA_DBG_PC_11 IOMUX_PAD(0x3cc, 0x1d4, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TDATA1__LCDC_LD19 IOMUX_PAD(0x3cc, 0x1d4, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_CLK__TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0, 0, 0, (HYS | PKE | PUE)) +#define MX25_PAD_FEC_TX_CLK__PWMO IOMUX_PAD(0x3e0, 0x1e8, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_CLK__DAT6 IOMUX_PAD(0x3e0, 0x1e8, 2, 0x4fc, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_CLK__LCDC_LD16 IOMUX_PAD(0x3e0, 0x1e8, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_CLK__GPIO13 IOMUX_PAD(0x3e0, 0x1e8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_CLK__SDMA_DBG_PC_12 IOMUX_PAD(0x3e0, 0x1e8, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_CLK__M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x3e0, 0x1e8, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_EN__TX_EN IOMUX_PAD(0x3d0, 0x1d8, 0, 0, 0, PUE) +#define MX25_PAD_FEC_TX_EN__DAT2 IOMUX_PAD(0x3d0, 0x1d8, 1, 0x4ec, 2, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_EN__AUD4_RXC IOMUX_PAD(0x3d0, 0x1d8, 2, 0x468, 1, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_EN__IORDY IOMUX_PAD(0x3d0, 0x1d8, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_EN__TXCAN IOMUX_PAD(0x3d0, 0x1d8, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_EN__GPIO9 IOMUX_PAD(0x3d0, 0x1d8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_EN__ROW4 IOMUX_PAD(0x3d0, 0x1d8, 6, 0x53c, 0, NO_PAD_CTRL) +#define MX25_PAD_FEC_TX_EN__LCDC_LD20 IOMUX_PAD(0x3d0, 0x1d8, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__GPIO0 IOMUX_PAD(0x3f0, 0x1f4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__PWMO IOMUX_PAD(0x3f0, 0x1f4, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__ROW4 IOMUX_PAD(0x3f0, 0x1f4, 3, 0x53c, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__SCL IOMUX_PAD(0x3f0, 0x1f4, 4, 0x524, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__TXCAN IOMUX_PAD(0x3f0, 0x1f4, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_A__INT_MUX_OUT IOMUX_PAD(0x3f0, 0x1f4, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_B__GPIO1 IOMUX_PAD(0x3f4, 0x1f8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_B__PWMO IOMUX_PAD(0x3f4, 0x1f8, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 2, 0x57c, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_B__ROW5 IOMUX_PAD(0x3f4, 0x1f8, 3, 0x540, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_B__SDA IOMUX_PAD(0x3f4, 0x1f8, 4, 0x528, 2, NO_PAD_CTRL) +#define MX25_PAD_GPIO_B__RXCAN IOMUX_PAD(0x3f4, 0x1f8, 6, 0x480, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__GPIO2 IOMUX_PAD(0x3f8, 0x1fc, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__PWMO IOMUX_PAD(0x3f8, 0x1fc, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__SCL IOMUX_PAD(0x3f8, 0x1fc, 2, 0x51c, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__COL4 IOMUX_PAD(0x3f8, 0x1fc, 3, 0x52c, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__CAPIN1 IOMUX_PAD(0x3f8, 0x1fc, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__CSPI1_SS2 IOMUX_PAD(0x3f8, 0x1fc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__TXCAN IOMUX_PAD(0x3f8, 0x1fc, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_C__CSPI2_SS2 IOMUX_PAD(0x3f8, 0x1fc, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__GPIO3 IOMUX_PAD(0x3fc, 0x200, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__WDOG_B IOMUX_PAD(0x3fc, 0x200, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__SDA IOMUX_PAD(0x3fc, 0x200, 2, 0x520, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__COL5 IOMUX_PAD(0x3fc, 0x200, 3, 0x530, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__CMPOUT1 IOMUX_PAD(0x3fc, 0x200, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__RXCAN IOMUX_PAD(0x3fc, 0x200, 6, 0x484, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_D__SS2 IOMUX_PAD(0x3fc, 0x200, 7, 0x4c4, 1, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__GPIO4 IOMUX_PAD(0x400, 0x204, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__SCL IOMUX_PAD(0x400, 0x204, 1, 0x524, 2, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__LCDC_LD16 IOMUX_PAD(0x400, 0x204, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__RXD_MUX IOMUX_PAD(0x400, 0x204, 6, 0x570, 2, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__CTI_TRIG_IN0_6 IOMUX_PAD(0x400, 0x204, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__GPIO5 IOMUX_PAD(0x404, 0x208, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__LCDC_LD17 IOMUX_PAD(0x404, 0x208, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__EPITO IOMUX_PAD(0x404, 0x208, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__AUD7_TXC IOMUX_PAD(0x404, 0x208, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__TXD_MUX IOMUX_PAD(0x404, 0x208, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__CTI_TRIG_OUT0_6 IOMUX_PAD(0x404, 0x208, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_HSYNC__LCDC_HSYN IOMUX_PAD(0x300, 0x108, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_HSYNC__SCL IOMUX_PAD(0x300, 0x108, 2, 0x524, 0, NO_PAD_CTRL) +#define MX25_PAD_HSYNC__BUFFER_EN IOMUX_PAD(0x300, 0x108, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_HSYNC__VEN1 IOMUX_PAD(0x300, 0x108, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_HSYNC__GPIO22 IOMUX_PAD(0x300, 0x108, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_HSYNC__USBH2_DATA4 IOMUX_PAD(0x300, 0x108, 6, 0, 0, 0xe5) +#define MX25_PAD_HSYNC__BT_UART_SRC1 IOMUX_PAD(0x300, 0x108, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_CLK__SCL IOMUX_PAD(0x348, 0x150, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_CLK__GPIO12 IOMUX_PAD(0x348, 0x150, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_CLK__SLCDC_DATA6 IOMUX_PAD(0x348, 0x150, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_DAT__SDA IOMUX_PAD(0x34c, 0x154, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_DAT__GPIO13 IOMUX_PAD(0x34c, 0x154, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_I2C1_DAT__SLCDC_DATA7 IOMUX_PAD(0x34c, 0x154, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL0__COL0 IOMUX_PAD(0x3b0, 0x1b8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL0__RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 1, 0x570, 1, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL0__AUD5_TXD IOMUX_PAD(0x3b0, 0x1b8, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL0__GPIO1 IOMUX_PAD(0x3b0, 0x1b8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL0__SDMA_DBG_PC_4 IOMUX_PAD(0x3b0, 0x1b8, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL1__COL1 IOMUX_PAD(0x3b4, 0x1bc, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL1__TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL1__AUD5_RXD IOMUX_PAD(0x3b4, 0x1bc, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL1__GPIO2 IOMUX_PAD(0x3b4, 0x1bc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL1__SDMA_DBG_PC_5 IOMUX_PAD(0x3b4, 0x1bc, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__COL2 IOMUX_PAD(0x3b8, 0x1c0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__RTS IOMUX_PAD(0x3b8, 0x1c0, 1, 0x56c, 1, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__AUD5_TXC IOMUX_PAD(0x3b8, 0x1c0, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__GPIO3 IOMUX_PAD(0x3b8, 0x1c0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__SDMA_DBG_PC_6 IOMUX_PAD(0x3b8, 0x1c0, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL2__M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x3b8, 0x1c0, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__COL3 IOMUX_PAD(0x3bc, 0x1c4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__CTS IOMUX_PAD(0x3bc, 0x1c4, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__AUD5_TXFS IOMUX_PAD(0x3bc, 0x1c4, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__GPIO4 IOMUX_PAD(0x3bc, 0x1c4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__SDMA_DBG_PC_7 IOMUX_PAD(0x3bc, 0x1c4, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_COL3__M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x3bc, 0x1c4, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW0__RXD_MUX IOMUX_PAD(0x3a0, 0x1a8, 1, 0x568, 1, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW0__ROW0 IOMUX_PAD(0x3a0, 0x1a8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW0__DTR IOMUX_PAD(0x3a0, 0x1a8, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW0__GPIO29 IOMUX_PAD(0x3a0, 0x1a8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW0__SDMA_DBG_PC_0 IOMUX_PAD(0x3a0, 0x1a8, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW1__ROW1 IOMUX_PAD(0x3a4, 0x1ac, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW1__TXD_MUX IOMUX_PAD(0x3a4, 0x1ac, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW1__DSR IOMUX_PAD(0x3a4, 0x1ac, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW1__GPIO30 IOMUX_PAD(0x3a4, 0x1ac, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW1__SDMA_DBG_PC_1 IOMUX_PAD(0x3a4, 0x1ac, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__ROW2 IOMUX_PAD(0x3a8, 0x1b0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__RTS IOMUX_PAD(0x3a8, 0x1b0, 1, 0x564, 1, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__AUD5_RXC IOMUX_PAD(0x3a8, 0x1b0, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__CSI_D0 IOMUX_PAD(0x3a8, 0x1b0, 3, 0x488, 2, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__DCD IOMUX_PAD(0x3a8, 0x1b0, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__GPIO31 IOMUX_PAD(0x3a8, 0x1b0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW2__SDMA_DBG_PC_2 IOMUX_PAD(0x3a8, 0x1b0, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__ROW3 IOMUX_PAD(0x3ac, 0x1b4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__CTS IOMUX_PAD(0x3ac, 0x1b4, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__AUD5_RXFS IOMUX_PAD(0x3ac, 0x1b4, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__CSI_D1 IOMUX_PAD(0x3ac, 0x1b4, 3, 0x48c, 2, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__RI IOMUX_PAD(0x3ac, 0x1b4, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__GPIO0 IOMUX_PAD(0x3ac, 0x1b4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_KPP_ROW3__SDMA_DBG_PC_3 IOMUX_PAD(0x3ac, 0x1b4, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LBA__EIM_LBA IOMUX_PAD(0x274, 0x64, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LBA__RXD_MUX IOMUX_PAD(0x274, 0x64, 3, 0x578, 0, NO_PAD_CTRL) +#define MX25_PAD_LBA__GPIO24 IOMUX_PAD(0x274, 0x64, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LBA__RDY IOMUX_PAD(0x274, 0x64, 6, 0x4b0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__LCDC_LD0 IOMUX_PAD(0x2c0, 0xc8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__SLCDC_DATA0 IOMUX_PAD(0x2c0, 0xc8, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__CSI_D0 IOMUX_PAD(0x2c0, 0xc8, 2, 0x488, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__DATA0 IOMUX_PAD(0x2c0, 0xc8, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__CLK1 IOMUX_PAD(0x2c0, 0xc8, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__GPIO15 IOMUX_PAD(0x2c0, 0xc8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD0__USBH2_CLK IOMUX_PAD(0x2c0, 0xc8, 6, 0, 0, 0xe0) +#define MX25_PAD_LD0__BT_MEM_CTRL0 IOMUX_PAD(0x2c0, 0xc8, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__LCDC_LD10 IOMUX_PAD(0x2e8, 0xf0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__SLCDC_DATA10 IOMUX_PAD(0x2e8, 0xf0, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__RTS IOMUX_PAD(0x2e8, 0xf0, 2, 0x56c, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__DATA10 IOMUX_PAD(0x2e8, 0xf0, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__AUD3_TXC IOMUX_PAD(0x2e8, 0xf0, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__DAT0 IOMUX_PAD(0x2e8, 0xf0, 6, 0x4e4, 0, NO_PAD_CTRL) +#define MX25_PAD_LD10__RX_ERR IOMUX_PAD(0x2e8, 0xf0, 5, 0x518, 1, NO_PAD_CTRL) +#define MX25_PAD_LD10__BT_MLC_SEL IOMUX_PAD(0x2e8, 0xf0, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__LCDC_LD11 IOMUX_PAD(0x2ec, 0xf4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__SLCDC_DATA11 IOMUX_PAD(0x2ec, 0xf4, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__CTS IOMUX_PAD(0x2ec, 0xf4, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__DATA11 IOMUX_PAD(0x2ec, 0xf4, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__AUD3_TXFS IOMUX_PAD(0x2ec, 0xf4, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__RDATA2 IOMUX_PAD(0x2ec, 0xf4, 5, 0x50c, 1, NO_PAD_CTRL) +#define MX25_PAD_LD11__DAT1 IOMUX_PAD(0x2ec, 0xf4, 6, 0x4e8, 0, NO_PAD_CTRL) +#define MX25_PAD_LD11__BT_SPARE_SIZE IOMUX_PAD(0x2ec, 0xf4, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__LCDC_LD12 IOMUX_PAD(0x2f0, 0xf8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__SLCDC_DATA12 IOMUX_PAD(0x2f0, 0xf8, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__MOSI IOMUX_PAD(0x2f0, 0xf8, 2, 0x4a0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__DATA12 IOMUX_PAD(0x2f0, 0xf8, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__ROW6 IOMUX_PAD(0x2f0, 0xf8, 4, 0x544, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__RDATA3 IOMUX_PAD(0x2f0, 0xf8, 5, 0x510, 1, NO_PAD_CTRL) +#define MX25_PAD_LD12__DAT2 IOMUX_PAD(0x2f0, 0xf8, 6, 0x4ec, 0, NO_PAD_CTRL) +#define MX25_PAD_LD12__BT_SRC0 IOMUX_PAD(0x2f0, 0xf8, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__LCDC_LD13 IOMUX_PAD(0x2f4, 0xfc, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__SLCDC_DATA13 IOMUX_PAD(0x2f4, 0xfc, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__MISO IOMUX_PAD(0x2f4, 0xfc, 2, 0x49c, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__DATA13 IOMUX_PAD(0x2f4, 0xfc, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__ROW7 IOMUX_PAD(0x2f4, 0xfc, 4, 0x548, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__TDATA2 IOMUX_PAD(0x2f4, 0xfc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__DAT3 IOMUX_PAD(0x2f4, 0xfc, 6, 0x4f0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD13__BT_SRC1 IOMUX_PAD(0x2f4, 0xfc, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__LCDC_LD14 IOMUX_PAD(0x2f8, 0x100, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__SLCDC_DATA14 IOMUX_PAD(0x2f8, 0x100, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__SCLK IOMUX_PAD(0x2f8, 0x100, 2, 0x494, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__DATA14 IOMUX_PAD(0x2f8, 0x100, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__COL6 IOMUX_PAD(0x2f8, 0x100, 4, 0x534, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__TDATA3 IOMUX_PAD(0x2f8, 0x100, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__AUD3_RXC IOMUX_PAD(0x2f8, 0x100, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD14__BT_EEPROM_CFG IOMUX_PAD(0x2f8, 0x100, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__LCDC_LD15 IOMUX_PAD(0x2fc, 0x104, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__SLCDC_DATA15 IOMUX_PAD(0x2fc, 0x104, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__RDY IOMUX_PAD(0x2fc, 0x104, 2, 0x498, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__DATA15 IOMUX_PAD(0x2fc, 0x104, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__COL7 IOMUX_PAD(0x2fc, 0x104, 4, 0x538, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__RX_CLK IOMUX_PAD(0x2fc, 0x104, 5, 0x514, 1, NO_PAD_CTRL) +#define MX25_PAD_LD15__AUD3_RXFS IOMUX_PAD(0x2fc, 0x104, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD15__BT_UART_SRC0 IOMUX_PAD(0x2fc, 0x104, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__LCDC_LD1 IOMUX_PAD(0x2c4, 0xcc, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__SLCDC_DATA1 IOMUX_PAD(0x2c4, 0xcc, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__CSI_D1 IOMUX_PAD(0x2c4, 0xcc, 2, 0x48c, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__DATA1 IOMUX_PAD(0x2c4, 0xcc, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__RST1 IOMUX_PAD(0x2c4, 0xcc, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__GPIO16 IOMUX_PAD(0x2c4, 0xcc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD1__USBH2_DIR IOMUX_PAD(0x2c4, 0xcc, 6, 0, 0, 0xe0) +#define MX25_PAD_LD1__BT_MEM_CTRL1 IOMUX_PAD(0x2c4, 0xcc, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__LCDC_LD2 IOMUX_PAD(0x2c8, 0xd0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__SLCDC_DATA2 IOMUX_PAD(0x2c8, 0xd0, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__CSI_D15 IOMUX_PAD(0x2c8, 0xd0, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__DATA2 IOMUX_PAD(0x2c8, 0xd0, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__VEN1 IOMUX_PAD(0x2c8, 0xd0, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__GPIO17 IOMUX_PAD(0x2c8, 0xd0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD2__USBH2_STP IOMUX_PAD(0x2c8, 0xd0, 6, 0, 0, 0xe5) +#define MX25_PAD_LD2__BT_MEM_TYPE0 IOMUX_PAD(0x2c8, 0xd0, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD3__LCDC_LD3 IOMUX_PAD(0x2cc, 0xd4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD3__SLCDC_DATA3 IOMUX_PAD(0x2cc, 0xd4, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD3__CSI_D14 IOMUX_PAD(0x2cc, 0xd4, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD3__DATA3 IOMUX_PAD(0x2cc, 0xd4, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD3__TX1 IOMUX_PAD(0x2cc, 0xd4, 4, 0x554, 1, NO_PAD_CTRL) +#define MX25_PAD_LD3__GPIO18 IOMUX_PAD(0x2cc, 0xd4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD3__USBH2_NXT IOMUX_PAD(0x2cc, 0xd4, 6, 0, 0, 0xe0) +#define MX25_PAD_LD3__BT_MEM_TYPE1 IOMUX_PAD(0x2cc, 0xd4, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD4__LCDC_LD4 IOMUX_PAD(0x2d0, 0xd8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD4__SLCDC_DATA4 IOMUX_PAD(0x2d0, 0xd8, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD4__CSI_D13 IOMUX_PAD(0x2d0, 0xd8, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD4__DATA4 IOMUX_PAD(0x2d0, 0xd8, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD4__PD1 IOMUX_PAD(0x2d0, 0xd8, 4, 0x550, 1, NO_PAD_CTRL) +#define MX25_PAD_LD4__GPIO19 IOMUX_PAD(0x2d0, 0xd8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD4__USBH2_DATA0 IOMUX_PAD(0x2d0, 0xd8, 6, 0, 0, 0xe5) +#define MX25_PAD_LD4__BT_PAGE_SIZE0 IOMUX_PAD(0x2d0, 0xd8, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD5__LCDC_LD5 IOMUX_PAD(0x2d4, 0xdc, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD5__SLCDC_DATA5 IOMUX_PAD(0x2d4, 0xdc, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD5__CSI_D12 IOMUX_PAD(0x2d4, 0xdc, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD5__DATA5 IOMUX_PAD(0x2d4, 0xdc, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD5__RX1 IOMUX_PAD(0x2d4, 0xdc, 4, 0x54c, 1, NO_PAD_CTRL) +#define MX25_PAD_LD5__GPIO19 IOMUX_PAD(0x2d4, 0xdc, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD5__USBH2_DATA1 IOMUX_PAD(0x2d4, 0xdc, 6, 0, 0, 0xe5) +#define MX25_PAD_LD5__BT_PAGE_SIZE1 IOMUX_PAD(0x2d4, 0xdc, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__LCDC_LD6 IOMUX_PAD(0x2d8, 0xe0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__SLCDC_DATA6 IOMUX_PAD(0x2d8, 0xe0, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__CSI_D11 IOMUX_PAD(0x2d8, 0xe0, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__DATA6 IOMUX_PAD(0x2d8, 0xe0, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__CLK1 IOMUX_PAD(0x2d8, 0xe0, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__GPIO20 IOMUX_PAD(0x2d8, 0xe0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD6__USBH2_DATA2 IOMUX_PAD(0x2d8, 0xe0, 6, 0, 0, 0xe5) +#define MX25_PAD_LD6__BT_BUS_WIDTH0 IOMUX_PAD(0x2d8, 0xe0, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__LCDC_LD7 IOMUX_PAD(0x2dc, 0xe4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__SLCDC_DATA7 IOMUX_PAD(0x2dc, 0xe4, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__CSI_D10 IOMUX_PAD(0x2dc, 0xe4, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__DATA7 IOMUX_PAD(0x2dc, 0xe4, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__RST1 IOMUX_PAD(0x2dc, 0xe4, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__GPIO21 IOMUX_PAD(0x2dc, 0xe4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD7__USBH2_DATA3 IOMUX_PAD(0x2dc, 0xe4, 6, 0, 0, 0xe5) +#define MX25_PAD_LD7__BT_BUS_WIDTH1 IOMUX_PAD(0x2dc, 0xe4, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__LCDC_LD8 IOMUX_PAD(0x2e0, 0xe8, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__SLCDC_DATA8 IOMUX_PAD(0x2e0, 0xe8, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__RXD_MUX IOMUX_PAD(0x2e0, 0xe8, 2, 0x570, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__DATA8 IOMUX_PAD(0x2e0, 0xe8, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__AUD3_TXD IOMUX_PAD(0x2e0, 0xe8, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__TX_ERR IOMUX_PAD(0x2e0, 0xe8, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__CMD IOMUX_PAD(0x2e0, 0xe8, 6, 0x4e0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD8__BT_USB_SRC0 IOMUX_PAD(0x2e0, 0xe8, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__LCDC_LD9 IOMUX_PAD(0x2e4, 0xec, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__SLCDC_DATA9 IOMUX_PAD(0x2e4, 0xec, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__TXD_MUX IOMUX_PAD(0x2e4, 0xec, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__DATA9 IOMUX_PAD(0x2e4, 0xec, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__AUD3_RXD IOMUX_PAD(0x2e4, 0xec, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__COL IOMUX_PAD(0x2e4, 0xec, 5, 0x504, 1, NO_PAD_CTRL) +#define MX25_PAD_LD9__CLK IOMUX_PAD(0x2e4, 0xec, 6, 0x4dc, 0, NO_PAD_CTRL) +#define MX25_PAD_LD9__BT_USB_SRC1 IOMUX_PAD(0x2e4, 0xec, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LSCLK__LCDC_LSCLK IOMUX_PAD(0x308, 0x110, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LSCLK__SLCDC_CS IOMUX_PAD(0x308, 0x110, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LSCLK__DA_0 IOMUX_PAD(0x308, 0x110, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LSCLK__PD1 IOMUX_PAD(0x308, 0x110, 4, 0x55c, 1, NO_PAD_CTRL) +#define MX25_PAD_LSCLK__GPIO24 IOMUX_PAD(0x308, 0x110, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_LSCLK__USBH2_DATA6 IOMUX_PAD(0x308, 0x110, 6, 0, 0, 0xe5) +#define MX25_PAD_LSCLK__BT_LPB_FREQ0 IOMUX_PAD(0x308, 0x110, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFALE__NANDF_ALE IOMUX_PAD(0x000, 0x78, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFALE__GPIO28 IOMUX_PAD(0x000, 0x78, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFALE__PIPESTAT0 IOMUX_PAD(0x000, 0x78, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NF_CE0__NANDF_CE0 IOMUX_PAD(0x26c, 0x5c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NF_CE0__SS3 IOMUX_PAD(0x26c, 0x5c, 1, 0x490, 0, NO_PAD_CTRL) +#define MX25_PAD_NF_CE0__GPIO22 IOMUX_PAD(0x26c, 0x5c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NF_CE0__TRACE3 IOMUX_PAD(0x26c, 0x5c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFCLE__NANDF_CLE IOMUX_PAD(0x000, 0x7c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFCLE__GPIO29 IOMUX_PAD(0x000, 0x7c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFCLE__TRACE0 IOMUX_PAD(0x000, 0x7c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFRB__NANDF_RB IOMUX_PAD(0x27c, 0x84, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFRB__GPIO31 IOMUX_PAD(0x27c, 0x84, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFRB__TRACE2 IOMUX_PAD(0x27c, 0x84, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFRE_B__NANDF_RE_B IOMUX_PAD(0x000, 0x74, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFRE_B__GPIO27 IOMUX_PAD(0x000, 0x74, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFRE_B__PIPESTAT1 IOMUX_PAD(0x000, 0x74, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWE_B__NANDF_WE_B IOMUX_PAD(0x000, 0x70, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWE_B__GPIO26 IOMUX_PAD(0x000, 0x70, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWE_B__PIPESTAT2 IOMUX_PAD(0x000, 0x70, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWP_B__NANDF_WP_B IOMUX_PAD(0x000, 0x80, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWP_B__GPIO30 IOMUX_PAD(0x000, 0x80, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_NFWP_B__TRACE1 IOMUX_PAD(0x000, 0x80, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__LCDC_OE_ACD IOMUX_PAD(0x30c, 0x114, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__SLCDC_RS IOMUX_PAD(0x30c, 0x114, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__SS0 IOMUX_PAD(0x30c, 0x114, 2, 0x4a4, 0, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__DA_1 IOMUX_PAD(0x30c, 0x114, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__RX1 IOMUX_PAD(0x30c, 0x114, 4, 0x558, 1, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__GPIO25 IOMUX_PAD(0x30c, 0x114, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE_ACD__USBH2_DATA7 IOMUX_PAD(0x30c, 0x114, 6, 0, 0, 0xe5) +#define MX25_PAD_OE_ACD__BT_LPB_FREQ1 IOMUX_PAD(0x30c, 0x114, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE__EIM_OE IOMUX_PAD(0x260, 0x48, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE__AUD4_TXC IOMUX_PAD(0x260, 0x48, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_OE__GPIO14 IOMUX_PAD(0x260, 0x48, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_POWER_FAIL__POWER_FAIL_INT IOMUX_PAD(0x410, 0x21c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_POWER_FAIL__AUD7_RXD IOMUX_PAD(0x410, 0x21c, 4, 0x478, 1, NO_PAD_CTRL) +#define MX25_PAD_POWER_FAIL__GPIO19 IOMUX_PAD(0x410, 0x21c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_POWER_FAIL__CTS IOMUX_PAD(0x410, 0x21c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_PWM__PWMO IOMUX_PAD(0x314, 0x11c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_PWM__CMPOUT1 IOMUX_PAD(0x314, 0x11c, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_PWM__GPIO26 IOMUX_PAD(0x314, 0x11c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_PWM__USBH2_OC IOMUX_PAD(0x314, 0x11c, 6, 0x580, 1, NO_PAD_CTRL) +#define MX25_PAD_PWM__BT_LPB_FREQ2 IOMUX_PAD(0x314, 0x11c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RTCK__RTCK IOMUX_PAD(0x3e4, 0x1ec, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RTCK__LINE IOMUX_PAD(0x3e4, 0x1ec, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RTCK__DAT7 IOMUX_PAD(0x3e4, 0x1ec, 2, 0x500, 1, NO_PAD_CTRL) +#define MX25_PAD_RTCK__GPIO14 IOMUX_PAD(0x3e4, 0x1ec, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RTCK__SDMA_DBG_PC_13 IOMUX_PAD(0x3e4, 0x1ec, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RW__EIM_RW IOMUX_PAD(0x278, 0x6c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x6c, 4, 0x474, 0, NO_PAD_CTRL) +#define MX25_PAD_RW__GPIO25 IOMUX_PAD(0x278, 0x6c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CLK__CLK IOMUX_PAD(0x38c, 0x194, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CLK__MISO IOMUX_PAD(0x38c, 0x194, 1, 0x49c, 1, NO_PAD_CTRL) +#define MX25_PAD_SD1_CLK__RDATA3 IOMUX_PAD(0x38c, 0x194, 2, 0x510, 2, NO_PAD_CTRL) +#define MX25_PAD_SD1_CLK__SDMA_DBG_STAT_0 IOMUX_PAD(0x38c, 0x194, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CLK__GPIO24 IOMUX_PAD(0x38c, 0x194, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CLK__SLCDC_DATA1 IOMUX_PAD(0x38c, 0x194, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CLK__TRACE11 IOMUX_PAD(0x38c, 0x194, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CMD__CMD IOMUX_PAD(0x388, 0x190, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CMD__MOSI IOMUX_PAD(0x388, 0x190, 1, 0x4a0, 1, NO_PAD_CTRL) +#define MX25_PAD_SD1_CMD__RDATA2 IOMUX_PAD(0x388, 0x190, 2, 0x50c, 2, NO_PAD_CTRL) +#define MX25_PAD_SD1_CMD__SDMA_DBG_EVT_SEL IOMUX_PAD(0x388, 0x190, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CMD__GPIO23 IOMUX_PAD(0x388, 0x190, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CMD__SLCDC_DATA0 IOMUX_PAD(0x388, 0x190, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_CMD__TRACE10 IOMUX_PAD(0x388, 0x190, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA0__DAT0 IOMUX_PAD(0x390, 0x198, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA0__SCLK IOMUX_PAD(0x390, 0x198, 1, 0x494, 1, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA0__TDATA2 IOMUX_PAD(0x390, 0x198, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA0__AUD7_TXFS IOMUX_PAD(0x390, 0x198, 3, 0x47c, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA0__SDMA_DBG_STAT_1 IOMUX_PAD(0x390, 0x198, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA0__GPIO25 IOMUX_PAD(0x390, 0x198, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA0__SLCDC_DATA2 IOMUX_PAD(0x390, 0x198, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA0__TRACE12 IOMUX_PAD(0x390, 0x198, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__DAT1 IOMUX_PAD(0x394, 0x19c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__RDY IOMUX_PAD(0x394, 0x19c, 1, 0x498, 1, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__TDATA3 IOMUX_PAD(0x394, 0x19c, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 3, 0x478, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__SDMA_DBG_STAT_2 IOMUX_PAD(0x394, 0x19c, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__GPIO26 IOMUX_PAD(0x394, 0x19c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__SLCDC_DATA3 IOMUX_PAD(0x394, 0x19c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA1__TRACE13 IOMUX_PAD(0x394, 0x19c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__DAT2 IOMUX_PAD(0x398, 0x1a0, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__SS0 IOMUX_PAD(0x398, 0x1a0, 1, 0x4a4, 1, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__RX_CLK IOMUX_PAD(0x398, 0x1a0, 2, 0x514, 2, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__AUD7_RXC IOMUX_PAD(0x398, 0x1a0, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__SDMA_DBG_STAT_3 IOMUX_PAD(0x398, 0x1a0, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__GPIO27 IOMUX_PAD(0x398, 0x1a0, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__SLCDC_DATA4 IOMUX_PAD(0x398, 0x1a0, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA2__TRACE14 IOMUX_PAD(0x398, 0x1a0, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA3__DAT3 IOMUX_PAD(0x39c, 0x1a4, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA3__SS1 IOMUX_PAD(0x39c, 0x1a4, 1, 0x4a8, 1, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA3__CRS IOMUX_PAD(0x39c, 0x1a4, 2, 0x508, 2, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA3__AUD7_RXFS IOMUX_PAD(0x39c, 0x1a4, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA3__GPIO28 IOMUX_PAD(0x39c, 0x1a4, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA3__SLCDC_DATA5 IOMUX_PAD(0x39c, 0x1a4, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_SD1_DATA3__TRACE15 IOMUX_PAD(0x39c, 0x1a4, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_CTS__CTS IOMUX_PAD(0x374, 0x17c, 0, 0, 0, 0x40) +#define MX25_PAD_UART1_CTS__CSI_D1 IOMUX_PAD(0x374, 0x17c, 1, 0x48c, 1, NO_PAD_CTRL) +#define MX25_PAD_UART1_CTS__CMPOUT1 IOMUX_PAD(0x374, 0x17c, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_CTS__RI IOMUX_PAD(0x374, 0x17c, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_CTS__LCDC_REV IOMUX_PAD(0x374, 0x17c, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_CTS__GPIO25 IOMUX_PAD(0x374, 0x17c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_CTS__SLCDC_DATA11 IOMUX_PAD(0x374, 0x17c, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RTS__RTS IOMUX_PAD(0x370, 0x178, 0, 0, 0, 0x1E0) +#define MX25_PAD_UART1_RTS__CSI_D0 IOMUX_PAD(0x370, 0x178, 1, 0x488, 1, NO_PAD_CTRL) +#define MX25_PAD_UART1_RTS__CAPIN1 IOMUX_PAD(0x370, 0x178, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RTS__DCD IOMUX_PAD(0x370, 0x178, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RTS__LCDC_PS IOMUX_PAD(0x370, 0x178, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RTS__GPIO24 IOMUX_PAD(0x370, 0x178, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RTS__SLCDC_DATA10 IOMUX_PAD(0x370, 0x178, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RXD__RXD_MUX IOMUX_PAD(0x368, 0x170, 0, 0, 0, 0x1e0) +#define MX25_PAD_UART1_RXD__DTR IOMUX_PAD(0x368, 0x170, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RXD__LCDC_CLS IOMUX_PAD(0x368, 0x170, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RXD__GPIO22 IOMUX_PAD(0x368, 0x170, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_RXD__SLCDC_DATA8 IOMUX_PAD(0x368, 0x170, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_TXD__TXD_MUX IOMUX_PAD(0x36c, 0x174, 0, 0, 0, 0x40) +#define MX25_PAD_UART1_TXD__DSR IOMUX_PAD(0x36c, 0x174, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_TXD__LCDC_SPL IOMUX_PAD(0x36c, 0x174, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_TXD__GPIO23 IOMUX_PAD(0x36c, 0x174, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART1_TXD__SLCDC_DATA9 IOMUX_PAD(0x36c, 0x174, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__CTS IOMUX_PAD(0x384, 0x18c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__DAT4 IOMUX_PAD(0x384, 0x18c, 1, 0x4cc, 1, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__RX_ERR IOMUX_PAD(0x384, 0x18c, 2, 0x518, 2, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__CMPOUT1 IOMUX_PAD(0x384, 0x18c, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__GPIO29 IOMUX_PAD(0x384, 0x18c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__SS3 IOMUX_PAD(0x384, 0x18c, 6, 0x4c8, 1, NO_PAD_CTRL) +#define MX25_PAD_UART2_CTS__EXTDMA_2 IOMUX_PAD(0x384, 0x18c, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__RTS IOMUX_PAD(0x380, 0x188, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__DAT5 IOMUX_PAD(0x380, 0x188, 1, 0x4d0, 1, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__COL IOMUX_PAD(0x380, 0x188, 2, 0x504, 2, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__CAPIN1 IOMUX_PAD(0x380, 0x188, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__EPITO IOMUX_PAD(0x380, 0x188, 4, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__GPIO28 IOMUX_PAD(0x380, 0x188, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__SS3 IOMUX_PAD(0x380, 0x188, 6, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RTS__EXTDMA_1 IOMUX_PAD(0x380, 0x188, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RXD__RXD_MUX IOMUX_PAD(0x378, 0x180, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_RXD__DAT7 IOMUX_PAD(0x378, 0x180, 1, 0x4d8, 1, NO_PAD_CTRL) +#define MX25_PAD_UART2_RXD__GPIO26 IOMUX_PAD(0x378, 0x180, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_TXD__TXD_MUX IOMUX_PAD(0x37c, 0x184, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_TXD__DAT6 IOMUX_PAD(0x37c, 0x184, 1, 0x4d4, 1, NO_PAD_CTRL) +#define MX25_PAD_UART2_TXD__TX_ERR IOMUX_PAD(0x37c, 0x184, 2, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_TXD__GPIO27 IOMUX_PAD(0x37c, 0x184, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UART2_TXD__EXTDMA_0 IOMUX_PAD(0x37c, 0x184, 7, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_UPLL_BYPCLK__GPIO16 IOMUX_PAD(0x000, 0x210, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__hreset_b IOMUX_PAD(0x40c, 0x218, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__VSTBY_ACK IOMUX_PAD(0x40c, 0x218, 1, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__SS3 IOMUX_PAD(0x40c, 0x218, 2, 0x490, 1, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__EPITO IOMUX_PAD(0x40c, 0x218, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_ACK__GPIO18 IOMUX_PAD(0x40c, 0x218, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_REQ__VSTBY_REQ IOMUX_PAD(0x408, 0x214, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_REQ__AUD7_TXFS IOMUX_PAD(0x408, 0x214, 4, 0x47c, 1, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_REQ__GPIO17 IOMUX_PAD(0x408, 0x214, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSTBY_REQ__RTS IOMUX_PAD(0x408, 0x214, 6, 0x56c, 2, NO_PAD_CTRL) +#define MX25_PAD_VSYNC__LCDC_VSYN IOMUX_PAD(0x304, 0x10c, 0, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSYNC__SDA IOMUX_PAD(0x304, 0x10c, 2, 0x528, 0, NO_PAD_CTRL) +#define MX25_PAD_VSYNC__DMARQ IOMUX_PAD(0x304, 0x10c, 3, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSYNC__TX1 IOMUX_PAD(0x304, 0x10c, 4, 0x560, 1, NO_PAD_CTRL) +#define MX25_PAD_VSYNC__GPIO23 IOMUX_PAD(0x304, 0x10c, 5, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_VSYNC__USBH2_DATA5 IOMUX_PAD(0x304, 0x10c, 6, 0, 0, 0xe5) +#define MX25_PAD_VSYNC__BT_UART_SRC2 IOMUX_PAD(0x304, 0x10c, 7, 0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX25_H__ */ + diff --git a/arch/arm/mach-imx/include/mach/iomux-mx31.h b/arch/arm/mach-imx/include/mach/iomux-mx31.h new file mode 100644 index 0000000000..16c8e51e8c --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx31.h @@ -0,0 +1,553 @@ +/* + * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_MX31_IOMUX_H__ +#define __MACH_MX31_IOMUX_H__ + +#include <linux/types.h> + +/* + * various IOMUX output functions + */ + +#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */ +#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */ +#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */ +#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */ +#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */ +#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ +#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ +#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ +#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ +#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ +#define IOMUX_ICONFIG_FUNC 2 /* used as function */ +#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ +#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */ + +#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO) +#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC) +#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1) +#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2) + +/* + * various IOMUX pad functions + */ +enum iomux_pad_config { + PAD_CTL_NOLOOPBACK = 0x0 << 9, + PAD_CTL_LOOPBACK = 0x1 << 9, + PAD_CTL_PKE_NONE = 0x0 << 8, + PAD_CTL_PKE_ENABLE = 0x1 << 8, + PAD_CTL_PUE_KEEPER = 0x0 << 7, + PAD_CTL_PUE_PUD = 0x1 << 7, + PAD_CTL_100K_PD = 0x0 << 5, + PAD_CTL_100K_PU = 0x1 << 5, + PAD_CTL_47K_PU = 0x2 << 5, + PAD_CTL_22K_PU = 0x3 << 5, + PAD_CTL_HYS_CMOS = 0x0 << 4, + PAD_CTL_HYS_SCHMITZ = 0x1 << 4, + PAD_CTL_ODE_CMOS = 0x0 << 3, + PAD_CTL_ODE_OpenDrain = 0x1 << 3, + PAD_CTL_DRV_NORMAL = 0x0 << 1, + PAD_CTL_DRV_HIGH = 0x1 << 1, + PAD_CTL_DRV_MAX = 0x2 << 1, + PAD_CTL_SRE_SLOW = 0x0 << 0, + PAD_CTL_SRE_FAST = 0x1 << 0 +}; + +/* + * various IOMUX general purpose functions + */ +enum iomux_gp_func { + MUX_PGP_FIRI = 1 << 0, + MUX_DDR_MODE = 1 << 1, + MUX_PGP_CSPI_BB = 1 << 2, + MUX_PGP_ATA_1 = 1 << 3, + MUX_PGP_ATA_2 = 1 << 4, + MUX_PGP_ATA_3 = 1 << 5, + MUX_PGP_ATA_4 = 1 << 6, + MUX_PGP_ATA_5 = 1 << 7, + MUX_PGP_ATA_6 = 1 << 8, + MUX_PGP_ATA_7 = 1 << 9, + MUX_PGP_ATA_8 = 1 << 10, + MUX_PGP_UH2 = 1 << 11, + MUX_SDCTL_CSD0_SEL = 1 << 12, + MUX_SDCTL_CSD1_SEL = 1 << 13, + MUX_CSPI1_UART3 = 1 << 14, + MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, + MUX_TAMPER_DETECT_EN = 1 << 16, + MUX_PGP_USB_4WIRE = 1 << 17, + MUX_PGB_USB_COMMON = 1 << 18, + MUX_SDHC_MEMSTICK1 = 1 << 19, + MUX_SDHC_MEMSTICK2 = 1 << 20, + MUX_PGP_SPLL_BYP = 1 << 21, + MUX_PGP_UPLL_BYP = 1 << 22, + MUX_PGP_MSHC1_CLK_SEL = 1 << 23, + MUX_PGP_MSHC2_CLK_SEL = 1 << 24, + MUX_CSPI3_UART5_SEL = 1 << 25, + MUX_PGP_ATA_9 = 1 << 26, + MUX_PGP_USB_SUSPEND = 1 << 27, + MUX_PGP_USB_OTG_LOOPBACK = 1 << 28, + MUX_PGP_USB_HS1_LOOPBACK = 1 << 29, + MUX_PGP_USB_HS2_LOOPBACK = 1 << 30, + MUX_CLKO_DDR_MODE = 1 << 31, +}; + +/* + * This function enables/disables the general purpose function for a particular + * signal. + */ +void iomux_config_gpr(enum iomux_gp_func , int); + +/* + * set the mode for a IOMUX pin. + */ +int mxc_iomux_mode(unsigned int); + +/* + * This function enables/disables the general purpose function for a particular + * signal. + */ +void mxc_iomux_set_gpr(enum iomux_gp_func, int); + +#define IOMUX_PADNUM_MASK 0x1ff +#define IOMUX_GPIONUM_SHIFT 9 +#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT) +#define IOMUX_MODE_SHIFT 17 +#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT) + +#define IOMUX_PIN(gpionum, padnum) \ + (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \ + (padnum & IOMUX_PADNUM_MASK)) + +#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT) + +#define IOMUX_TO_GPIO(iomux_pin) \ + ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) +#define IOMUX_TO_IRQ(iomux_pin) \ + (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \ + MXC_GPIO_INT_BASE) + +/* + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ + +enum iomux_pins { + MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0), + MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1), + MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2), + MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3), + MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4), + MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5), + MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6), + MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7), + MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8), + MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9), + MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10), + MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11), + MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12), + MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13), + MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14), + MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15), + MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16), + MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17), + MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18), + MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19), + MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20), + MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21), + MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22), + MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23), + MX31_PIN_READ = IOMUX_PIN(0xff, 24), + MX31_PIN_WRITE = IOMUX_PIN(0xff, 25), + MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26), + MX31_PIN_SER_RS = IOMUX_PIN(89, 27), + MX31_PIN_LCS1 = IOMUX_PIN(88, 28), + MX31_PIN_LCS0 = IOMUX_PIN(87, 29), + MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30), + MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31), + MX31_PIN_SD_D_I = IOMUX_PIN(84, 32), + MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33), + MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34), + MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35), + MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36), + MX31_PIN_LD17 = IOMUX_PIN(0xff, 37), + MX31_PIN_LD16 = IOMUX_PIN(0xff, 38), + MX31_PIN_LD15 = IOMUX_PIN(0xff, 39), + MX31_PIN_LD14 = IOMUX_PIN(0xff, 40), + MX31_PIN_LD13 = IOMUX_PIN(0xff, 41), + MX31_PIN_LD12 = IOMUX_PIN(0xff, 42), + MX31_PIN_LD11 = IOMUX_PIN(0xff, 43), + MX31_PIN_LD10 = IOMUX_PIN(0xff, 44), + MX31_PIN_LD9 = IOMUX_PIN(0xff, 45), + MX31_PIN_LD8 = IOMUX_PIN(0xff, 46), + MX31_PIN_LD7 = IOMUX_PIN(0xff, 47), + MX31_PIN_LD6 = IOMUX_PIN(0xff, 48), + MX31_PIN_LD5 = IOMUX_PIN(0xff, 49), + MX31_PIN_LD4 = IOMUX_PIN(0xff, 50), + MX31_PIN_LD3 = IOMUX_PIN(0xff, 51), + MX31_PIN_LD2 = IOMUX_PIN(0xff, 52), + MX31_PIN_LD1 = IOMUX_PIN(0xff, 53), + MX31_PIN_LD0 = IOMUX_PIN(0xff, 54), + MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55), + MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56), + MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57), + MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58), + MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59), + MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60), + MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61), + MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62), + MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63), + MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64), + MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65), + MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66), + MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67), + MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68), + MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69), + MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70), + MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71), + MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72), + MX31_PIN_USB_BYP = IOMUX_PIN(31, 73), + MX31_PIN_USB_OC = IOMUX_PIN(30, 74), + MX31_PIN_USB_PWR = IOMUX_PIN(29, 75), + MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76), + MX31_PIN_DE_B = IOMUX_PIN(0xff, 77), + MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78), + MX31_PIN_TDO = IOMUX_PIN(0xff, 79), + MX31_PIN_TDI = IOMUX_PIN(0xff, 80), + MX31_PIN_TMS = IOMUX_PIN(0xff, 81), + MX31_PIN_TCK = IOMUX_PIN(0xff, 82), + MX31_PIN_RTCK = IOMUX_PIN(0xff, 83), + MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84), + MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85), + MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86), + MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87), + MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88), + MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89), + MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90), + MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91), + MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92), + MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93), + MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94), + MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95), + MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96), + MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97), + MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98), + MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99), + MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100), + MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101), + MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102), + MX31_PIN_TXD2 = IOMUX_PIN(28, 103), + MX31_PIN_RXD2 = IOMUX_PIN(27, 104), + MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105), + MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106), + MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107), + MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108), + MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109), + MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110), + MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111), + MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112), + MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113), + MX31_PIN_CTS1 = IOMUX_PIN(39, 114), + MX31_PIN_RTS1 = IOMUX_PIN(38, 115), + MX31_PIN_TXD1 = IOMUX_PIN(37, 116), + MX31_PIN_RXD1 = IOMUX_PIN(36, 117), + MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118), + MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119), + MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120), + MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121), + MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122), + MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123), + MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124), + MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125), + MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126), + MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127), + MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128), + MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129), + MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130), + MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131), + MX31_PIN_SFS6 = IOMUX_PIN(26, 132), + MX31_PIN_SCK6 = IOMUX_PIN(25, 133), + MX31_PIN_SRXD6 = IOMUX_PIN(24, 134), + MX31_PIN_STXD6 = IOMUX_PIN(23, 135), + MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136), + MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137), + MX31_PIN_SRXD5 = IOMUX_PIN(22, 138), + MX31_PIN_STXD5 = IOMUX_PIN(21, 139), + MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140), + MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141), + MX31_PIN_SRXD4 = IOMUX_PIN(20, 142), + MX31_PIN_STXD4 = IOMUX_PIN(19, 143), + MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144), + MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145), + MX31_PIN_SRXD3 = IOMUX_PIN(18, 146), + MX31_PIN_STXD3 = IOMUX_PIN(17, 147), + MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148), + MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149), + MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150), + MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151), + MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152), + MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153), + MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154), + MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155), + MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156), + MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157), + MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158), + MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159), + MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160), + MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161), + MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162), + MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163), + MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164), + MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165), + MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166), + MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167), + MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168), + MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169), + MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170), + MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171), + MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172), + MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173), + MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174), + MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175), + MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176), + MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177), + MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178), + MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179), + MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180), + MX31_PIN_D0 = IOMUX_PIN(0xff, 181), + MX31_PIN_D1 = IOMUX_PIN(0xff, 182), + MX31_PIN_D2 = IOMUX_PIN(0xff, 183), + MX31_PIN_D3 = IOMUX_PIN(0xff, 184), + MX31_PIN_D4 = IOMUX_PIN(0xff, 185), + MX31_PIN_D5 = IOMUX_PIN(0xff, 186), + MX31_PIN_D6 = IOMUX_PIN(0xff, 187), + MX31_PIN_D7 = IOMUX_PIN(0xff, 188), + MX31_PIN_D8 = IOMUX_PIN(0xff, 189), + MX31_PIN_D9 = IOMUX_PIN(0xff, 190), + MX31_PIN_D10 = IOMUX_PIN(0xff, 191), + MX31_PIN_D11 = IOMUX_PIN(0xff, 192), + MX31_PIN_D12 = IOMUX_PIN(0xff, 193), + MX31_PIN_D13 = IOMUX_PIN(0xff, 194), + MX31_PIN_D14 = IOMUX_PIN(0xff, 195), + MX31_PIN_D15 = IOMUX_PIN(0xff, 196), + MX31_PIN_NFRB = IOMUX_PIN(16, 197), + MX31_PIN_NFCE_B = IOMUX_PIN(15, 198), + MX31_PIN_NFWP_B = IOMUX_PIN(14, 199), + MX31_PIN_NFCLE = IOMUX_PIN(13, 200), + MX31_PIN_NFALE = IOMUX_PIN(12, 201), + MX31_PIN_NFRE_B = IOMUX_PIN(11, 202), + MX31_PIN_NFWE_B = IOMUX_PIN(10, 203), + MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204), + MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205), + MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206), + MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207), + MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208), + MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209), + MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210), + MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211), + MX31_PIN_SDWE = IOMUX_PIN(0xff, 212), + MX31_PIN_CAS = IOMUX_PIN(0xff, 213), + MX31_PIN_RAS = IOMUX_PIN(0xff, 214), + MX31_PIN_RW = IOMUX_PIN(0xff, 215), + MX31_PIN_BCLK = IOMUX_PIN(0xff, 216), + MX31_PIN_LBA = IOMUX_PIN(0xff, 217), + MX31_PIN_ECB = IOMUX_PIN(0xff, 218), + MX31_PIN_CS5 = IOMUX_PIN(0xff, 219), + MX31_PIN_CS4 = IOMUX_PIN(0xff, 220), + MX31_PIN_CS3 = IOMUX_PIN(0xff, 221), + MX31_PIN_CS2 = IOMUX_PIN(0xff, 222), + MX31_PIN_CS1 = IOMUX_PIN(0xff, 223), + MX31_PIN_CS0 = IOMUX_PIN(0xff, 224), + MX31_PIN_OE = IOMUX_PIN(0xff, 225), + MX31_PIN_EB1 = IOMUX_PIN(0xff, 226), + MX31_PIN_EB0 = IOMUX_PIN(0xff, 227), + MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228), + MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229), + MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230), + MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231), + MX31_PIN_SD31 = IOMUX_PIN(0xff, 232), + MX31_PIN_SD30 = IOMUX_PIN(0xff, 233), + MX31_PIN_SD29 = IOMUX_PIN(0xff, 234), + MX31_PIN_SD28 = IOMUX_PIN(0xff, 235), + MX31_PIN_SD27 = IOMUX_PIN(0xff, 236), + MX31_PIN_SD26 = IOMUX_PIN(0xff, 237), + MX31_PIN_SD25 = IOMUX_PIN(0xff, 238), + MX31_PIN_SD24 = IOMUX_PIN(0xff, 239), + MX31_PIN_SD23 = IOMUX_PIN(0xff, 240), + MX31_PIN_SD22 = IOMUX_PIN(0xff, 241), + MX31_PIN_SD21 = IOMUX_PIN(0xff, 242), + MX31_PIN_SD20 = IOMUX_PIN(0xff, 243), + MX31_PIN_SD19 = IOMUX_PIN(0xff, 244), + MX31_PIN_SD18 = IOMUX_PIN(0xff, 245), + MX31_PIN_SD17 = IOMUX_PIN(0xff, 246), + MX31_PIN_SD16 = IOMUX_PIN(0xff, 247), + MX31_PIN_SD15 = IOMUX_PIN(0xff, 248), + MX31_PIN_SD14 = IOMUX_PIN(0xff, 249), + MX31_PIN_SD13 = IOMUX_PIN(0xff, 250), + MX31_PIN_SD12 = IOMUX_PIN(0xff, 251), + MX31_PIN_SD11 = IOMUX_PIN(0xff, 252), + MX31_PIN_SD10 = IOMUX_PIN(0xff, 253), + MX31_PIN_SD9 = IOMUX_PIN(0xff, 254), + MX31_PIN_SD8 = IOMUX_PIN(0xff, 255), + MX31_PIN_SD7 = IOMUX_PIN(0xff, 256), + MX31_PIN_SD6 = IOMUX_PIN(0xff, 257), + MX31_PIN_SD5 = IOMUX_PIN(0xff, 258), + MX31_PIN_SD4 = IOMUX_PIN(0xff, 259), + MX31_PIN_SD3 = IOMUX_PIN(0xff, 260), + MX31_PIN_SD2 = IOMUX_PIN(0xff, 261), + MX31_PIN_SD1 = IOMUX_PIN(0xff, 262), + MX31_PIN_SD0 = IOMUX_PIN(0xff, 263), + MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264), + MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265), + MX31_PIN_A25 = IOMUX_PIN(0xff, 266), + MX31_PIN_A24 = IOMUX_PIN(0xff, 267), + MX31_PIN_A23 = IOMUX_PIN(0xff, 268), + MX31_PIN_A22 = IOMUX_PIN(0xff, 269), + MX31_PIN_A21 = IOMUX_PIN(0xff, 270), + MX31_PIN_A20 = IOMUX_PIN(0xff, 271), + MX31_PIN_A19 = IOMUX_PIN(0xff, 272), + MX31_PIN_A18 = IOMUX_PIN(0xff, 273), + MX31_PIN_A17 = IOMUX_PIN(0xff, 274), + MX31_PIN_A16 = IOMUX_PIN(0xff, 275), + MX31_PIN_A14 = IOMUX_PIN(0xff, 276), + MX31_PIN_A15 = IOMUX_PIN(0xff, 277), + MX31_PIN_A13 = IOMUX_PIN(0xff, 278), + MX31_PIN_A12 = IOMUX_PIN(0xff, 279), + MX31_PIN_A11 = IOMUX_PIN(0xff, 280), + MX31_PIN_MA10 = IOMUX_PIN(0xff, 281), + MX31_PIN_A10 = IOMUX_PIN(0xff, 282), + MX31_PIN_A9 = IOMUX_PIN(0xff, 283), + MX31_PIN_A8 = IOMUX_PIN(0xff, 284), + MX31_PIN_A7 = IOMUX_PIN(0xff, 285), + MX31_PIN_A6 = IOMUX_PIN(0xff, 286), + MX31_PIN_A5 = IOMUX_PIN(0xff, 287), + MX31_PIN_A4 = IOMUX_PIN(0xff, 288), + MX31_PIN_A3 = IOMUX_PIN(0xff, 289), + MX31_PIN_A2 = IOMUX_PIN(0xff, 290), + MX31_PIN_A1 = IOMUX_PIN(0xff, 291), + MX31_PIN_A0 = IOMUX_PIN(0xff, 292), + MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293), + MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294), + MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295), + MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296), + MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297), + MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298), + MX31_PIN_CKIL = IOMUX_PIN(0xff, 299), + MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300), + MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301), + MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302), + MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303), + MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304), + MX31_PIN_CLKO = IOMUX_PIN(0xff, 305), + MX31_PIN_POR_B = IOMUX_PIN(0xff, 306), + MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307), + MX31_PIN_CKIH = IOMUX_PIN(0xff, 308), + MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309), + MX31_PIN_SRX0 = IOMUX_PIN(34, 310), + MX31_PIN_STX0 = IOMUX_PIN(33, 311), + MX31_PIN_SVEN0 = IOMUX_PIN(32, 312), + MX31_PIN_SRST0 = IOMUX_PIN(67, 313), + MX31_PIN_SCLK0 = IOMUX_PIN(66, 314), + MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315), + MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316), + MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317), + MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318), + MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319), + MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320), + MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321), + MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322), + MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323), + MX31_PIN_PWMO = IOMUX_PIN( 9, 324), + MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325), + MX31_PIN_COMPARE = IOMUX_PIN( 8, 326), + MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), +}; + +/* + * Convenience values for use with mxc_iomux_mode() + * + * Format here is MX31_PIN_(pin name)__(function) + */ +#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) +#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2) +#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI2_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI2_SS2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI3_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC) +#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) + +/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 + * cspi1_ss1*/ + +/* + * This function configures the pad value for a IOMUX pin. + */ +int imx_iomux_mode(unsigned int pin_mode); +void imx_iomux_set_pad(enum iomux_pins pin, u32 config); +void imx_iomux_set_gpr(enum iomux_gp_func gp, int en); + +#endif + + diff --git a/arch/arm/mach-imx/include/mach/iomux-mx35.h b/arch/arm/mach-imx/include/mach/iomux-mx35.h new file mode 100644 index 0000000000..8a56d86791 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx35.h @@ -0,0 +1,1268 @@ +/* + * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option, NO_PAD_CTRL) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IOMUX_MX35_H__ +#define __MACH_IOMUX_MX35_H__ + +#include <mach/iomux-v3.h> + +/* + * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named + * GPIO_<unit>_<num> see also iomux-v3.h + */ + +/* PAD MUX ALT INPSE PATH */ +#define MX35_PAD_CAPTURE__GPT_CAPIN1 IOMUX_PAD(0x328, 0x004, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__GPT_CMPOUT2 IOMUX_PAD(0x328, 0x004, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__CSPI2_SS1 IOMUX_PAD(0x328, 0x004, 2, 0x7f4, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__EPIT1_EPITO IOMUX_PAD(0x328, 0x004, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__CCM_CLK32K IOMUX_PAD(0x328, 0x004, 4, 0x7d0, 0, NO_PAD_CTRL) +#define MX35_PAD_CAPTURE__GPIO1_4 IOMUX_PAD(0x328, 0x004, 5, 0x850, 0, NO_PAD_CTRL) + +#define MX35_PAD_COMPARE__GPT_CMPOUT1 IOMUX_PAD(0x32c, 0x008, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPT_CAPIN2 IOMUX_PAD(0x32c, 0x008, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPT_CMPOUT3 IOMUX_PAD(0x32c, 0x008, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__EPIT2_EPITO IOMUX_PAD(0x32c, 0x008, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__GPIO1_5 IOMUX_PAD(0x32c, 0x008, 5, 0x854, 0, NO_PAD_CTRL) +#define MX35_PAD_COMPARE__SDMA_EXTDMA_2 IOMUX_PAD(0x32c, 0x008, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_WDOG_RST__WDOG_WDOG_B IOMUX_PAD(0x330, 0x00c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_WDOG_RST__IPU_FLASH_STROBE IOMUX_PAD(0x330, 0x00c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_WDOG_RST__GPIO1_6 IOMUX_PAD(0x330, 0x00c, 5, 0x858, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x334, 0x010, 0, 0x82c, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__CCM_PMIC_RDY IOMUX_PAD(0x334, 0x010, 1, 0x7d4, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__OWIRE_LINE IOMUX_PAD(0x334, 0x010, 2, 0x990, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_0__SDMA_EXTDMA_0 IOMUX_PAD(0x334, 0x010, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x338, 0x014, 0, 0x838, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__PWM_PWMO IOMUX_PAD(0x338, 0x014, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__CSPI1_SS2 IOMUX_PAD(0x338, 0x014, 3, 0x7d8, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT IOMUX_PAD(0x338, 0x014, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO1_1__SDMA_EXTDMA_1 IOMUX_PAD(0x338, 0x014, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO2_0__GPIO2_0 IOMUX_PAD(0x33c, 0x018, 0, 0x868, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK IOMUX_PAD(0x33c, 0x018, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_GPIO3_0__GPIO3_0 IOMUX_PAD(0x340, 0x01c, 0, 0x8e8, 0, NO_PAD_CTRL) +#define MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK IOMUX_PAD(0x340, 0x01c, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RESET_IN_B__CCM_RESET_IN_B IOMUX_PAD(0x344, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_POR_B__CCM_POR_B IOMUX_PAD(0x348, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLKO__CCM_CLKO IOMUX_PAD(0x34c, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CLKO__GPIO1_8 IOMUX_PAD(0x34c, 0x020, 5, 0x860, 0, NO_PAD_CTRL) + +#define MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0 IOMUX_PAD(0x350, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1 IOMUX_PAD(0x354, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0 IOMUX_PAD(0x358, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1 IOMUX_PAD(0x35c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26 IOMUX_PAD(0x360, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_VSTBY__CCM_VSTBY IOMUX_PAD(0x364, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_VSTBY__GPIO1_7 IOMUX_PAD(0x364, 0x024, 5, 0x85c, 0, NO_PAD_CTRL) + +#define MX35_PAD_A0__EMI_EIM_DA_L_0 IOMUX_PAD(0x368, 0x028, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A1__EMI_EIM_DA_L_1 IOMUX_PAD(0x36c, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A2__EMI_EIM_DA_L_2 IOMUX_PAD(0x370, 0x030, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A3__EMI_EIM_DA_L_3 IOMUX_PAD(0x374, 0x034, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A4__EMI_EIM_DA_L_4 IOMUX_PAD(0x378, 0x038, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A5__EMI_EIM_DA_L_5 IOMUX_PAD(0x37c, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A6__EMI_EIM_DA_L_6 IOMUX_PAD(0x380, 0x040, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A7__EMI_EIM_DA_L_7 IOMUX_PAD(0x384, 0x044, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A8__EMI_EIM_DA_H_8 IOMUX_PAD(0x388, 0x048, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A9__EMI_EIM_DA_H_9 IOMUX_PAD(0x38c, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A10__EMI_EIM_DA_H_10 IOMUX_PAD(0x390, 0x050, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MA10__EMI_MA10 IOMUX_PAD(0x394, 0x054, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A11__EMI_EIM_DA_H_11 IOMUX_PAD(0x398, 0x058, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A12__EMI_EIM_DA_H_12 IOMUX_PAD(0x39c, 0x05c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A13__EMI_EIM_DA_H_13 IOMUX_PAD(0x3a0, 0x060, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A14__EMI_EIM_DA_H2_14 IOMUX_PAD(0x3a4, 0x064, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A15__EMI_EIM_DA_H2_15 IOMUX_PAD(0x3a8, 0x068, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A16__EMI_EIM_A_16 IOMUX_PAD(0x3ac, 0x06c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A17__EMI_EIM_A_17 IOMUX_PAD(0x3b0, 0x070, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A18__EMI_EIM_A_18 IOMUX_PAD(0x3b4, 0x074, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A19__EMI_EIM_A_19 IOMUX_PAD(0x3b8, 0x078, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A20__EMI_EIM_A_20 IOMUX_PAD(0x3bc, 0x07c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A21__EMI_EIM_A_21 IOMUX_PAD(0x3c0, 0x080, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A22__EMI_EIM_A_22 IOMUX_PAD(0x3c4, 0x084, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A23__EMI_EIM_A_23 IOMUX_PAD(0x3c8, 0x088, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A24__EMI_EIM_A_24 IOMUX_PAD(0x3cc, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_A25__EMI_EIM_A_25 IOMUX_PAD(0x3d0, 0x090, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDBA1__EMI_EIM_SDBA1 IOMUX_PAD(0x3d4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDBA0__EMI_EIM_SDBA0 IOMUX_PAD(0x3d8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD0__EMI_DRAM_D_0 IOMUX_PAD(0x3dc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1__EMI_DRAM_D_1 IOMUX_PAD(0x3e0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2__EMI_DRAM_D_2 IOMUX_PAD(0x3e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD3__EMI_DRAM_D_3 IOMUX_PAD(0x3e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD4__EMI_DRAM_D_4 IOMUX_PAD(0x3ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD5__EMI_DRAM_D_5 IOMUX_PAD(0x3f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD6__EMI_DRAM_D_6 IOMUX_PAD(0x3f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD7__EMI_DRAM_D_7 IOMUX_PAD(0x3f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD8__EMI_DRAM_D_8 IOMUX_PAD(0x3fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD9__EMI_DRAM_D_9 IOMUX_PAD(0x400, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD10__EMI_DRAM_D_10 IOMUX_PAD(0x404, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD11__EMI_DRAM_D_11 IOMUX_PAD(0x408, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD12__EMI_DRAM_D_12 IOMUX_PAD(0x40c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD13__EMI_DRAM_D_13 IOMUX_PAD(0x410, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD14__EMI_DRAM_D_14 IOMUX_PAD(0x414, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD15__EMI_DRAM_D_15 IOMUX_PAD(0x418, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD16__EMI_DRAM_D_16 IOMUX_PAD(0x41c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD17__EMI_DRAM_D_17 IOMUX_PAD(0x420, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD18__EMI_DRAM_D_18 IOMUX_PAD(0x424, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD19__EMI_DRAM_D_19 IOMUX_PAD(0x428, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD20__EMI_DRAM_D_20 IOMUX_PAD(0x42c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD21__EMI_DRAM_D_21 IOMUX_PAD(0x430, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD22__EMI_DRAM_D_22 IOMUX_PAD(0x434, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD23__EMI_DRAM_D_23 IOMUX_PAD(0x438, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD24__EMI_DRAM_D_24 IOMUX_PAD(0x43c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD25__EMI_DRAM_D_25 IOMUX_PAD(0x440, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD26__EMI_DRAM_D_26 IOMUX_PAD(0x444, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD27__EMI_DRAM_D_27 IOMUX_PAD(0x448, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD28__EMI_DRAM_D_28 IOMUX_PAD(0x44c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD29__EMI_DRAM_D_29 IOMUX_PAD(0x450, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD30__EMI_DRAM_D_30 IOMUX_PAD(0x454, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD31__EMI_DRAM_D_31 IOMUX_PAD(0x458, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM0__EMI_DRAM_DQM_0 IOMUX_PAD(0x45c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM1__EMI_DRAM_DQM_1 IOMUX_PAD(0x460, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM2__EMI_DRAM_DQM_2 IOMUX_PAD(0x464, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DQM3__EMI_DRAM_DQM_3 IOMUX_PAD(0x468, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EB0__EMI_EIM_EB0_B IOMUX_PAD(0x46c, 0x094, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EB1__EMI_EIM_EB1_B IOMUX_PAD(0x470, 0x098, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_OE__EMI_EIM_OE IOMUX_PAD(0x474, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS0__EMI_EIM_CS0 IOMUX_PAD(0x478, 0x0a0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS1__EMI_EIM_CS1 IOMUX_PAD(0x47c, 0x0a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS1__EMI_NANDF_CE3 IOMUX_PAD(0x47c, 0x0a4, 3, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS2__EMI_EIM_CS2 IOMUX_PAD(0x480, 0x0a8, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS3__EMI_EIM_CS3 IOMUX_PAD(0x484, 0x0ac, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS4__EMI_EIM_CS4 IOMUX_PAD(0x488, 0x0b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__EMI_DTACK_B IOMUX_PAD(0x488, 0x0b0, 1, 0x800, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__EMI_NANDF_CE1 IOMUX_PAD(0x488, 0x0b0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS4__GPIO1_20 IOMUX_PAD(0x488, 0x0b0, 5, 0x83c, 0, NO_PAD_CTRL) + +#define MX35_PAD_CS5__EMI_EIM_CS5 IOMUX_PAD(0x48c, 0x0b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__CSPI2_SS2 IOMUX_PAD(0x48c, 0x0b4, 1, 0x7f8, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__CSPI1_SS2 IOMUX_PAD(0x48c, 0x0b4, 2, 0x7d8, 1, NO_PAD_CTRL) +#define MX35_PAD_CS5__EMI_NANDF_CE2 IOMUX_PAD(0x48c, 0x0b4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CS5__GPIO1_21 IOMUX_PAD(0x48c, 0x0b4, 5, 0x840, 0, NO_PAD_CTRL) + +#define MX35_PAD_NF_CE0__EMI_NANDF_CE0 IOMUX_PAD(0x490, 0x0b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NF_CE0__GPIO1_22 IOMUX_PAD(0x490, 0x0b8, 5, 0x844, 0, NO_PAD_CTRL) + +#define MX35_PAD_ECB__EMI_EIM_ECB IOMUX_PAD(0x494, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LBA__EMI_EIM_LBA IOMUX_PAD(0x498, 0x0bc, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_BCLK__EMI_EIM_BCLK IOMUX_PAD(0x49c, 0x0c0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RW__EMI_EIM_RW IOMUX_PAD(0x4a0, 0x0c4, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RAS__EMI_DRAM_RAS IOMUX_PAD(0x4a4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CAS__EMI_DRAM_CAS IOMUX_PAD(0x4a8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDWE__EMI_DRAM_SDWE IOMUX_PAD(0x4ac, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0 IOMUX_PAD(0x4b0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1 IOMUX_PAD(0x4b4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDCLK__EMI_DRAM_SDCLK IOMUX_PAD(0x4b8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS0__EMI_DRAM_SDQS_0 IOMUX_PAD(0x4bc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS1__EMI_DRAM_SDQS_1 IOMUX_PAD(0x4c0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS2__EMI_DRAM_SDQS_2 IOMUX_PAD(0x4c4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SDQS3__EMI_DRAM_SDQS_3 IOMUX_PAD(0x4c8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFWE_B__EMI_NANDF_WE_B IOMUX_PAD(0x4cc, 0x0c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x4cc, 0x0c8, 1, 0x9d8, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x4cc, 0x0c8, 2, 0x924, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__GPIO2_18 IOMUX_PAD(0x4cc, 0x0c8, 5, 0x88c, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0 IOMUX_PAD(0x4cc, 0x0c8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFRE_B__EMI_NANDF_RE_B IOMUX_PAD(0x4d0, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR IOMUX_PAD(0x4d0, 0x0cc, 1, 0x9ec, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__IPU_DISPB_BCLK IOMUX_PAD(0x4d0, 0x0cc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__GPIO2_19 IOMUX_PAD(0x4d0, 0x0cc, 5, 0x890, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1 IOMUX_PAD(0x4d0, 0x0cc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFALE__EMI_NANDF_ALE IOMUX_PAD(0x4d4, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__USB_TOP_USBH2_STP IOMUX_PAD(0x4d4, 0x0d0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__IPU_DISPB_CS0 IOMUX_PAD(0x4d4, 0x0d0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__GPIO2_20 IOMUX_PAD(0x4d4, 0x0d0, 5, 0x898, 0, NO_PAD_CTRL) +#define MX35_PAD_NFALE__ARM11P_TOP_TRACE_2 IOMUX_PAD(0x4d4, 0x0d0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFCLE__EMI_NANDF_CLE IOMUX_PAD(0x4d8, 0x0d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__USB_TOP_USBH2_NXT IOMUX_PAD(0x4d8, 0x0d4, 1, 0x9f0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__IPU_DISPB_PAR_RS IOMUX_PAD(0x4d8, 0x0d4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__GPIO2_21 IOMUX_PAD(0x4d8, 0x0d4, 5, 0x89c, 0, NO_PAD_CTRL) +#define MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3 IOMUX_PAD(0x4d8, 0x0d4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFWP_B__EMI_NANDF_WP_B IOMUX_PAD(0x4dc, 0x0d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x4dc, 0x0d8, 1, 0x9e8, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__IPU_DISPB_WR IOMUX_PAD(0x4dc, 0x0d8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__GPIO2_22 IOMUX_PAD(0x4dc, 0x0d8, 5, 0x8a0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL IOMUX_PAD(0x4dc, 0x0d8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_NFRB__EMI_NANDF_RB IOMUX_PAD(0x4e0, 0x0dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__IPU_DISPB_RD IOMUX_PAD(0x4e0, 0x0dc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__GPIO2_23 IOMUX_PAD(0x4e0, 0x0dc, 5, 0x8a4, 0, NO_PAD_CTRL) +#define MX35_PAD_NFRB__ARM11P_TOP_TRCLK IOMUX_PAD(0x4e0, 0x0dc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D15__EMI_EIM_D_15 IOMUX_PAD(0x4e4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D14__EMI_EIM_D_14 IOMUX_PAD(0x4e8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D13__EMI_EIM_D_13 IOMUX_PAD(0x4ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D12__EMI_EIM_D_12 IOMUX_PAD(0x4f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D11__EMI_EIM_D_11 IOMUX_PAD(0x4f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D10__EMI_EIM_D_10 IOMUX_PAD(0x4f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D9__EMI_EIM_D_9 IOMUX_PAD(0x4fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D8__EMI_EIM_D_8 IOMUX_PAD(0x500, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D7__EMI_EIM_D_7 IOMUX_PAD(0x504, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D6__EMI_EIM_D_6 IOMUX_PAD(0x508, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D5__EMI_EIM_D_5 IOMUX_PAD(0x50c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D4__EMI_EIM_D_4 IOMUX_PAD(0x510, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3__EMI_EIM_D_3 IOMUX_PAD(0x514, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D2__EMI_EIM_D_2 IOMUX_PAD(0x518, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D1__EMI_EIM_D_1 IOMUX_PAD(0x51c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D0__EMI_EIM_D_0 IOMUX_PAD(0x520, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D8__IPU_CSI_D_8 IOMUX_PAD(0x524, 0x0e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__KPP_COL_0 IOMUX_PAD(0x524, 0x0e0, 1, 0x950, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__GPIO1_20 IOMUX_PAD(0x524, 0x0e0, 5, 0x83c, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13 IOMUX_PAD(0x524, 0x0e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D9__IPU_CSI_D_9 IOMUX_PAD(0x528, 0x0e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__KPP_COL_1 IOMUX_PAD(0x528, 0x0e4, 1, 0x954, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__GPIO1_21 IOMUX_PAD(0x528, 0x0e4, 5, 0x840, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14 IOMUX_PAD(0x528, 0x0e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D10__IPU_CSI_D_10 IOMUX_PAD(0x52c, 0x0e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__KPP_COL_2 IOMUX_PAD(0x52c, 0x0e8, 1, 0x958, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__GPIO1_22 IOMUX_PAD(0x52c, 0x0e8, 5, 0x844, 1, NO_PAD_CTRL) +#define MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15 IOMUX_PAD(0x52c, 0x0e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D11__IPU_CSI_D_11 IOMUX_PAD(0x530, 0x0ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D11__KPP_COL_3 IOMUX_PAD(0x530, 0x0ec, 1, 0x95c, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D11__GPIO1_23 IOMUX_PAD(0x530, 0x0ec, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D12__IPU_CSI_D_12 IOMUX_PAD(0x534, 0x0f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D12__KPP_ROW_0 IOMUX_PAD(0x534, 0x0f0, 1, 0x970, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D12__GPIO1_24 IOMUX_PAD(0x534, 0x0f0, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D13__IPU_CSI_D_13 IOMUX_PAD(0x538, 0x0f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D13__KPP_ROW_1 IOMUX_PAD(0x538, 0x0f4, 1, 0x974, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D13__GPIO1_25 IOMUX_PAD(0x538, 0x0f4, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D14__IPU_CSI_D_14 IOMUX_PAD(0x53c, 0x0f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D14__KPP_ROW_2 IOMUX_PAD(0x53c, 0x0f8, 1, 0x978, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D14__GPIO1_26 IOMUX_PAD(0x53c, 0x0f8, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_D15__IPU_CSI_D_15 IOMUX_PAD(0x540, 0x0fc, 0, 0x97c, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D15__KPP_ROW_3 IOMUX_PAD(0x540, 0x0fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_D15__GPIO1_27 IOMUX_PAD(0x540, 0x0fc, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_MCLK__IPU_CSI_MCLK IOMUX_PAD(0x544, 0x100, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_MCLK__GPIO1_28 IOMUX_PAD(0x544, 0x100, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC IOMUX_PAD(0x548, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_VSYNC__GPIO1_29 IOMUX_PAD(0x548, 0x104, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC IOMUX_PAD(0x54c, 0x108, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_HSYNC__GPIO1_30 IOMUX_PAD(0x54c, 0x108, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK IOMUX_PAD(0x550, 0x10c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSI_PIXCLK__GPIO1_31 IOMUX_PAD(0x550, 0x10c, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C1_CLK__I2C1_SCL IOMUX_PAD(0x554, 0x110, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_CLK__GPIO2_24 IOMUX_PAD(0x554, 0x110, 5, 0x8a8, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK IOMUX_PAD(0x554, 0x110, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C1_DAT__I2C1_SDA IOMUX_PAD(0x558, 0x114, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C1_DAT__GPIO2_25 IOMUX_PAD(0x558, 0x114, 5, 0x8ac, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C2_CLK__I2C2_SCL IOMUX_PAD(0x55c, 0x118, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__CAN1_TXCAN IOMUX_PAD(0x55c, 0x118, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR IOMUX_PAD(0x55c, 0x118, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__GPIO2_26 IOMUX_PAD(0x55c, 0x118, 5, 0x8b0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2 IOMUX_PAD(0x55c, 0x118, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_I2C2_DAT__I2C2_SDA IOMUX_PAD(0x560, 0x11c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__CAN1_RXCAN IOMUX_PAD(0x560, 0x11c, 1, 0x7c8, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC IOMUX_PAD(0x560, 0x11c, 2, 0x9f4, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__GPIO2_27 IOMUX_PAD(0x560, 0x11c, 5, 0x8b4, 0, NO_PAD_CTRL) +#define MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3 IOMUX_PAD(0x560, 0x11c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXD4__AUDMUX_AUD4_TXD IOMUX_PAD(0x564, 0x120, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD4__GPIO2_28 IOMUX_PAD(0x564, 0x120, 5, 0x8b8, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0 IOMUX_PAD(0x564, 0x120, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SRXD4__AUDMUX_AUD4_RXD IOMUX_PAD(0x568, 0x124, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD4__GPIO2_29 IOMUX_PAD(0x568, 0x124, 5, 0x8bc, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1 IOMUX_PAD(0x568, 0x124, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCK4__AUDMUX_AUD4_TXC IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK4__GPIO2_30 IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS IOMUX_PAD(0x570, 0x12c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS4__GPIO2_31 IOMUX_PAD(0x570, 0x12c, 5, 0x8c8, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3 IOMUX_PAD(0x570, 0x12c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXD5__AUDMUX_AUD5_TXD IOMUX_PAD(0x574, 0x130, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x574, 0x130, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__CSPI2_MOSI IOMUX_PAD(0x574, 0x130, 2, 0x7ec, 0, NO_PAD_CTRL) +#define MX35_PAD_STXD5__GPIO1_0 IOMUX_PAD(0x574, 0x130, 5, 0x82c, 1, NO_PAD_CTRL) +#define MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4 IOMUX_PAD(0x574, 0x130, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SRXD5__AUDMUX_AUD5_RXD IOMUX_PAD(0x578, 0x134, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__SPDIF_SPDIF_IN1 IOMUX_PAD(0x578, 0x134, 1, 0x998, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__CSPI2_MISO IOMUX_PAD(0x578, 0x134, 2, 0x7e8, 0, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__GPIO1_1 IOMUX_PAD(0x578, 0x134, 5, 0x838, 1, NO_PAD_CTRL) +#define MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5 IOMUX_PAD(0x578, 0x134, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCK5__AUDMUX_AUD5_TXC IOMUX_PAD(0x57c, 0x138, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x57c, 0x138, 1, 0x994, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__CSPI2_SCLK IOMUX_PAD(0x57c, 0x138, 2, 0x7e0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__GPIO1_2 IOMUX_PAD(0x57c, 0x138, 5, 0x848, 0, NO_PAD_CTRL) +#define MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6 IOMUX_PAD(0x57c, 0x138, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS IOMUX_PAD(0x580, 0x13c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__CSPI2_RDY IOMUX_PAD(0x580, 0x13c, 2, 0x7e4, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__GPIO1_3 IOMUX_PAD(0x580, 0x13c, 5, 0x84c, 0, NO_PAD_CTRL) +#define MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7 IOMUX_PAD(0x580, 0x13c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCKR__ESAI_SCKR IOMUX_PAD(0x584, 0x140, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKR__GPIO1_4 IOMUX_PAD(0x584, 0x140, 5, 0x850, 1, NO_PAD_CTRL) +#define MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10 IOMUX_PAD(0x584, 0x140, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FSR__ESAI_FSR IOMUX_PAD(0x588, 0x144, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FSR__GPIO1_5 IOMUX_PAD(0x588, 0x144, 5, 0x854, 1, NO_PAD_CTRL) +#define MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11 IOMUX_PAD(0x588, 0x144, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_HCKR__ESAI_HCKR IOMUX_PAD(0x58c, 0x148, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__AUDMUX_AUD5_RXFS IOMUX_PAD(0x58c, 0x148, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__CSPI2_SS0 IOMUX_PAD(0x58c, 0x148, 2, 0x7f0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__IPU_FLASH_STROBE IOMUX_PAD(0x58c, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKR__GPIO1_6 IOMUX_PAD(0x58c, 0x148, 5, 0x858, 1, NO_PAD_CTRL) +#define MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12 IOMUX_PAD(0x58c, 0x148, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SCKT__ESAI_SCKT IOMUX_PAD(0x590, 0x14c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKT__GPIO1_7 IOMUX_PAD(0x590, 0x14c, 5, 0x85c, 1, NO_PAD_CTRL) +#define MX35_PAD_SCKT__IPU_CSI_D_0 IOMUX_PAD(0x590, 0x14c, 6, 0x930, 0, NO_PAD_CTRL) +#define MX35_PAD_SCKT__KPP_ROW_2 IOMUX_PAD(0x590, 0x14c, 7, 0x978, 1, NO_PAD_CTRL) + +#define MX35_PAD_FST__ESAI_FST IOMUX_PAD(0x594, 0x150, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FST__GPIO1_8 IOMUX_PAD(0x594, 0x150, 5, 0x860, 1, NO_PAD_CTRL) +#define MX35_PAD_FST__IPU_CSI_D_1 IOMUX_PAD(0x594, 0x150, 6, 0x934, 0, NO_PAD_CTRL) +#define MX35_PAD_FST__KPP_ROW_3 IOMUX_PAD(0x594, 0x150, 7, 0x97c, 1, NO_PAD_CTRL) + +#define MX35_PAD_HCKT__ESAI_HCKT IOMUX_PAD(0x598, 0x154, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__AUDMUX_AUD5_RXC IOMUX_PAD(0x598, 0x154, 1, 0x7a8, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__GPIO1_9 IOMUX_PAD(0x598, 0x154, 5, 0x864, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__IPU_CSI_D_2 IOMUX_PAD(0x598, 0x154, 6, 0x938, 0, NO_PAD_CTRL) +#define MX35_PAD_HCKT__KPP_COL_3 IOMUX_PAD(0x598, 0x154, 7, 0x95c, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX5_RX0__ESAI_TX5_RX0 IOMUX_PAD(0x59c, 0x158, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC IOMUX_PAD(0x59c, 0x158, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__CSPI2_SS2 IOMUX_PAD(0x59c, 0x158, 2, 0x7f8, 1, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__CAN2_TXCAN IOMUX_PAD(0x59c, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__UART2_DTR IOMUX_PAD(0x59c, 0x158, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__GPIO1_10 IOMUX_PAD(0x59c, 0x158, 5, 0x830, 0, NO_PAD_CTRL) +#define MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0 IOMUX_PAD(0x59c, 0x158, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TX4_RX1__ESAI_TX4_RX1 IOMUX_PAD(0x5a0, 0x15c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS IOMUX_PAD(0x5a0, 0x15c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__CSPI2_SS3 IOMUX_PAD(0x5a0, 0x15c, 2, 0x7fc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__CAN2_RXCAN IOMUX_PAD(0x5a0, 0x15c, 3, 0x7cc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__UART2_DSR IOMUX_PAD(0x5a0, 0x15c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__GPIO1_11 IOMUX_PAD(0x5a0, 0x15c, 5, 0x834, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__IPU_CSI_D_3 IOMUX_PAD(0x5a0, 0x15c, 6, 0x93c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX4_RX1__KPP_ROW_0 IOMUX_PAD(0x5a0, 0x15c, 7, 0x970, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX3_RX2__ESAI_TX3_RX2 IOMUX_PAD(0x5a4, 0x160, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__I2C3_SCL IOMUX_PAD(0x5a4, 0x160, 1, 0x91c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__EMI_NANDF_CE1 IOMUX_PAD(0x5a4, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__GPIO1_12 IOMUX_PAD(0x5a4, 0x160, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__IPU_CSI_D_4 IOMUX_PAD(0x5a4, 0x160, 6, 0x940, 0, NO_PAD_CTRL) +#define MX35_PAD_TX3_RX2__KPP_ROW_1 IOMUX_PAD(0x5a4, 0x160, 7, 0x974, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX2_RX3__ESAI_TX2_RX3 IOMUX_PAD(0x5a8, 0x164, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__I2C3_SDA IOMUX_PAD(0x5a8, 0x164, 1, 0x920, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__EMI_NANDF_CE2 IOMUX_PAD(0x5a8, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__GPIO1_13 IOMUX_PAD(0x5a8, 0x164, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__IPU_CSI_D_5 IOMUX_PAD(0x5a8, 0x164, 6, 0x944, 0, NO_PAD_CTRL) +#define MX35_PAD_TX2_RX3__KPP_COL_0 IOMUX_PAD(0x5a8, 0x164, 7, 0x950, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX1__ESAI_TX1 IOMUX_PAD(0x5ac, 0x168, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__CCM_PMIC_RDY IOMUX_PAD(0x5ac, 0x168, 1, 0x7d4, 1, NO_PAD_CTRL) +#define MX35_PAD_TX1__CSPI1_SS2 IOMUX_PAD(0x5ac, 0x168, 2, 0x7d8, 2, NO_PAD_CTRL) +#define MX35_PAD_TX1__EMI_NANDF_CE3 IOMUX_PAD(0x5ac, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__UART2_RI IOMUX_PAD(0x5ac, 0x168, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__GPIO1_14 IOMUX_PAD(0x5ac, 0x168, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__IPU_CSI_D_6 IOMUX_PAD(0x5ac, 0x168, 6, 0x948, 0, NO_PAD_CTRL) +#define MX35_PAD_TX1__KPP_COL_1 IOMUX_PAD(0x5ac, 0x168, 7, 0x954, 1, NO_PAD_CTRL) + +#define MX35_PAD_TX0__ESAI_TX0 IOMUX_PAD(0x5b0, 0x16c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5b0, 0x16c, 1, 0x994, 1, NO_PAD_CTRL) +#define MX35_PAD_TX0__CSPI1_SS3 IOMUX_PAD(0x5b0, 0x16c, 2, 0x7dc, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__EMI_DTACK_B IOMUX_PAD(0x5b0, 0x16c, 3, 0x800, 1, NO_PAD_CTRL) +#define MX35_PAD_TX0__UART2_DCD IOMUX_PAD(0x5b0, 0x16c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__GPIO1_15 IOMUX_PAD(0x5b0, 0x16c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__IPU_CSI_D_7 IOMUX_PAD(0x5b0, 0x16c, 6, 0x94c, 0, NO_PAD_CTRL) +#define MX35_PAD_TX0__KPP_COL_2 IOMUX_PAD(0x5b0, 0x16c, 7, 0x958, 1, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x5b4, 0x170, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MOSI__GPIO1_16 IOMUX_PAD(0x5b4, 0x170, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2 IOMUX_PAD(0x5b4, 0x170, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x5b8, 0x174, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MISO__GPIO1_17 IOMUX_PAD(0x5b8, 0x174, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3 IOMUX_PAD(0x5b8, 0x174, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x5bc, 0x178, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__OWIRE_LINE IOMUX_PAD(0x5bc, 0x178, 1, 0x990, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__CSPI2_SS3 IOMUX_PAD(0x5bc, 0x178, 2, 0x7fc, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__GPIO1_18 IOMUX_PAD(0x5bc, 0x178, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4 IOMUX_PAD(0x5bc, 0x178, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x5c0, 0x17c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__PWM_PWMO IOMUX_PAD(0x5c0, 0x17c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__CCM_CLK32K IOMUX_PAD(0x5c0, 0x17c, 2, 0x7d0, 1, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__GPIO1_19 IOMUX_PAD(0x5c0, 0x17c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__IPU_DIAGB_29 IOMUX_PAD(0x5c0, 0x17c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5 IOMUX_PAD(0x5c0, 0x17c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x5c4, 0x180, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__GPIO3_4 IOMUX_PAD(0x5c4, 0x180, 5, 0x904, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30 IOMUX_PAD(0x5c4, 0x180, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1 IOMUX_PAD(0x5c4, 0x180, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY IOMUX_PAD(0x5c8, 0x184, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__GPIO3_5 IOMUX_PAD(0x5c8, 0x184, 5, 0x908, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31 IOMUX_PAD(0x5c8, 0x184, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2 IOMUX_PAD(0x5c8, 0x184, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RXD1__UART1_RXD_MUX IOMUX_PAD(0x5cc, 0x188, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__CSPI2_MOSI IOMUX_PAD(0x5cc, 0x188, 1, 0x7ec, 1, NO_PAD_CTRL) +#define MX35_PAD_RXD1__KPP_COL_4 IOMUX_PAD(0x5cc, 0x188, 4, 0x960, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__GPIO3_6 IOMUX_PAD(0x5cc, 0x188, 5, 0x90c, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16 IOMUX_PAD(0x5cc, 0x188, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TXD1__UART1_TXD_MUX IOMUX_PAD(0x5d0, 0x18c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__CSPI2_MISO IOMUX_PAD(0x5d0, 0x18c, 1, 0x7e8, 1, NO_PAD_CTRL) +#define MX35_PAD_TXD1__KPP_COL_5 IOMUX_PAD(0x5d0, 0x18c, 4, 0x964, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__GPIO3_7 IOMUX_PAD(0x5d0, 0x18c, 5, 0x910, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17 IOMUX_PAD(0x5d0, 0x18c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTS1__UART1_RTS IOMUX_PAD(0x5d4, 0x190, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__CSPI2_SCLK IOMUX_PAD(0x5d4, 0x190, 1, 0x7e0, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__I2C3_SCL IOMUX_PAD(0x5d4, 0x190, 2, 0x91c, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__IPU_CSI_D_0 IOMUX_PAD(0x5d4, 0x190, 3, 0x930, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS1__KPP_COL_6 IOMUX_PAD(0x5d4, 0x190, 4, 0x968, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__GPIO3_8 IOMUX_PAD(0x5d4, 0x190, 5, 0x914, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__EMI_NANDF_CE1 IOMUX_PAD(0x5d4, 0x190, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18 IOMUX_PAD(0x5d4, 0x190, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CTS1__UART1_CTS IOMUX_PAD(0x5d8, 0x194, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__CSPI2_RDY IOMUX_PAD(0x5d8, 0x194, 1, 0x7e4, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__I2C3_SDA IOMUX_PAD(0x5d8, 0x194, 2, 0x920, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__IPU_CSI_D_1 IOMUX_PAD(0x5d8, 0x194, 3, 0x934, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS1__KPP_COL_7 IOMUX_PAD(0x5d8, 0x194, 4, 0x96c, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__GPIO3_9 IOMUX_PAD(0x5d8, 0x194, 5, 0x918, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__EMI_NANDF_CE2 IOMUX_PAD(0x5d8, 0x194, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19 IOMUX_PAD(0x5d8, 0x194, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RXD2__UART2_RXD_MUX IOMUX_PAD(0x5dc, 0x198, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD2__KPP_ROW_4 IOMUX_PAD(0x5dc, 0x198, 4, 0x980, 0, NO_PAD_CTRL) +#define MX35_PAD_RXD2__GPIO3_10 IOMUX_PAD(0x5dc, 0x198, 5, 0x8ec, 0, NO_PAD_CTRL) + +#define MX35_PAD_TXD2__UART2_TXD_MUX IOMUX_PAD(0x5e0, 0x19c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x5e0, 0x19c, 1, 0x994, 2, NO_PAD_CTRL) +#define MX35_PAD_TXD2__KPP_ROW_5 IOMUX_PAD(0x5e0, 0x19c, 4, 0x984, 0, NO_PAD_CTRL) +#define MX35_PAD_TXD2__GPIO3_11 IOMUX_PAD(0x5e0, 0x19c, 5, 0x8f0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTS2__UART2_RTS IOMUX_PAD(0x5e4, 0x1a0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__SPDIF_SPDIF_IN1 IOMUX_PAD(0x5e4, 0x1a0, 1, 0x998, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__CAN2_RXCAN IOMUX_PAD(0x5e4, 0x1a0, 2, 0x7cc, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__IPU_CSI_D_2 IOMUX_PAD(0x5e4, 0x1a0, 3, 0x938, 1, NO_PAD_CTRL) +#define MX35_PAD_RTS2__KPP_ROW_6 IOMUX_PAD(0x5e4, 0x1a0, 4, 0x988, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__GPIO3_12 IOMUX_PAD(0x5e4, 0x1a0, 5, 0x8f4, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__AUDMUX_AUD5_RXC IOMUX_PAD(0x5e4, 0x1a0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_RTS2__UART3_RXD_MUX IOMUX_PAD(0x5e4, 0x1a0, 7, 0x9a0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CTS2__UART2_CTS IOMUX_PAD(0x5e8, 0x1a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x5e8, 0x1a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__CAN2_TXCAN IOMUX_PAD(0x5e8, 0x1a4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__IPU_CSI_D_3 IOMUX_PAD(0x5e8, 0x1a4, 3, 0x93c, 1, NO_PAD_CTRL) +#define MX35_PAD_CTS2__KPP_ROW_7 IOMUX_PAD(0x5e8, 0x1a4, 4, 0x98c, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__GPIO3_13 IOMUX_PAD(0x5e8, 0x1a4, 5, 0x8f8, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__AUDMUX_AUD5_RXFS IOMUX_PAD(0x5e8, 0x1a4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CTS2__UART3_TXD_MUX IOMUX_PAD(0x5e8, 0x1a4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_RTCK__ARM11P_TOP_RTCK IOMUX_PAD(0x5ec, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TCK__SJC_TCK IOMUX_PAD(0x5f0, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TMS__SJC_TMS IOMUX_PAD(0x5f4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TDI__SJC_TDI IOMUX_PAD(0x5f8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TDO__SJC_TDO IOMUX_PAD(0x5fc, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TRSTB__SJC_TRSTB IOMUX_PAD(0x600, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_DE_B__SJC_DE_B IOMUX_PAD(0x604, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SJC_MOD__SJC_MOD IOMUX_PAD(0x608, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR IOMUX_PAD(0x60c, 0x1a8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR IOMUX_PAD(0x60c, 0x1a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_PWR__GPIO3_14 IOMUX_PAD(0x60c, 0x1a8, 5, 0x8fc, 0, NO_PAD_CTRL) + +#define MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC IOMUX_PAD(0x610, 0x1ac, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC IOMUX_PAD(0x610, 0x1ac, 1, 0x9f4, 1, NO_PAD_CTRL) +#define MX35_PAD_USBOTG_OC__GPIO3_15 IOMUX_PAD(0x610, 0x1ac, 5, 0x900, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD0__IPU_DISPB_DAT_0 IOMUX_PAD(0x614, 0x1b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD0__GPIO2_0 IOMUX_PAD(0x614, 0x1b0, 5, 0x868, 1, NO_PAD_CTRL) +#define MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0 IOMUX_PAD(0x614, 0x1b0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD1__IPU_DISPB_DAT_1 IOMUX_PAD(0x618, 0x1b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD1__GPIO2_1 IOMUX_PAD(0x618, 0x1b4, 5, 0x894, 0, NO_PAD_CTRL) +#define MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1 IOMUX_PAD(0x618, 0x1b4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD2__IPU_DISPB_DAT_2 IOMUX_PAD(0x61c, 0x1b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD2__GPIO2_2 IOMUX_PAD(0x61c, 0x1b8, 5, 0x8c0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2 IOMUX_PAD(0x61c, 0x1b8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD3__IPU_DISPB_DAT_3 IOMUX_PAD(0x620, 0x1bc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD3__GPIO2_3 IOMUX_PAD(0x620, 0x1bc, 5, 0x8cc, 0, NO_PAD_CTRL) +#define MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3 IOMUX_PAD(0x620, 0x1bc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD4__IPU_DISPB_DAT_4 IOMUX_PAD(0x624, 0x1c0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD4__GPIO2_4 IOMUX_PAD(0x624, 0x1c0, 5, 0x8d0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4 IOMUX_PAD(0x624, 0x1c0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD5__IPU_DISPB_DAT_5 IOMUX_PAD(0x628, 0x1c4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD5__GPIO2_5 IOMUX_PAD(0x628, 0x1c4, 5, 0x8d4, 0, NO_PAD_CTRL) +#define MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5 IOMUX_PAD(0x628, 0x1c4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD6__IPU_DISPB_DAT_6 IOMUX_PAD(0x62c, 0x1c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD6__GPIO2_6 IOMUX_PAD(0x62c, 0x1c8, 5, 0x8d8, 0, NO_PAD_CTRL) +#define MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6 IOMUX_PAD(0x62c, 0x1c8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD7__IPU_DISPB_DAT_7 IOMUX_PAD(0x630, 0x1cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD7__GPIO2_7 IOMUX_PAD(0x630, 0x1cc, 5, 0x8dc, 0, NO_PAD_CTRL) +#define MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7 IOMUX_PAD(0x630, 0x1cc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD8__IPU_DISPB_DAT_8 IOMUX_PAD(0x634, 0x1d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD8__GPIO2_8 IOMUX_PAD(0x634, 0x1d0, 5, 0x8e0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL) +#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD10__GPIO2_10 IOMUX_PAD(0x63c, 0x1d8, 5, 0x86c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10 IOMUX_PAD(0x63c, 0x1d8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD11__IPU_DISPB_DAT_11 IOMUX_PAD(0x640, 0x1dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__GPIO2_11 IOMUX_PAD(0x640, 0x1dc, 5, 0x870, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11 IOMUX_PAD(0x640, 0x1dc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD11__ARM11P_TOP_TRACE_4 IOMUX_PAD(0x640, 0x1dc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD12__IPU_DISPB_DAT_12 IOMUX_PAD(0x644, 0x1e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__GPIO2_12 IOMUX_PAD(0x644, 0x1e0, 5, 0x874, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12 IOMUX_PAD(0x644, 0x1e0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD12__ARM11P_TOP_TRACE_5 IOMUX_PAD(0x644, 0x1e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD13__IPU_DISPB_DAT_13 IOMUX_PAD(0x648, 0x1e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__GPIO2_13 IOMUX_PAD(0x648, 0x1e4, 5, 0x878, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13 IOMUX_PAD(0x648, 0x1e4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD13__ARM11P_TOP_TRACE_6 IOMUX_PAD(0x648, 0x1e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD14__IPU_DISPB_DAT_14 IOMUX_PAD(0x64c, 0x1e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__GPIO2_14 IOMUX_PAD(0x64c, 0x1e8, 5, 0x87c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x64c, 0x1e8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD14__ARM11P_TOP_TRACE_7 IOMUX_PAD(0x64c, 0x1e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD15__IPU_DISPB_DAT_15 IOMUX_PAD(0x650, 0x1ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__GPIO2_15 IOMUX_PAD(0x650, 0x1ec, 5, 0x880, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x650, 0x1ec, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD15__ARM11P_TOP_TRACE_8 IOMUX_PAD(0x650, 0x1ec, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD16__IPU_DISPB_DAT_16 IOMUX_PAD(0x654, 0x1f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x654, 0x1f0, 2, 0x928, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__GPIO2_16 IOMUX_PAD(0x654, 0x1f0, 5, 0x884, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x654, 0x1f0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD16__ARM11P_TOP_TRACE_9 IOMUX_PAD(0x654, 0x1f0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD17__IPU_DISPB_DAT_17 IOMUX_PAD(0x658, 0x1f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__IPU_DISPB_CS2 IOMUX_PAD(0x658, 0x1f4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__GPIO2_17 IOMUX_PAD(0x658, 0x1f4, 5, 0x888, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3 IOMUX_PAD(0x658, 0x1f4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD17__ARM11P_TOP_TRACE_10 IOMUX_PAD(0x658, 0x1f4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD18__IPU_DISPB_DAT_18 IOMUX_PAD(0x65c, 0x1f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x65c, 0x1f8, 1, 0x924, 1, NO_PAD_CTRL) +#define MX35_PAD_LD18__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x65c, 0x1f8, 2, 0x928, 1, NO_PAD_CTRL) +#define MX35_PAD_LD18__ESDHC3_CMD IOMUX_PAD(0x65c, 0x1f8, 3, 0x818, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x65c, 0x1f8, 4, 0x9b0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__GPIO3_24 IOMUX_PAD(0x65c, 0x1f8, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4 IOMUX_PAD(0x65c, 0x1f8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD18__ARM11P_TOP_TRACE_11 IOMUX_PAD(0x65c, 0x1f8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD19__IPU_DISPB_DAT_19 IOMUX_PAD(0x660, 0x1fc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__IPU_DISPB_BCLK IOMUX_PAD(0x660, 0x1fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__IPU_DISPB_CS1 IOMUX_PAD(0x660, 0x1fc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__ESDHC3_CLK IOMUX_PAD(0x660, 0x1fc, 3, 0x814, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__USB_TOP_USBOTG_DIR IOMUX_PAD(0x660, 0x1fc, 4, 0x9c4, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__GPIO3_25 IOMUX_PAD(0x660, 0x1fc, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5 IOMUX_PAD(0x660, 0x1fc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD19__ARM11P_TOP_TRACE_12 IOMUX_PAD(0x660, 0x1fc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD20__IPU_DISPB_DAT_20 IOMUX_PAD(0x664, 0x200, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__IPU_DISPB_CS0 IOMUX_PAD(0x664, 0x200, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__IPU_DISPB_SD_CLK IOMUX_PAD(0x664, 0x200, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__ESDHC3_DAT0 IOMUX_PAD(0x664, 0x200, 3, 0x81c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__GPIO3_26 IOMUX_PAD(0x664, 0x200, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3 IOMUX_PAD(0x664, 0x200, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD20__ARM11P_TOP_TRACE_13 IOMUX_PAD(0x664, 0x200, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD21__IPU_DISPB_DAT_21 IOMUX_PAD(0x668, 0x204, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__IPU_DISPB_PAR_RS IOMUX_PAD(0x668, 0x204, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__IPU_DISPB_SER_RS IOMUX_PAD(0x668, 0x204, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__ESDHC3_DAT1 IOMUX_PAD(0x668, 0x204, 3, 0x820, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__USB_TOP_USBOTG_STP IOMUX_PAD(0x668, 0x204, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__GPIO3_27 IOMUX_PAD(0x668, 0x204, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL IOMUX_PAD(0x668, 0x204, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD21__ARM11P_TOP_TRACE_14 IOMUX_PAD(0x668, 0x204, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD22__IPU_DISPB_DAT_22 IOMUX_PAD(0x66c, 0x208, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__IPU_DISPB_WR IOMUX_PAD(0x66c, 0x208, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__IPU_DISPB_SD_D_I IOMUX_PAD(0x66c, 0x208, 2, 0x92c, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__ESDHC3_DAT2 IOMUX_PAD(0x66c, 0x208, 3, 0x824, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__USB_TOP_USBOTG_NXT IOMUX_PAD(0x66c, 0x208, 4, 0x9c8, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__GPIO3_28 IOMUX_PAD(0x66c, 0x208, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR IOMUX_PAD(0x66c, 0x208, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD22__ARM11P_TOP_TRCTL IOMUX_PAD(0x66c, 0x208, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_LD23__IPU_DISPB_DAT_23 IOMUX_PAD(0x670, 0x20c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__IPU_DISPB_RD IOMUX_PAD(0x670, 0x20c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__IPU_DISPB_SD_D_IO IOMUX_PAD(0x670, 0x20c, 2, 0x92c, 1, NO_PAD_CTRL) +#define MX35_PAD_LD23__ESDHC3_DAT3 IOMUX_PAD(0x670, 0x20c, 3, 0x828, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x670, 0x20c, 4, 0x9c0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__GPIO3_29 IOMUX_PAD(0x670, 0x20c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS IOMUX_PAD(0x670, 0x20c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_LD23__ARM11P_TOP_TRCLK IOMUX_PAD(0x670, 0x20c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC IOMUX_PAD(0x674, 0x210, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO IOMUX_PAD(0x674, 0x210, 2, 0x92c, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__GPIO3_30 IOMUX_PAD(0x674, 0x210, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE IOMUX_PAD(0x674, 0x210, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15 IOMUX_PAD(0x674, 0x210, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK IOMUX_PAD(0x678, 0x214, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK IOMUX_PAD(0x678, 0x214, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__GPIO3_31 IOMUX_PAD(0x678, 0x214, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0 IOMUX_PAD(0x678, 0x214, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16 IOMUX_PAD(0x678, 0x214, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY IOMUX_PAD(0x67c, 0x218, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O IOMUX_PAD(0x67c, 0x218, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__GPIO1_0 IOMUX_PAD(0x67c, 0x218, 5, 0x82c, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1 IOMUX_PAD(0x67c, 0x218, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17 IOMUX_PAD(0x67c, 0x218, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_CONTRAST__IPU_DISPB_CONTR IOMUX_PAD(0x680, 0x21c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__GPIO1_1 IOMUX_PAD(0x680, 0x21c, 5, 0x838, 2, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2 IOMUX_PAD(0x680, 0x21c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18 IOMUX_PAD(0x680, 0x21c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC IOMUX_PAD(0x684, 0x220, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__IPU_DISPB_CS1 IOMUX_PAD(0x684, 0x220, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__GPIO1_2 IOMUX_PAD(0x684, 0x220, 5, 0x848, 1, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD IOMUX_PAD(0x684, 0x220, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19 IOMUX_PAD(0x684, 0x220, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_REV__IPU_DISPB_D3_REV IOMUX_PAD(0x688, 0x224, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__IPU_DISPB_SER_RS IOMUX_PAD(0x688, 0x224, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__GPIO1_3 IOMUX_PAD(0x688, 0x224, 5, 0x84c, 1, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB IOMUX_PAD(0x688, 0x224, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20 IOMUX_PAD(0x688, 0x224, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS IOMUX_PAD(0x68c, 0x228, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__IPU_DISPB_CS2 IOMUX_PAD(0x68c, 0x228, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__GPIO1_4 IOMUX_PAD(0x68c, 0x228, 5, 0x850, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0 IOMUX_PAD(0x68c, 0x228, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21 IOMUX_PAD(0x68c, 0x228, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL IOMUX_PAD(0x690, 0x22c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x690, 0x22c, 2, 0x928, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__GPIO1_5 IOMUX_PAD(0x690, 0x22c, 5, 0x854, 2, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__GPIO1_11 IOMUX_PAD(0x6a8, 0x244, 5, 0x834, 1, NO_PAD_CTRL) +#define MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26 IOMUX_PAD(0x6a8, 0x244, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2_CMD__ESDHC2_CMD IOMUX_PAD(0x6ac, 0x248, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__I2C3_SCL IOMUX_PAD(0x6ac, 0x248, 1, 0x91c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__ESDHC1_DAT4 IOMUX_PAD(0x6ac, 0x248, 2, 0x804, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__IPU_CSI_D_2 IOMUX_PAD(0x6ac, 0x248, 3, 0x938, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x6ac, 0x248, 4, 0x9dc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__GPIO2_0 IOMUX_PAD(0x6ac, 0x248, 5, 0x868, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x6ac, 0x248, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6ac, 0x248, 7, 0x928, 3, NO_PAD_CTRL) + +#define MX35_PAD_SD2_CLK__ESDHC2_CLK IOMUX_PAD(0x6b0, 0x24c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__I2C3_SDA IOMUX_PAD(0x6b0, 0x24c, 1, 0x920, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__ESDHC1_DAT5 IOMUX_PAD(0x6b0, 0x24c, 2, 0x808, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__IPU_CSI_D_3 IOMUX_PAD(0x6b0, 0x24c, 3, 0x93c, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x6b0, 0x24c, 4, 0x9e0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__GPIO2_1 IOMUX_PAD(0x6b0, 0x24c, 5, 0x894, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1 IOMUX_PAD(0x6b0, 0x24c, 6, 0x998, 2, NO_PAD_CTRL) +#define MX35_PAD_SD2_CLK__IPU_DISPB_CS2 IOMUX_PAD(0x6b0, 0x24c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA0__ESDHC2_DAT0 IOMUX_PAD(0x6b4, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__UART3_RXD_MUX IOMUX_PAD(0x6b4, 0x250, 1, 0x9a0, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__ESDHC1_DAT6 IOMUX_PAD(0x6b4, 0x250, 2, 0x80c, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__IPU_CSI_D_4 IOMUX_PAD(0x6b4, 0x250, 3, 0x940, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x6b4, 0x250, 4, 0x9e4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__GPIO2_2 IOMUX_PAD(0x6b4, 0x250, 5, 0x8c0, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x6b4, 0x250, 6, 0x994, 3, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA1__ESDHC2_DAT1 IOMUX_PAD(0x6b8, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__UART3_TXD_MUX IOMUX_PAD(0x6b8, 0x254, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__ESDHC1_DAT7 IOMUX_PAD(0x6b8, 0x254, 2, 0x810, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__IPU_CSI_D_5 IOMUX_PAD(0x6b8, 0x254, 3, 0x944, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x6b8, 0x254, 4, 0x9cc, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA1__GPIO2_3 IOMUX_PAD(0x6b8, 0x254, 5, 0x8cc, 1, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA2__ESDHC2_DAT2 IOMUX_PAD(0x6bc, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__UART3_RTS IOMUX_PAD(0x6bc, 0x258, 1, 0x99c, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__CAN1_RXCAN IOMUX_PAD(0x6bc, 0x258, 2, 0x7c8, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__IPU_CSI_D_6 IOMUX_PAD(0x6bc, 0x258, 3, 0x948, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x6bc, 0x258, 4, 0x9d0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA2__GPIO2_4 IOMUX_PAD(0x6bc, 0x258, 5, 0x8d0, 1, NO_PAD_CTRL) + +#define MX35_PAD_SD2_DATA3__ESDHC2_DAT3 IOMUX_PAD(0x6c0, 0x25c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__UART3_CTS IOMUX_PAD(0x6c0, 0x25c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__CAN1_TXCAN IOMUX_PAD(0x6c0, 0x25c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__IPU_CSI_D_7 IOMUX_PAD(0x6c0, 0x25c, 3, 0x94c, 1, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x6c0, 0x25c, 4, 0x9d4, 0, NO_PAD_CTRL) +#define MX35_PAD_SD2_DATA3__GPIO2_5 IOMUX_PAD(0x6c0, 0x25c, 5, 0x8d4, 1, NO_PAD_CTRL) + +#define MX35_PAD_ATA_CS0__ATA_CS0 IOMUX_PAD(0x6c4, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__CSPI1_SS3 IOMUX_PAD(0x6c4, 0x260, 1, 0x7dc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__IPU_DISPB_CS1 IOMUX_PAD(0x6c4, 0x260, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__GPIO2_6 IOMUX_PAD(0x6c4, 0x260, 5, 0x8d8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__IPU_DIAGB_0 IOMUX_PAD(0x6c4, 0x260, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0 IOMUX_PAD(0x6c4, 0x260, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_CS1__ATA_CS1 IOMUX_PAD(0x6c8, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__IPU_DISPB_CS2 IOMUX_PAD(0x6c8, 0x264, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__CSPI2_SS0 IOMUX_PAD(0x6c8, 0x264, 4, 0x7f0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__GPIO2_7 IOMUX_PAD(0x6c8, 0x264, 5, 0x8dc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__IPU_DIAGB_1 IOMUX_PAD(0x6c8, 0x264, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1 IOMUX_PAD(0x6c8, 0x264, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DIOR__ATA_DIOR IOMUX_PAD(0x6cc, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__ESDHC3_DAT0 IOMUX_PAD(0x6cc, 0x268, 1, 0x81c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR IOMUX_PAD(0x6cc, 0x268, 2, 0x9c4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__IPU_DISPB_BE0 IOMUX_PAD(0x6cc, 0x268, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__CSPI2_SS1 IOMUX_PAD(0x6cc, 0x268, 4, 0x7f4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__GPIO2_8 IOMUX_PAD(0x6cc, 0x268, 5, 0x8e0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__IPU_DIAGB_2 IOMUX_PAD(0x6cc, 0x268, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2 IOMUX_PAD(0x6cc, 0x268, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DIOW__ATA_DIOW IOMUX_PAD(0x6d0, 0x26c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 IOMUX_PAD(0x6d0, 0x26c, 1, 0x820, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP IOMUX_PAD(0x6d0, 0x26c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__IPU_DISPB_BE1 IOMUX_PAD(0x6d0, 0x26c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__CSPI2_MOSI IOMUX_PAD(0x6d0, 0x26c, 4, 0x7ec, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__GPIO2_9 IOMUX_PAD(0x6d0, 0x26c, 5, 0x8e4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__IPU_DIAGB_3 IOMUX_PAD(0x6d0, 0x26c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3 IOMUX_PAD(0x6d0, 0x26c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DMACK__ATA_DMACK IOMUX_PAD(0x6d4, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__ESDHC3_DAT2 IOMUX_PAD(0x6d4, 0x270, 1, 0x824, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT IOMUX_PAD(0x6d4, 0x270, 2, 0x9c8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__CSPI2_MISO IOMUX_PAD(0x6d4, 0x270, 4, 0x7e8, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__GPIO2_10 IOMUX_PAD(0x6d4, 0x270, 5, 0x86c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__IPU_DIAGB_4 IOMUX_PAD(0x6d4, 0x270, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0 IOMUX_PAD(0x6d4, 0x270, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_RESET_B__ATA_RESET_B IOMUX_PAD(0x6d8, 0x274, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__ESDHC3_DAT3 IOMUX_PAD(0x6d8, 0x274, 1, 0x828, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6d8, 0x274, 2, 0x9a4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O IOMUX_PAD(0x6d8, 0x274, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__CSPI2_RDY IOMUX_PAD(0x6d8, 0x274, 4, 0x7e4, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__GPIO2_11 IOMUX_PAD(0x6d8, 0x274, 5, 0x870, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__IPU_DIAGB_5 IOMUX_PAD(0x6d8, 0x274, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1 IOMUX_PAD(0x6d8, 0x274, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_IORDY__ATA_IORDY IOMUX_PAD(0x6dc, 0x278, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ESDHC3_DAT4 IOMUX_PAD(0x6dc, 0x278, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6dc, 0x278, 2, 0x9a8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO IOMUX_PAD(0x6dc, 0x278, 3, 0x92c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ESDHC2_DAT4 IOMUX_PAD(0x6dc, 0x278, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__GPIO2_12 IOMUX_PAD(0x6dc, 0x278, 5, 0x874, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__IPU_DIAGB_6 IOMUX_PAD(0x6dc, 0x278, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2 IOMUX_PAD(0x6dc, 0x278, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA0__ATA_DATA_0 IOMUX_PAD(0x6e0, 0x27c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ESDHC3_DAT5 IOMUX_PAD(0x6e0, 0x27c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6e0, 0x27c, 2, 0x9ac, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x6e0, 0x27c, 3, 0x928, 4, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ESDHC2_DAT5 IOMUX_PAD(0x6e0, 0x27c, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__GPIO2_13 IOMUX_PAD(0x6e0, 0x27c, 5, 0x878, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__IPU_DIAGB_7 IOMUX_PAD(0x6e0, 0x27c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3 IOMUX_PAD(0x6e0, 0x27c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA1__ATA_DATA_1 IOMUX_PAD(0x6e4, 0x280, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ESDHC3_DAT6 IOMUX_PAD(0x6e4, 0x280, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3 IOMUX_PAD(0x6e4, 0x280, 2, 0x9b0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK IOMUX_PAD(0x6e4, 0x280, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ESDHC2_DAT6 IOMUX_PAD(0x6e4, 0x280, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__GPIO2_14 IOMUX_PAD(0x6e4, 0x280, 5, 0x87c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__IPU_DIAGB_8 IOMUX_PAD(0x6e4, 0x280, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27 IOMUX_PAD(0x6e4, 0x280, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA2__ATA_DATA_2 IOMUX_PAD(0x6e8, 0x284, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ESDHC3_DAT7 IOMUX_PAD(0x6e8, 0x284, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x6e8, 0x284, 2, 0x9b4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS IOMUX_PAD(0x6e8, 0x284, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ESDHC2_DAT7 IOMUX_PAD(0x6e8, 0x284, 4, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__GPIO2_15 IOMUX_PAD(0x6e8, 0x284, 5, 0x880, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__IPU_DIAGB_9 IOMUX_PAD(0x6e8, 0x284, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28 IOMUX_PAD(0x6e8, 0x284, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA3__ATA_DATA_3 IOMUX_PAD(0x6e8, 0x288, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ESDHC3_CLK IOMUX_PAD(0x6e8, 0x288, 1, 0x814, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x6e8, 0x288, 2, 0x9b8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__CSPI2_SCLK IOMUX_PAD(0x6e8, 0x288, 4, 0x7e0, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__GPIO2_16 IOMUX_PAD(0x6e8, 0x288, 5, 0x884, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__IPU_DIAGB_10 IOMUX_PAD(0x6e8, 0x288, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29 IOMUX_PAD(0x6e8, 0x288, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA4__ATA_DATA_4 IOMUX_PAD(0x6f0, 0x28c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__ESDHC3_CMD IOMUX_PAD(0x6f0, 0x28c, 1, 0x818, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x6f0, 0x28c, 2, 0x9bc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__GPIO2_17 IOMUX_PAD(0x6f0, 0x28c, 5, 0x888, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__IPU_DIAGB_11 IOMUX_PAD(0x6f0, 0x28c, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30 IOMUX_PAD(0x6f0, 0x28c, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA5__ATA_DATA_5 IOMUX_PAD(0x6f4, 0x290, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7 IOMUX_PAD(0x6f4, 0x290, 2, 0x9c0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__GPIO2_18 IOMUX_PAD(0x6f4, 0x290, 5, 0x88c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__IPU_DIAGB_12 IOMUX_PAD(0x6f4, 0x290, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31 IOMUX_PAD(0x6f4, 0x290, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA6__ATA_DATA_6 IOMUX_PAD(0x6f8, 0x294, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__CAN1_TXCAN IOMUX_PAD(0x6f8, 0x294, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__UART1_DTR IOMUX_PAD(0x6f8, 0x294, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD IOMUX_PAD(0x6f8, 0x294, 3, 0x7b4, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__GPIO2_19 IOMUX_PAD(0x6f8, 0x294, 5, 0x890, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA6__IPU_DIAGB_13 IOMUX_PAD(0x6f8, 0x294, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA7__ATA_DATA_7 IOMUX_PAD(0x6fc, 0x298, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__CAN1_RXCAN IOMUX_PAD(0x6fc, 0x298, 1, 0x7c8, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__UART1_DSR IOMUX_PAD(0x6fc, 0x298, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD IOMUX_PAD(0x6fc, 0x298, 3, 0x7b0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__GPIO2_20 IOMUX_PAD(0x6fc, 0x298, 5, 0x898, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA7__IPU_DIAGB_14 IOMUX_PAD(0x6fc, 0x298, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA8__ATA_DATA_8 IOMUX_PAD(0x700, 0x29c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__UART3_RTS IOMUX_PAD(0x700, 0x29c, 1, 0x99c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__UART1_RI IOMUX_PAD(0x700, 0x29c, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC IOMUX_PAD(0x700, 0x29c, 3, 0x7c0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__GPIO2_21 IOMUX_PAD(0x700, 0x29c, 5, 0x89c, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA8__IPU_DIAGB_15 IOMUX_PAD(0x700, 0x29c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA9__ATA_DATA_9 IOMUX_PAD(0x704, 0x2a0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__UART3_CTS IOMUX_PAD(0x704, 0x2a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__UART1_DCD IOMUX_PAD(0x704, 0x2a0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS IOMUX_PAD(0x704, 0x2a0, 3, 0x7c4, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__GPIO2_22 IOMUX_PAD(0x704, 0x2a0, 5, 0x8a0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA9__IPU_DIAGB_16 IOMUX_PAD(0x704, 0x2a0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA10__ATA_DATA_10 IOMUX_PAD(0x708, 0x2a4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__UART3_RXD_MUX IOMUX_PAD(0x708, 0x2a4, 1, 0x9a0, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC IOMUX_PAD(0x708, 0x2a4, 3, 0x7b8, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__GPIO2_23 IOMUX_PAD(0x708, 0x2a4, 5, 0x8a4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA10__IPU_DIAGB_17 IOMUX_PAD(0x708, 0x2a4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA11__ATA_DATA_11 IOMUX_PAD(0x70c, 0x2a8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__UART3_TXD_MUX IOMUX_PAD(0x70c, 0x2a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS IOMUX_PAD(0x70c, 0x2a8, 3, 0x7bc, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__GPIO2_24 IOMUX_PAD(0x70c, 0x2a8, 5, 0x8a8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA11__IPU_DIAGB_18 IOMUX_PAD(0x70c, 0x2a8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA12__ATA_DATA_12 IOMUX_PAD(0x710, 0x2ac, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__I2C3_SCL IOMUX_PAD(0x710, 0x2ac, 1, 0x91c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__GPIO2_25 IOMUX_PAD(0x710, 0x2ac, 5, 0x8ac, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA12__IPU_DIAGB_19 IOMUX_PAD(0x710, 0x2ac, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA13__ATA_DATA_13 IOMUX_PAD(0x714, 0x2b0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__I2C3_SDA IOMUX_PAD(0x714, 0x2b0, 1, 0x920, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__GPIO2_26 IOMUX_PAD(0x714, 0x2b0, 5, 0x8b0, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA13__IPU_DIAGB_20 IOMUX_PAD(0x714, 0x2b0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA14__ATA_DATA_14 IOMUX_PAD(0x718, 0x2b4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__IPU_CSI_D_0 IOMUX_PAD(0x718, 0x2b4, 1, 0x930, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__KPP_ROW_0 IOMUX_PAD(0x718, 0x2b4, 3, 0x970, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__GPIO2_27 IOMUX_PAD(0x718, 0x2b4, 5, 0x8b4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA14__IPU_DIAGB_21 IOMUX_PAD(0x718, 0x2b4, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DATA15__ATA_DATA_15 IOMUX_PAD(0x71c, 0x2b8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__IPU_CSI_D_1 IOMUX_PAD(0x71c, 0x2b8, 1, 0x934, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__KPP_ROW_1 IOMUX_PAD(0x71c, 0x2b8, 3, 0x974, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__GPIO2_28 IOMUX_PAD(0x71c, 0x2b8, 5, 0x8b8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DATA15__IPU_DIAGB_22 IOMUX_PAD(0x71c, 0x2b8, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_INTRQ__ATA_INTRQ IOMUX_PAD(0x720, 0x2bc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__IPU_CSI_D_2 IOMUX_PAD(0x720, 0x2bc, 1, 0x938, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__KPP_ROW_2 IOMUX_PAD(0x720, 0x2bc, 3, 0x978, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__GPIO2_29 IOMUX_PAD(0x720, 0x2bc, 5, 0x8bc, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_INTRQ__IPU_DIAGB_23 IOMUX_PAD(0x720, 0x2bc, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN IOMUX_PAD(0x724, 0x2c0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3 IOMUX_PAD(0x724, 0x2c0, 1, 0x93c, 3, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__KPP_ROW_3 IOMUX_PAD(0x724, 0x2c0, 3, 0x97c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__GPIO2_30 IOMUX_PAD(0x724, 0x2c0, 5, 0x8c4, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24 IOMUX_PAD(0x724, 0x2c0, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DMARQ__ATA_DMARQ IOMUX_PAD(0x728, 0x2c4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__IPU_CSI_D_4 IOMUX_PAD(0x728, 0x2c4, 1, 0x940, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__KPP_COL_0 IOMUX_PAD(0x728, 0x2c4, 3, 0x950, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__GPIO2_31 IOMUX_PAD(0x728, 0x2c4, 5, 0x8c8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__IPU_DIAGB_25 IOMUX_PAD(0x728, 0x2c4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4 IOMUX_PAD(0x728, 0x2c4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA0__ATA_DA_0 IOMUX_PAD(0x72c, 0x2c8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__IPU_CSI_D_5 IOMUX_PAD(0x72c, 0x2c8, 1, 0x944, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__KPP_COL_1 IOMUX_PAD(0x72c, 0x2c8, 3, 0x954, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__GPIO3_0 IOMUX_PAD(0x72c, 0x2c8, 5, 0x8e8, 1, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__IPU_DIAGB_26 IOMUX_PAD(0x72c, 0x2c8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5 IOMUX_PAD(0x72c, 0x2c8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA1__ATA_DA_1 IOMUX_PAD(0x730, 0x2cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__IPU_CSI_D_6 IOMUX_PAD(0x730, 0x2cc, 1, 0x948, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__KPP_COL_2 IOMUX_PAD(0x730, 0x2cc, 3, 0x958, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__GPIO3_1 IOMUX_PAD(0x730, 0x2cc, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__IPU_DIAGB_27 IOMUX_PAD(0x730, 0x2cc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6 IOMUX_PAD(0x730, 0x2cc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_ATA_DA2__ATA_DA_2 IOMUX_PAD(0x734, 0x2d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__IPU_CSI_D_7 IOMUX_PAD(0x734, 0x2d0, 1, 0x94c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__KPP_COL_3 IOMUX_PAD(0x734, 0x2d0, 3, 0x95c, 2, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__GPIO3_2 IOMUX_PAD(0x734, 0x2d0, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__IPU_DIAGB_28 IOMUX_PAD(0x734, 0x2d0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7 IOMUX_PAD(0x734, 0x2d0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MLB_CLK__MLB_MLBCLK IOMUX_PAD(0x738, 0x2d4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_CLK__GPIO3_3 IOMUX_PAD(0x738, 0x2d4, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_MLB_DAT__MLB_MLBDAT IOMUX_PAD(0x73c, 0x2d8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_DAT__GPIO3_4 IOMUX_PAD(0x73c, 0x2d8, 5, 0x904, 1, NO_PAD_CTRL) + +#define MX35_PAD_MLB_SIG__MLB_MLBSIG IOMUX_PAD(0x740, 0x2dc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_MLB_SIG__GPIO3_5 IOMUX_PAD(0x740, 0x2dc, 5, 0x908, 1, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x744, 0x2e0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4 IOMUX_PAD(0x744, 0x2e0, 1, 0x804, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX IOMUX_PAD(0x744, 0x2e0, 2, 0x9a0, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR IOMUX_PAD(0x744, 0x2e0, 3, 0x9ec, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__CSPI2_MOSI IOMUX_PAD(0x744, 0x2e0, 4, 0x7ec, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__GPIO3_6 IOMUX_PAD(0x744, 0x2e0, 5, 0x90c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC IOMUX_PAD(0x744, 0x2e0, 6, 0x928, 5, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0 IOMUX_PAD(0x744, 0x2e0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_CLK__FEC_RX_CLK IOMUX_PAD(0x748, 0x2e4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5 IOMUX_PAD(0x748, 0x2e4, 1, 0x808, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX IOMUX_PAD(0x748, 0x2e4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP IOMUX_PAD(0x748, 0x2e4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__CSPI2_MISO IOMUX_PAD(0x748, 0x2e4, 4, 0x7e8, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__GPIO3_7 IOMUX_PAD(0x748, 0x2e4, 5, 0x910, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I IOMUX_PAD(0x748, 0x2e4, 6, 0x92c, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1 IOMUX_PAD(0x748, 0x2e4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_DV__FEC_RX_DV IOMUX_PAD(0x74c, 0x2e8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__ESDHC1_DAT6 IOMUX_PAD(0x74c, 0x2e8, 1, 0x80c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__UART3_RTS IOMUX_PAD(0x74c, 0x2e8, 2, 0x99c, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT IOMUX_PAD(0x74c, 0x2e8, 3, 0x9f0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__CSPI2_SCLK IOMUX_PAD(0x74c, 0x2e8, 4, 0x7e0, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__GPIO3_8 IOMUX_PAD(0x74c, 0x2e8, 5, 0x914, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK IOMUX_PAD(0x74c, 0x2e8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2 IOMUX_PAD(0x74c, 0x2e8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_COL__FEC_COL IOMUX_PAD(0x750, 0x2ec, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__ESDHC1_DAT7 IOMUX_PAD(0x750, 0x2ec, 1, 0x810, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__UART3_CTS IOMUX_PAD(0x750, 0x2ec, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0 IOMUX_PAD(0x750, 0x2ec, 3, 0x9cc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__CSPI2_RDY IOMUX_PAD(0x750, 0x2ec, 4, 0x7e4, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__GPIO3_9 IOMUX_PAD(0x750, 0x2ec, 5, 0x918, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__IPU_DISPB_SER_RS IOMUX_PAD(0x750, 0x2ec, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3 IOMUX_PAD(0x750, 0x2ec, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA0__FEC_RDATA_0 IOMUX_PAD(0x754, 0x2f0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__PWM_PWMO IOMUX_PAD(0x754, 0x2f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__UART3_DTR IOMUX_PAD(0x754, 0x2f0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1 IOMUX_PAD(0x754, 0x2f0, 3, 0x9d0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__CSPI2_SS0 IOMUX_PAD(0x754, 0x2f0, 4, 0x7f0, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__GPIO3_10 IOMUX_PAD(0x754, 0x2f0, 5, 0x8ec, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1 IOMUX_PAD(0x754, 0x2f0, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4 IOMUX_PAD(0x754, 0x2f0, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA0__FEC_TDATA_0 IOMUX_PAD(0x758, 0x2f4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1 IOMUX_PAD(0x758, 0x2f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__UART3_DSR IOMUX_PAD(0x758, 0x2f4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2 IOMUX_PAD(0x758, 0x2f4, 3, 0x9d4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__CSPI2_SS1 IOMUX_PAD(0x758, 0x2f4, 4, 0x7f4, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__GPIO3_11 IOMUX_PAD(0x758, 0x2f4, 5, 0x8f0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0 IOMUX_PAD(0x758, 0x2f4, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5 IOMUX_PAD(0x758, 0x2f4, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_EN__FEC_TX_EN IOMUX_PAD(0x75c, 0x2f8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1 IOMUX_PAD(0x75c, 0x2f8, 1, 0x998, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__UART3_RI IOMUX_PAD(0x75c, 0x2f8, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3 IOMUX_PAD(0x75c, 0x2f8, 3, 0x9d8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__GPIO3_12 IOMUX_PAD(0x75c, 0x2f8, 5, 0x8f4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS IOMUX_PAD(0x75c, 0x2f8, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6 IOMUX_PAD(0x75c, 0x2f8, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_MDC__FEC_MDC IOMUX_PAD(0x760, 0x2fc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__CAN2_TXCAN IOMUX_PAD(0x760, 0x2fc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__UART3_DCD IOMUX_PAD(0x760, 0x2fc, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4 IOMUX_PAD(0x760, 0x2fc, 3, 0x9dc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__GPIO3_13 IOMUX_PAD(0x760, 0x2fc, 5, 0x8f8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__IPU_DISPB_WR IOMUX_PAD(0x760, 0x2fc, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7 IOMUX_PAD(0x760, 0x2fc, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_MDIO__FEC_MDIO IOMUX_PAD(0x764, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__CAN2_RXCAN IOMUX_PAD(0x764, 0x300, 1, 0x7cc, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5 IOMUX_PAD(0x764, 0x300, 3, 0x9e0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__GPIO3_14 IOMUX_PAD(0x764, 0x300, 5, 0x8fc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__IPU_DISPB_RD IOMUX_PAD(0x764, 0x300, 6, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8 IOMUX_PAD(0x764, 0x300, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TX_ERR__FEC_TX_ERR IOMUX_PAD(0x768, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__OWIRE_LINE IOMUX_PAD(0x768, 0x304, 1, 0x990, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK IOMUX_PAD(0x768, 0x304, 2, 0x994, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6 IOMUX_PAD(0x768, 0x304, 3, 0x9e4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__GPIO3_15 IOMUX_PAD(0x768, 0x304, 5, 0x900, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x768, 0x304, 6, 0x924, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9 IOMUX_PAD(0x768, 0x304, 7, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RX_ERR__FEC_RX_ERR IOMUX_PAD(0x76c, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0 IOMUX_PAD(0x76c, 0x308, 1, 0x930, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7 IOMUX_PAD(0x76c, 0x308, 3, 0x9e8, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__KPP_COL_4 IOMUX_PAD(0x76c, 0x308, 4, 0x960, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__GPIO3_16 IOMUX_PAD(0x76c, 0x308, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO IOMUX_PAD(0x76c, 0x308, 6, 0x92c, 5, NO_PAD_CTRL) + +#define MX35_PAD_FEC_CRS__FEC_CRS IOMUX_PAD(0x770, 0x30c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__IPU_CSI_D_1 IOMUX_PAD(0x770, 0x30c, 1, 0x934, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR IOMUX_PAD(0x770, 0x30c, 3, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__KPP_COL_5 IOMUX_PAD(0x770, 0x30c, 4, 0x964, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__GPIO3_17 IOMUX_PAD(0x770, 0x30c, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_CRS__IPU_FLASH_STROBE IOMUX_PAD(0x770, 0x30c, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA1__FEC_RDATA_1 IOMUX_PAD(0x774, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__IPU_CSI_D_2 IOMUX_PAD(0x774, 0x310, 1, 0x938, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC IOMUX_PAD(0x774, 0x310, 2, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC IOMUX_PAD(0x774, 0x310, 3, 0x9f4, 2, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__KPP_COL_6 IOMUX_PAD(0x774, 0x310, 4, 0x968, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__GPIO3_18 IOMUX_PAD(0x774, 0x310, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0 IOMUX_PAD(0x774, 0x310, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA1__FEC_TDATA_1 IOMUX_PAD(0x778, 0x314, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__IPU_CSI_D_3 IOMUX_PAD(0x778, 0x314, 1, 0x93c, 4, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS IOMUX_PAD(0x778, 0x314, 2, 0x7bc, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__KPP_COL_7 IOMUX_PAD(0x778, 0x314, 4, 0x96c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__GPIO3_19 IOMUX_PAD(0x778, 0x314, 5, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1 IOMUX_PAD(0x778, 0x314, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA2__FEC_RDATA_2 IOMUX_PAD(0x77c, 0x318, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__IPU_CSI_D_4 IOMUX_PAD(0x77c, 0x318, 1, 0x940, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD IOMUX_PAD(0x77c, 0x318, 2, 0x7b4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__KPP_ROW_4 IOMUX_PAD(0x77c, 0x318, 4, 0x980, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA2__GPIO3_20 IOMUX_PAD(0x77c, 0x318, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA2__FEC_TDATA_2 IOMUX_PAD(0x780, 0x31c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__IPU_CSI_D_5 IOMUX_PAD(0x780, 0x31c, 1, 0x944, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD IOMUX_PAD(0x780, 0x31c, 2, 0x7b0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__KPP_ROW_5 IOMUX_PAD(0x780, 0x31c, 4, 0x984, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA2__GPIO3_21 IOMUX_PAD(0x780, 0x31c, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_RDATA3__FEC_RDATA_3 IOMUX_PAD(0x784, 0x320, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__IPU_CSI_D_6 IOMUX_PAD(0x784, 0x320, 1, 0x948, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC IOMUX_PAD(0x784, 0x320, 2, 0x7c0, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__KPP_ROW_6 IOMUX_PAD(0x784, 0x320, 4, 0x988, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_RDATA3__GPIO3_22 IOMUX_PAD(0x784, 0x320, 6, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_FEC_TDATA3__FEC_TDATA_3 IOMUX_PAD(0x788, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__IPU_CSI_D_7 IOMUX_PAD(0x788, 0x324, 1, 0x94c, 3, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS IOMUX_PAD(0x788, 0x324, 2, 0x7c4, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__KPP_ROW_7 IOMUX_PAD(0x788, 0x324, 4, 0x98c, 1, NO_PAD_CTRL) +#define MX35_PAD_FEC_TDATA3__GPIO3_23 IOMUX_PAD(0x788, 0x324, 5, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK IOMUX_PAD(0x78c, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX35_PAD_TEST_MODE__TCU_TEST_MODE IOMUX_PAD(0x790, 0x0, 0, 0x0, 0, NO_PAD_CTRL) + + +#endif /* __MACH_IOMUX_MX35_H__ */ + diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h new file mode 100644 index 0000000000..8b2f1ae7f9 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-v3.h @@ -0,0 +1,107 @@ +/* + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, + * <armlinux@phytec.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __MACH_IOMUX_V3_H__ +#define __MACH_IOMUX_V3_H__ + +/* + * build IOMUX_PAD structure + * + * This iomux scheme is based around pads, which are the physical balls + * on the processor. + * + * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls + * things like driving strength and pullup/pulldown. + * - Each pad can have but not necessarily does have an output routing register + * (IOMUXC_SW_MUX_CTL_PAD_x). + * - Each pad can have but not necessarily does have an input routing register + * (IOMUXC_x_SELECT_INPUT) + * + * The three register sets do not have a fixed offset to each other, + * hence we order this table by pad control registers (which all pads + * have) and put the optional i/o routing registers into additional + * fields. + * + * The naming convention for the pad modes is MX35_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named + * GPIO_<unit>_<num> + * + */ + +struct pad_desc { + unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ + unsigned mux_mode:8; + unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ +#define NO_PAD_CTRL (1 << 16) + unsigned pad_ctrl:17; + unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ + unsigned select_input:3; +}; + +#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ + _select_input, _pad_ctrl) \ + { \ + .mux_ctrl_ofs = _mux_ctrl_ofs, \ + .mux_mode = _mux_mode, \ + .pad_ctrl_ofs = _pad_ctrl_ofs, \ + .pad_ctrl = _pad_ctrl, \ + .select_input_ofs = _select_input_ofs, \ + .select_input = _select_input, \ + } + +/* + * Use to set PAD control + */ +#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0 +#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1 + +#define PAD_CTL_NO_HYSTERESIS 0 +#define PAD_CTL_HYSTERESIS 1 + +#define PAD_CTL_PULL_DISABLED 0x0 +#define PAD_CTL_PULL_KEEPER 0xa +#define PAD_CTL_PULL_DOWN_100K 0xc +#define PAD_CTL_PULL_UP_47K 0xd +#define PAD_CTL_PULL_UP_100K 0xe +#define PAD_CTL_PULL_UP_22K 0xf + +#define PAD_CTL_OUTPUT_CMOS 0 +#define PAD_CTL_OUTPUT_OPEN_DRAIN 1 + +#define PAD_CTL_DRIVE_STRENGTH_NORM 0 +#define PAD_CTL_DRIVE_STRENGTH_HIGH 1 +#define PAD_CTL_DRIVE_STRENGTH_MAX 2 + +#define PAD_CTL_SLEW_RATE_SLOW 0 +#define PAD_CTL_SLEW_RATE_FAST 1 + +/* + * setups a single pad: + * - reserves the pad so that it is not claimed by another driver + * - setups the iomux according to the configuration + */ +int mxc_iomux_v3_setup_pad(struct pad_desc *pad); + +/* + * setups mutliple pads + * convenient way to call the above function with tables + */ +int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); + +#endif /* __MACH_IOMUX_V3_H__*/ diff --git a/arch/arm/mach-imx/include/mach/pmic.h b/arch/arm/mach-imx/include/mach/pmic.h new file mode 100644 index 0000000000..e9a951bd38 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/pmic.h @@ -0,0 +1,11 @@ +#ifndef __ASM_ARCH_PMIC_H +#define __ASM_ARCH_PMIC_H + +/* The only function the PMIC driver currently exports. It's purpose + * is to adjust the switchers to 1.45V in order to speed up the CPU + * to 400MHz. This is probably board dependent, so we have to think + * about a proper API for the PMIC + */ +int pmic_power(void); + +#endif /* __ASM_ARCH_PMIC_H */ diff --git a/arch/arm/mach-imx/include/mach/spi.h b/arch/arm/mach-imx/include/mach/spi.h new file mode 100644 index 0000000000..08be445e8e --- /dev/null +++ b/arch/arm/mach-imx/include/mach/spi.h @@ -0,0 +1,27 @@ + +#ifndef __MACH_SPI_H_ +#define __MACH_SPI_H_ + +/* + * struct spi_imx_master - device.platform_data for SPI controller devices. + * @chipselect: Array of chipselects for this master. Numbers >= 0 mean gpio + * pins, numbers < 0 mean internal CSPI chipselects according + * to MXC_SPI_CS(). Normally you want to use gpio based chip + * selects as the CSPI module tries to be intelligent about + * when to assert the chipselect: The CSPI module deasserts the + * chipselect once it runs out of input data. The other problem + * is that it is not possible to mix between high active and low + * active chipselects on one single bus using the internal + * chipselects. Unfortunately Freescale decided to put some + * chipselects on dedicated pins which are not usable as gpios, + * so we have to support the internal chipselects. + * @num_chipselect: ARRAY_SIZE(chipselect) + */ +struct spi_imx_master { + int *chipselect; + int num_chipselect; +}; + +#define MXC_SPI_CS(no) ((no) - 32) + +#endif /* __MACH_SPI_H_*/ diff --git a/arch/arm/mach-imx/include/mach/u-boot.lds.h b/arch/arm/mach-imx/include/mach/u-boot.lds.h new file mode 100644 index 0000000000..52eb458f0f --- /dev/null +++ b/arch/arm/mach-imx/include/mach/u-boot.lds.h @@ -0,0 +1,9 @@ + +#define PRE_IMAGE .pre_image : { \ + KEEP(*(.flash_header_start*)) \ + . = ALIGN(0x400); \ + KEEP(*(.flash_header*)) \ + KEEP(*(.dcd_entry*)) \ + KEEP(*(.image_len*)) \ + } + diff --git a/arch/arm/mach-imx/iomux-v2.c b/arch/arm/mach-imx/iomux-v2.c index d040deeec5..abb2ebe195 100644 --- a/arch/arm/mach-imx/iomux-v2.c +++ b/arch/arm/mach-imx/iomux-v2.c @@ -19,8 +19,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux-mx31.h> +#include <mach/imx-regs.h> +#include <mach/iomux-mx31.h> /* * IOMUX register (base) addresses diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c index 3b9416e95f..a74f942509 100644 --- a/arch/arm/mach-imx/iomux-v3.c +++ b/arch/arm/mach-imx/iomux-v3.c @@ -20,8 +20,8 @@ */ #include <common.h> #include <asm/io.h> -#include <asm/arch/iomux-v3.h> -#include <asm/arch/imx-regs.h> +#include <mach/iomux-v3.h> +#include <mach/imx-regs.h> /* * setups a single pin: diff --git a/arch/arm/mach-imx/speed-imx1.c b/arch/arm/mach-imx/speed-imx1.c index 9db5d113c5..41b56deeb4 100644 --- a/arch/arm/mach-imx/speed-imx1.c +++ b/arch/arm/mach-imx/speed-imx1.c @@ -23,8 +23,8 @@ #include <common.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> +#include <mach/imx-regs.h> +#include <mach/clock.h> #include <init.h> #include <driver.h> diff --git a/arch/arm/mach-imx/speed-imx21.c b/arch/arm/mach-imx/speed-imx21.c index c9d6d88351..aa0a5281d8 100644 --- a/arch/arm/mach-imx/speed-imx21.c +++ b/arch/arm/mach-imx/speed-imx21.c @@ -16,9 +16,9 @@ */ #include <common.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/generic.h> -#include <asm/arch/clock.h> +#include <mach/imx-regs.h> +#include <mach/generic.h> +#include <mach/clock.h> #include <init.h> #ifndef CLK32 diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c index bc2af193a8..be20880b25 100644 --- a/arch/arm/mach-imx/speed-imx25.c +++ b/arch/arm/mach-imx/speed-imx25.c @@ -1,7 +1,7 @@ #include <common.h> -#include <asm/arch/imx-regs.h> +#include <mach/imx-regs.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include <init.h> unsigned long imx_get_mpllclk(void) diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c index 61fcc72bf2..deaca1eb4d 100644 --- a/arch/arm/mach-imx/speed-imx27.c +++ b/arch/arm/mach-imx/speed-imx27.c @@ -16,9 +16,9 @@ */ #include <common.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/generic.h> -#include <asm/arch/clock.h> +#include <mach/imx-regs.h> +#include <mach/generic.h> +#include <mach/clock.h> #include <init.h> #ifndef CLK32 diff --git a/arch/arm/mach-imx/speed-imx31.c b/arch/arm/mach-imx/speed-imx31.c index 77f861053c..630c648dbf 100644 --- a/arch/arm/mach-imx/speed-imx31.c +++ b/arch/arm/mach-imx/speed-imx31.c @@ -17,8 +17,8 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/clock.h> +#include <mach/imx-regs.h> +#include <mach/clock.h> #include <init.h> ulong imx_get_mpl_dpdgck_clk(void) diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c index 43a6ddb350..8d1614f3de 100644 --- a/arch/arm/mach-imx/speed-imx35.c +++ b/arch/arm/mach-imx/speed-imx35.c @@ -16,9 +16,9 @@ */ #include <common.h> -#include <asm/arch/imx-regs.h> +#include <mach/imx-regs.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <mach/clock.h> #include <init.h> unsigned long imx_get_mpllclk(void) diff --git a/arch/arm/mach-netx/clocksource.c b/arch/arm/mach-netx/clocksource.c index b326c15532..818709df47 100644 --- a/arch/arm/mach-netx/clocksource.c +++ b/arch/arm/mach-netx/clocksource.c @@ -25,7 +25,7 @@ #include <common.h> #include <init.h> #include <clock.h> -#include <asm/arch/netx-regs.h> +#include <mach/netx-regs.h> uint64_t netx_clocksource_read(void) { diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 985f3b8cef..4af945f4d6 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -20,7 +20,7 @@ #include <common.h> #include <command.h> -#include <asm/arch/netx-regs.h> +#include <mach/netx-regs.h> #include "eth_firmware.h" struct fw_header { diff --git a/arch/arm/mach-netx/include/mach/netx-cm.h b/arch/arm/mach-netx/include/mach/netx-cm.h new file mode 100644 index 0000000000..37cf76d1f9 --- /dev/null +++ b/arch/arm/mach-netx/include/mach/netx-cm.h @@ -0,0 +1,32 @@ + +#ifndef __AT_CM_USERAREAS_H__ +#define __AT_CM_USERAREAS_H__ + +int netx_cm_init(void); + +struct netx_cm_userarea_1 { + unsigned short signature; /* configuration block signature */ + unsigned short version; /* version information */ + unsigned short crc16; /* crc16 checksum over all 3 areas, including the reserved blocks */ + unsigned char mac[4][6]; /* mac addresses */ + unsigned char reserved[2]; /* reserved, must be 0 */ +}; + +struct netx_cm_userarea_2 { + unsigned long sdram_size; /* sdram size in bytes */ + unsigned long sdram_control; /* sdram control register value (sdram_general_ctrl) */ + unsigned long sdram_timing; /* sdram timing register value (sdram_timing_ctrl) */ + unsigned char reserved0[20]; /* reserved, must be 0 */ +}; + +struct netx_cm_userarea_3 { + unsigned char reserved[32]; /* reserved, must be 0 */ +}; + +struct netx_cm_userarea { + struct netx_cm_userarea_1 area_1; + struct netx_cm_userarea_2 area_2; + struct netx_cm_userarea_3 area_3; +}; + +#endif /* __AT_CM_USERAREAS_H__ */ diff --git a/arch/arm/mach-netx/include/mach/netx-eth.h b/arch/arm/mach-netx/include/mach/netx-eth.h new file mode 100644 index 0000000000..654cfe73d3 --- /dev/null +++ b/arch/arm/mach-netx/include/mach/netx-eth.h @@ -0,0 +1,9 @@ +#ifndef _ASM_ARCH_NETX_ETH_H +#define _ASM_ARCH_NETX_ETH_H + +struct netx_eth_platform_data { + int xcno; +}; + +#endif /* _ASM_ARCH_NETX_ETH_H */ + diff --git a/arch/arm/mach-netx/include/mach/netx-regs.h b/arch/arm/mach-netx/include/mach/netx-regs.h new file mode 100644 index 0000000000..c2278cdc48 --- /dev/null +++ b/arch/arm/mach-netx/include/mach/netx-regs.h @@ -0,0 +1,322 @@ +/* + * include/asm-arm/arch-netx/netx-regs.h + * + * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_NETX_REGS_H +#define __ASM_ARCH_NETX_REGS_H + +#define NETX_IO_PHYS 0x00100000 +#define io_p2v(x) (x) +#define __REG(base,ofs) (*((volatile unsigned long *)(io_p2v(base) + ofs))) + +#define XPEC_MEM_SIZE 0x4000 +#define XMAC_MEM_SIZE 0x1000 +#define SRAM_MEM_SIZE 0x8000 + +/* offsets relative to the beginning of the io space */ +#define NETX_OFS_SYSTEM 0x00000 +#define NETX_OFS_MEMCR 0x00100 +#define NETX_OFS_DPRAM 0x03000 +#define NETX_OFS_GPIO 0x00800 +#define NETX_OFS_PIO 0x00900 +#define NETX_OFS_UART0 0x00a00 +#define NETX_OFS_UART1 0x00a40 +#define NETX_OFS_UART2 0x00a80 +#define NETX_OF_MIIMU 0x00b00 +#define NETX_OFS_SPI 0x00c00 +#define NETX_OFS_I2C 0x00d00 +#define NETX_OFS_SYSTIME 0x01100 +#define NETX_OFS_RTC 0x01200 +#define NETX_OFS_LCD 0x04000 +#define NETX_OFS_USB 0x20000 +#define NETX_OFS_XMAC0 0x60000 +#define NETX_OFS_XMAC1 0x61000 +#define NETX_OFS_XMAC2 0x62000 +#define NETX_OFS_XMAC3 0x63000 +#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000) +#define NETX_OFS_PFIFO 0x64000 +#define NETX_OFS_XPEC0 0x70000 +#define NETX_OFS_XPEC1 0x74000 +#define NETX_OFS_XPEC2 0x78000 +#define NETX_OFS_XPEC3 0x7c000 +#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000) +#define NETX_OFS_VIC 0xff000 + +#define NETX_PA_SYSTEM (NETX_IO_PHYS + NETX_OFS_SYSTEM) +#define NETX_PA_MEMCR (NETX_IO_PHYS + NETX_OFS_MEMCR) +#define NETX_PA_DPRAM (NETX_IO_PHYS + NETX_OFS_DPRAM) +#define NETX_PA_GPIO (NETX_IO_PHYS + NETX_OFS_GPIO) +#define NETX_PA_PIO (NETX_IO_PHYS + NETX_OFS_PIO) +#define NETX_PA_UART0 (NETX_IO_PHYS + NETX_OFS_UART0) +#define NETX_PA_UART1 (NETX_IO_PHYS + NETX_OFS_UART1) +#define NETX_PA_UART2 (NETX_IO_PHYS + NETX_OFS_UART2) +#define NETX_PA_MIIMU (NETX_IO_PHYS + NETX_OF_MIIMU) +#define NETX_PA_SPI (NETX_IO_PHYS + NETX_OFS_SPI) +#define NETX_PA_I2C (NETX_IO_PHYS + NETX_OFS_I2C) +#define NETX_PA_SYSTIME (NETX_IO_PHYS + NETX_OFS_SYSTIME) +#define NETX_PA_RTC (NETX_IO_PHYS + NETX_OFS_RTC) +#define NETX_PA_LCD (NETX_IO_PHYS + NETX_OFS_LCD) +#define NETX_PA_USB (NETX_IO_PHYS + NETX_OFS_USB) +#define NETX_PA_XMAC0 (NETX_IO_PHYS + NETX_OFS_XMAC0) +#define NETX_PA_XMAC1 (NETX_IO_PHYS + NETX_OFS_XMAC1) +#define NETX_PA_XMAC2 (NETX_IO_PHYS + NETX_OFS_XMAC2) +#define NETX_PA_XMAC3 (NETX_IO_PHYS + NETX_OFS_XMAC3) +#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no)) +#define NETX_PA_PFIFO (NETX_IO_PHYS + NETX_OFS_PFIFO) +#define NETX_PA_XPEC0 (NETX_IO_PHYS + NETX_OFS_XPEC0) +#define NETX_PA_XPEC1 (NETX_IO_PHYS + NETX_OFS_XPEC1) +#define NETX_PA_XPEC2 (NETX_IO_PHYS + NETX_OFS_XPEC2) +#define NETX_PA_XPEC3 (NETX_IO_PHYS + NETX_OFS_XPEC3) +#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no)) +#define NETX_PA_VIC (NETX_IO_PHYS + NETX_OFS_VIC) + +/********************************* + * System functions * + *********************************/ + +#define SYSTEM_REG(x) __REG(NETX_PA_SYSTEM, (x)) +#define SYSTEM_BOO_SR 0x00 +#define SYSTEM_IOC_CR 0x04 +#define SYSTEM_IOC_MR 0x08 +#define SYSTEM_RES_CR 0x0c +#define SYSTEM_PHY_CONTROL 0x10 +#define SYSTEM_REV 0x34 +#define SYSTEM_IOC_ACCESS_KEY 0x70 +#define SYSTEM_WDG_TR 0x200 +#define SYSTEM_WDG_CTR 0x204 +#define SYSTEM_WDG_IRQ_TIMEOUT 0x208 +#define SYSTEM_WDG_RES_TIMEOUT 0x20c + +#define PHY_CONTROL_RESET (1<<31) +#define PHY_CONTROL_SIM_BYP (1<<30) +#define PHY_CONTROL_CLK_XLATIN (1<<29) +#define PHY_CONTROL_PHY1_EN (1<<21) +#define PHY_CONTROL_PHY1_NP_MSG_CODE +#define PHY_CONTROL_PHY1_AUTOMDIX (1<<17) +#define PHY_CONTROL_PHY1_FIXMODE (1<<16) +#define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13) +#define PHY_CONTROL_PHY0_EN (1<<12) +#define PHY_CONTROL_PHY0_NP_MSG_CODE +#define PHY_CONTROL_PHY0_AUTOMDIX (1<<8) +#define PHY_CONTROL_PHY0_FIXMODE (1<<7) +#define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4) +#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf) + +#define PHY_MODE_10BASE_T_HALF 0 +#define PHY_MODE_10BASE_T_FULL 1 +#define PHY_MODE_100BASE_TX_FX_FULL 2 +#define PHY_MODE_100BASE_TX_FX_HALF 3 +#define PHY_MODE_100BASE_TX_HALF 4 +#define PHY_MODE_REPEATER 5 +#define PHY_MODE_POWER_DOWN 6 +#define PHY_MODE_ALL 7 + +/********************************* + * Vector interrupt controller * + *********************************/ + +/* Registers */ +#define VIC_REG(x) __REG(NETX_PA_VIC, (x)) +#define VIC_IRQ_STATUS 0x00 +#define VIC_FIQ_STATUS 0x04 +#define VIC_IRQ_RAW_STATUS 0x08 +#define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */ +#define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */ +#define VIC_IRQ_ENABLE_CLEAR 0x14 +#define VIC_IRQ_SOFT 0x18 +#define VIC_IRQ_SOFT_CLEAR 0x1C +#define VIC_PROTECT 0x20 +#define VIC_VECT_ADDR 0x30 +#define VIC_DEF_VECT_ADDR 0x34 +#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ +#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ +#define VIC_ITCR 0x300 /* VIC test control register */ + +/* Bits */ +#define VECT_CNTL_ENABLE (1 << 5) + +/******************************* + * GPIO and timer module * + *******************************/ + +/* Registers */ +#define GPIO_REG(x) __REG(NETX_PA_GPIO, (x)) +#define GPIO_CFG(gpio) (0x0 + ((gpio)<<2)) +#define GPIO_THRESHOLD_CAPTURE(gpio) (0x40 + ((gpio)<<2)) +#define GPIO_COUNTER_CTRL(counter) (0x80 + ((counter)<<2)) +#define GPIO_COUNTER_MAX(counter) (0x94 + ((counter)<<2)) +#define GPIO_COUNTER_CURRENT(counter) (0xa8 + ((counter)<<2)) +#define GPIO_IRQ_ENABLE (0xbc) +#define GPIO_IRQ_DISABLE (0xc0) +#define GPIO_SYSTIME_NS_CMP (0xc4) +#define GPIO_LINE (0xc8) +#define GPIO_IRQ (0xd0) + +/* Bits */ +#define CFG_IOCFG_GP_INPUT (0x0) +#define CFG_IOCFG_GP_OUTPUT (0x1) +#define CFG_IOCFG_GP_UART (0x2) +#define CFG_INV (1<<2) +#define CFG_MODE_INPUT_READ (0<<3) +#define CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3) +#define CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3) +#define CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3) +#define CFG_COUNT_REF_COUNTER0 (0<<5) +#define CFG_COUNT_REF_COUNTER1 (1<<5) +#define CFG_COUNT_REF_COUNTER2 (2<<5) +#define CFG_COUNT_REF_COUNTER3 (3<<5) +#define CFG_COUNT_REF_COUNTER4 (4<<5) +#define CFG_COUNT_REF_SYSTIME (7<<5) + +#define COUNTER_CTRL_RUN (1<<0) +#define COUNTER_CTRL_SYM (1<<1) +#define COUNTER_CTRL_ONCE (1<<2) +#define COUNTER_CTRL_IRQ_EN (1<<3) +#define COUNTER_CTRL_CNT_EVENT (1<<4) +#define COUNTER_CTRL_RST_EN (1<<5) +#define COUNTER_CTRL_SEL_EVENT (1<<6) +#define COUNTER_CTRL_GPIO_REF /* FIXME */ + +#define GPIO_BIT(gpio) (1<<(gpio)) +#define COUNTER_BIT(counter) ((1<<16)<<(counter)) + +/******************************* + * PIO * + *******************************/ + +/* Registers */ +#define NETX_PIO_REG(ofs) __REG(NETX_PA_PIO, ofs) +#define NETX_PIO_INPIO NETX_PIO_REG(0x0) +#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4) +#define NETX_PIO_OEPIO NETX_PIO_REG(0x8) + +/******************************* + * MII Unit * + *******************************/ +#define MIIMU_REG __REG(NETX_PA_MIIMU, 0) +/* Bits */ +#define MIIMU_SNRDY (1<<0) +#define MIIMU_PREAMBLE (1<<1) +#define MIIMU_OPMODE_WRITE (1<<2) +#define MIIMU_MDC_PERIOD (1<<3) +#define MIIMU_PHY_NRES (1<<4) +#define MIIMU_RTA (1<<5) +#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6) +#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11) +#define MIIMU_DATA(data) (((data) & 0xffff) << 16) + +/******************************* + * xmac / xpec * + *******************************/ +#define XPEC_REG(no, reg) __REG(NETX_PA_XPEC(no), (reg)) +#define XPEC_R0 0x00 +#define XPEC_R1 0x04 +#define XPEC_R2 0x08 +#define XPEC_R3 0x0c +#define XPEC_R4 0x10 +#define XPEC_R5 0x14 +#define XPEC_R6 0x18 +#define XPEC_R7 0x1c +#define XPEC_RANGE01 0x20 +#define XPEC_RANGE23 0x24 +#define XPEC_RANGE45 0x28 +#define XPEC_RANGE67 0x2c +#define XPEC_PC 0x48 +#define XPEC_TIMER(timer) (0x30 + ((timer)<<2)) +#define XPEC_IRQ 0x8c +#define XPEC_SYSTIME_NS 0x90 +#define XPEC_FIFO_DATA 0x94 +#define XPEC_SYSTIME_S 0x98 +#define XPEC_ADC 0x9c +#define XPEC_URX_COUNT 0x40 +#define XPEC_UTX_COUNT 0x44 +#define XPEC_PC 0x48 +#define XPEC_ZERO 0x4c +#define XPEC_STATCFG 0x50 +#define XPEC_EC_MASKA 0x54 +#define XPEC_EC_MASKB 0x58 +#define XPEC_EC_MASK0 0x5c +#define XPEC_EC_MASK8 0x7c +#define XPEC_EC_MASK9 0x80 +#define XPEC_XPU_HOLD_PC 0x100 +#define XPEC_RAM_START 0x2000 + +#define XPU_HOLD_PC (1<<0) + +#define XMAC_REG(no, reg) __REG(NETX_PA_XMAC(no), (reg)) +#define XMAC_RPU_PROGRAM_START 0x000 +#define XMAC_RPU_PROGRAM_END 0x3ff +#define XMAC_TPU_PROGRAM_START 0x400 +#define XMAC_TPU_PROGRAM_END 0x7ff +#define XMAC_RPU_HOLD_PC 0xa00 +#define XMAC_TPU_HOLD_PC 0xa04 + +#define RPU_HOLD_PC (1<<15) +#define TPU_HOLD_PC (1<<15) +/******************************* + * Pointer FIFO * + *******************************/ +#define PFIFO_REG(x) __REG(NETX_PA_PFIFO, (x)) +#define PFIFO_BASE(pfifo) (0x00 + ((pfifo)<<2) ) +#define PFIFO_BORDER_BASE(pfifo) (0x80 + ((pfifo)<<2) ) +#define PFIFO_RESET 0x100 +#define PFIFO_FULL 0x104 +#define PFIFO_EMPTY 0x108 +#define PFIFO_OVEFLOW 0x10c +#define PFIFO_UNDERRUN 0x110 +#define PFIFO_FILL_LEVEL(pfifo) (0x180 + ((pfifo)<<2)) + +/******************************* + * Dual Port Memory * + *******************************/ + +/* Registers */ +#define NETX_DPMAS_REG(ofs) __REG(NETX_PA_DPMAS, (ofs)) +#define NETX_DPMAS_IF_CONF0_REG NETX_DPMAS_REG(0x608) +#define NETX_DPMAS_IF_CONF1_REG NETX_DPMAS_REG(0x60c) +#define NETX_DPMAS_EXT_CONFIG0_REG NETX_DPMAS_REG(0x610) +#define NETX_DPMAS_EXT_CONFIG1_REG NETX_DPMAS_REG(0x614) +#define NETX_DPMAS_EXT_CONFIG2_REG NETX_DPMAS_REG(0x618) +#define NETX_DPMAS_EXT_CONFIG3_REG NETX_DPMAS_REG(0x61c) +#define NETX_DPMAS_IO_MODE0_REG NETX_DPMAS_REG(0x620) /* I/O 32..63 */ +#define NETX_DPMAS_DRV_EN0_REG NETX_DPMAS_REG(0x624) +#define NETX_DPMAS_DATA0_REG NETX_DPMAS_REG(0x628) +#define NETX_DPMAS_IO_MODE1_REG NETX_DPMAS_REG(0x630) /* I/O 64..84 */ +#define NETX_DPMAS_DRV_EN1_REG NETX_DPMAS_REG(0x634) +#define NETX_DPMAS_DATA1_REG NETX_DPMAS_REG(0x638) + +/* Bits */ +#define IF_CONF0_HIF_DISABLED (0<<28) +#define IF_CONF0_HIF_EXT_BUS (1<<28) +#define IF_CONF0_HIF_UP_8BIT (2<<28) +#define IF_CONF0_HIF_UP_16BIT (3<<28) +#define IF_CONF0_HIF_IO (4<<28) + +#define IO_MODE1_SAMPLE_NPOR (0<<30) +#define IO_MODE1_SAMPLE_100MHZ (1<<30) +#define IO_MODE1_SAMPLE_NPIO36 (2<<30) +#define IO_MODE1_SAMPLE_PIO36 (3<<30) + +/******************************* + * I2C * + *******************************/ +#define NETX_I2C_REG(ofs) __REG(NETX_PA_I2C, (ofs)) +#define NETX_I2C_CTRL_REG NETX_I2C_REG(0x0) +#define NETX_I2C_DATA_REG NETX_I2C_REG(0x4) + +#endif /* __ASM_ARCH_NETX_REGS_H */ diff --git a/arch/arm/mach-netx/include/mach/netx-xc.h b/arch/arm/mach-netx/include/mach/netx-xc.h new file mode 100644 index 0000000000..060a9b3b02 --- /dev/null +++ b/arch/arm/mach-netx/include/mach/netx-xc.h @@ -0,0 +1,6 @@ +#ifndef __ASM_ARCH_NETX_XC_H +#define __ASM_ARCH_NETX_XC_H + +int loadxc(int); + +#endif diff --git a/arch/arm/mach-netx/interrupts.c b/arch/arm/mach-netx/interrupts.c index d163a51fd3..af78e19bfd 100644 --- a/arch/arm/mach-netx/interrupts.c +++ b/arch/arm/mach-netx/interrupts.c @@ -1,6 +1,6 @@ #include <common.h> -#include <asm/arch/netx-regs.h> +#include <mach/netx-regs.h> int timer_init (void) { diff --git a/arch/arm/mach-netx/netx-cm.c b/arch/arm/mach-netx/netx-cm.c index 2a7ac1fb9e..58b204274a 100644 --- a/arch/arm/mach-netx/netx-cm.c +++ b/arch/arm/mach-netx/netx-cm.c @@ -1,6 +1,6 @@ #include <common.h> -#include <asm/arch/netx-regs.h> -#include <asm/arch/netx-cm.h> +#include <mach/netx-regs.h> +#include <mach/netx-cm.h> #define I2C_CTRL_ENABLE (1<<0) #define I2C_CTRL_SPEED_25 (0<<1) diff --git a/arch/arm/mach-omap/gpmc.c b/arch/arm/mach-omap/gpmc.c index 4e7383ccc0..2b9964950d 100644 --- a/arch/arm/mach-omap/gpmc.c +++ b/arch/arm/mach-omap/gpmc.c @@ -30,10 +30,10 @@ #include <common.h> #include <init.h> #include <asm/io.h> -#include <asm/arch/silicon.h> -#include <asm/arch/gpmc.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/syslib.h> +#include <mach/silicon.h> +#include <mach/gpmc.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> /** * @brief Do a Generic initialization of GPMC. if you choose otherwise, diff --git a/arch/arm/mach-omap/include/mach/clocks.h b/arch/arm/mach-omap/include/mach/clocks.h new file mode 100644 index 0000000000..1221238de8 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/clocks.h @@ -0,0 +1,48 @@ +/** + * @file + * @brief Generic Clock wrapper header. + * + * FileName: include/asm-arm/arch-omap/clocks.h + * + * This includes each of the architecture Clock definitions under it. + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __OMAP_CLOCKS_H_ +#define __OMAP_CLOCKS_H_ + +#define LDELAY 12000000 + +/* Standard defines for Various clocks */ +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#ifdef CONFIG_ARCH_OMAP3 +#include <mach/omap3-clock.h> +#endif + +#endif /* __OMAP_CLOCKS_H_ */ diff --git a/arch/arm/mach-omap/include/mach/control.h b/arch/arm/mach-omap/include/mach/control.h new file mode 100644 index 0000000000..7c1614cc24 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/control.h @@ -0,0 +1,98 @@ +/** + * @file + * @brief This file contains the Control register defines + * + * FileName: include/asm-arm/arch-omap/control.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_CONTROL_H +#define __ASM_ARCH_OMAP_CONTROL_H + +/** + * Control register defintion which unwraps to the real register + * offset + base address + */ +#define CONTROL_REG(REGNAME) (OMAP_CTRL_BASE + CONTROL_##REGNAME) + +#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) +#define CONTROL_SCALABLE_OMAP_OCP (0x534) +#define CONTROL_SCRATCHPAD_BASE (0x910) +#define CONTROL_SCRATCHPAD_ROM_BASE (0x860) +#define CONTROL_STATUS (0x2f0) +#define CONTROL_SYSCONFIG (0x010) +#define CONTROL_DEVCONF0 (0x274) +#define CONTROL_DEVCONF1 (0x2D8) +#define CONTROL_IVA2_BOOTMOD (0x404) +#define CONTROL_IVA2_BOOTADDR (0x400) +#define CONTROL_PBIAS_1 (0x520) +#define CONTROL_GENERAL_PURPOSE_STATUS (0x2F4) +#define CONTROL_MEM_DFTRW0 (0x278) +#define CONTROL_MEM_DFTRW1 (0x27C) +#define CONTROL_MSUSPENDMUX_0 (0x290) +#define CONTROL_MSUSPENDMUX_1 (0x294) +#define CONTROL_MSUSPENDMUX_2 (0x298) +#define CONTROL_MSUSPENDMUX_3 (0x29C) +#define CONTROL_MSUSPENDMUX_4 (0x2A0) +#define CONTROL_MSUSPENDMUX_5 (0x2A4) +#define CONTROL_SEC_CTRL (0x2B0) +#define CONTROL_CSIRXFE (0x2DC) +#define CONTROL_DEBOBS_0 (0x420) +#define CONTROL_DEBOBS_1 (0x424) +#define CONTROL_DEBOBS_2 (0x428) +#define CONTROL_DEBOBS_3 (0x42C) +#define CONTROL_DEBOBS_4 (0x430) +#define CONTROL_DEBOBS_5 (0x434) +#define CONTROL_DEBOBS_6 (0x438) +#define CONTROL_DEBOBS_7 (0x43C) +#define CONTROL_DEBOBS_8 (0x440) +#define CONTROL_PROG_IO0 (0x444) +#define CONTROL_PROG_IO1 (0x448) +#define CONTROL_DSS_DPLL_SPREADING (0x450) +#define CONTROL_CORE_DPLL_SPREADING (0x454) +#define CONTROL_PER_DPLL_SPREADING (0x458) +#define CONTROL_USBHOST_DPLL_SPREADING (0x45C) +#define CONTROL_TEMP_SENSOR (0x524) +#define CONTROL_SRAMLDO4 (0x528) +#define CONTROL_SRAMLDO5 (0x52C) +#define CONTROL_CSI (0x530) +#define CONTROL_SCALABLE_OMAP_OCP (0x534) +#define CONTROL_SCALABLE_OMAP_STATUS (0x44C) + +/** Provide the Regoffset, Value */ +#define MUX_VAL(OFFSET,VALUE)\ + writew((VALUE), OMAP_CTRL_BASE + (OFFSET)) + +/** + * macro for Padconfig Registers @see + * include/mach-arm/arch-omap/omap3-mux.h + */ +#define CP(X) (CONTROL_PADCONF_##X) + +#endif /* __ASM_ARCH_OMAP_CONTROL_H */ diff --git a/arch/arm/mach-omap/include/mach/gpmc.h b/arch/arm/mach-omap/include/mach/gpmc.h new file mode 100644 index 0000000000..a658cf00e7 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/gpmc.h @@ -0,0 +1,161 @@ +/** + * @file + * @brief This file contains the GPMC's generic definitions + * + * FileName: include/asm-arm/arch-omap/gpmc.h + * + * OMAP's General Purpose Memory Controller(GPMC) provides features + * allowing us to communicate with memory devices such as NOR, NAND, + * OneNAND, SRAM etc.. This file defines certain generic parameters + * allowing us to configure the same painlessly. + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_GPMC_H +#define __ASM_ARCH_OMAP_GPMC_H + +/** GPMC Reg Wrapper */ +#define GPMC_REG(REGNAME) (OMAP_GPMC_BASE + GPMC_##REGNAME) + +#define GPMC_SYS_CONFIG (0x10) +#define GPMC_SYS_STATUS (0x14) +#define GPMC_IRQSTATUS (0x18) +#define GPMC_IRQ_ENABLE (0x1C) +#define GPMC_TIMEOUT_CONTROL (0x40) +#define GPMC_CFG (0x50) +#define GPMC_STATUS (0x54) +#define GPMC_PREFETCH_CONFIG_1 (0x1E0) +#define GPMC_PREFETCH_CONFIG_2 (0x1E4) +#define GPMC_PREFETCH_CTRL (0x1EC) +#define GPMC_ECC_CONFIG (0x1F4) +#define GPMC_ECC_CONTROL (0x1F8) +#define GPMC_ECC_SIZE_CONFIG (0x1FC) +#define GPMC_ECC1_RESULT (0x200) +#define GPMC_ECC2_RESULT (0x204) +#define GPMC_ECC3_RESULT (0x208) +#define GPMC_ECC4_RESULT (0x20C) +#define GPMC_ECC5_RESULT (0x210) +#define GPMC_ECC6_RESULT (0x214) +#define GPMC_ECC7_RESULT (0x218) +#define GPMC_ECC8_RESULT (0x21C) +#define GPMC_ECC9_RESULT (0x220) + +#define GPMC_CONFIG1_0 (0x60) +#define GPMC_CONFIG1_1 (0x90) +#define GPMC_CONFIG1_2 (0xC0) +#define GPMC_CONFIG1_3 (0xF0) +#define GPMC_CONFIG1_4 (0x120) +#define GPMC_CONFIG1_5 (0x150) +#define GPMC_CONFIG1_6 (0x180) +#define GPMC_CONFIG1_7 (0x1B0) +#define GPMC_CONFIG2_0 (0x64) +#define GPMC_CONFIG2_1 (0x94) +#define GPMC_CONFIG2_2 (0xC4) +#define GPMC_CONFIG2_3 (0xF4) +#define GPMC_CONFIG2_4 (0x124) +#define GPMC_CONFIG2_5 (0x154) +#define GPMC_CONFIG2_6 (0x184) +#define GPMC_CONFIG2_7 (0x1B4) +#define GPMC_CONFIG3_0 (0x68) +#define GPMC_CONFIG3_1 (0x98) +#define GPMC_CONFIG3_2 (0xC8) +#define GPMC_CONFIG3_3 (0xF8) +#define GPMC_CONFIG3_4 (0x128) +#define GPMC_CONFIG3_5 (0x158) +#define GPMC_CONFIG3_6 (0x188) +#define GPMC_CONFIG3_7 (0x1B8) +#define GPMC_CONFIG4_0 (0x6C) +#define GPMC_CONFIG4_1 (0x9C) +#define GPMC_CONFIG4_2 (0xCC) +#define GPMC_CONFIG4_3 (0xFC) +#define GPMC_CONFIG4_4 (0x12C) +#define GPMC_CONFIG4_5 (0x15C) +#define GPMC_CONFIG4_6 (0x18C) +#define GPMC_CONFIG4_7 (0x1BC) +#define GPMC_CONFIG5_0 (0x70) +#define GPMC_CONFIG5_1 (0xA0) +#define GPMC_CONFIG5_2 (0xD0) +#define GPMC_CONFIG5_3 (0x100) +#define GPMC_CONFIG5_4 (0x130) +#define GPMC_CONFIG5_5 (0x160) +#define GPMC_CONFIG5_6 (0x190) +#define GPMC_CONFIG5_7 (0x1C0) +#define GPMC_CONFIG6_0 (0x74) +#define GPMC_CONFIG6_1 (0xA4) +#define GPMC_CONFIG6_2 (0xD4) +#define GPMC_CONFIG6_3 (0x104) +#define GPMC_CONFIG6_4 (0x134) +#define GPMC_CONFIG6_5 (0x164) +#define GPMC_CONFIG6_6 (0x194) +#define GPMC_CONFIG6_7 (0x1C4) +#define GPMC_CONFIG7_0 (0x78) +#define GPMC_CONFIG7_1 (0xA8) +#define GPMC_CONFIG7_2 (0xD8) +#define GPMC_CONFIG7_3 (0x108) +#define GPMC_CONFIG7_4 (0x138) +#define GPMC_CONFIG7_5 (0x168) +#define GPMC_CONFIG7_6 (0x198) +#define GPMC_CONFIG7_7 (0x1C8) + +#define GPMC_NUM_CS 8 +#define GPMC_CONFIG_CS_SIZE (GPMC_CONFIG1_1 - GPMC_CONFIG1_0) +#define GPMC_CONFIG_REG_OFF (GPMC_CONFIG2_0 - GPMC_CONFIG1_0) + +#define GPMC_CS_NAND_COMMAND (0x1C) +#define GPMC_CS_NAND_ADDRESS (0x20) +#define GPMC_CS_NAND_DATA (0x24) + +#define GPMC_SIZE_128M 0x08 +#define GPMC_SIZE_64M 0x0C +#define GPMC_SIZE_32M 0x0E +#define GPMC_SIZE_16M 0x0F + +#define NAND_WP_BIT 0x00000010 + +#ifndef __ASSEMBLY__ + +/** Generic GPMC configuration structure to be used to configure a + * chip select + */ +struct gpmc_config { + unsigned int cfg[6]; + unsigned int base; + unsigned char size; +}; + +/** Generic configuration - will reset all the cs configs. */ +void gpmc_generic_init(unsigned int cfg); + +/** Configuration for a specific chip select */ +void gpmc_cs_config(char cs, struct gpmc_config *config); + +#endif + +#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/mach-omap/include/mach/gpmc_nand.h b/arch/arm/mach-omap/include/mach/gpmc_nand.h new file mode 100644 index 0000000000..c6c51d5d52 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/gpmc_nand.h @@ -0,0 +1,121 @@ +/** + * @file + * @brief This file contains exported structure for NAND + * + * FileName: include/asm-arm/arch-omap/gpmc_nand.h + * + * OMAP's General Purpose Memory Controller (GPMC) has a NAND controller + * embedded. this file provides the platform data structure required to + * hook on to it. + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.3.tar.gz + * include/asm-arm/arch-omap/nand.h + * + * Copyright (C) 2006 Micron Technology Inc. + * Author: Shahrom Sharif-Kashani + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_OMAP_NAND_GPMC_H +#define __ASM_OMAP_NAND_GPMC_H + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> + +/** omap nand platform data structure */ +struct gpmc_nand_platform_data { + /** Chip select you want to use */ + int cs; + struct mtd_partition *parts; + int nr_parts; + /** If there are any special setups you'd want to do */ + int (*nand_setup) (struct gpmc_nand_platform_data *); + + /** set up if we want H/w ECC here and other + * platform specific configs here + */ + unsigned short plat_options; + /** setup any special options */ + unsigned int options; + /** set up device access as 8,16 as per GPMC config */ + char device_width; + /** Set this to WAITx+1, so GPMC WAIT0 will be 1 and so on. */ + char wait_mon_pin; + /** Set this to the max timeout for the device */ + uint64_t max_timeout; + + /* if you like a custom oob use this. */ + struct nand_ecclayout *oob; + /** platform specific private data */ + void *priv; +}; + +/** Platform specific options definitions */ +/** plat_options: Wait montioring pin low */ +#define NAND_WAITPOL_LOW (0 << 0) +/** plat_options: Wait montioring pin high */ +#define NAND_WAITPOL_HIGH (1 << 0) +#define NAND_WAITPOL_MASK (1 << 0) + +#ifdef CONFIG_NAND_OMAP_GPMC_HWECC +/** plat_options: hw ecc enabled */ +#define NAND_HWECC_ENABLE (1 << 1) +#endif +/** plat_options: hw ecc disabled */ +#define NAND_HWECC_DISABLE (0 << 1) +#define NAND_HWECC_MASK (1 << 1) + +/* Typical BOOTROM oob layouts-requires hwecc **/ +#ifdef CONFIG_NAND_OMAP_GPMC_HWECC +/** Large Page x8 NAND device Layout */ +#define GPMC_NAND_ECC_LP_x8_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ + 9, 10, 11, 12},\ + .oobfree = {\ + {.offset = 60,\ + .length = 2 } } \ +} + +/** Large Page x16 NAND device Layout */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13},\ + .oobfree = {\ + {.offset = 60,\ + .length = 2 } } \ +} + +/** Small Page x8 NAND device Layout */ +#define GPMC_NAND_ECC_SP_x8_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {1, 2, 3},\ + .oobfree = {\ + {.offset = 14,\ + .length = 2 } } \ +} + +/** Small Page x16 NAND device Layout */ +#define GPMC_NAND_ECC_SP_x16_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {2, 3, 4},\ + .oobfree = {\ + {.offset = 14,\ + .length = 2 } } \ +} + +#endif /* CONFIG_NAND_OMAP_GPMC_HWECC */ + +#endif /* __ASM_OMAP_NAND_GPMC_H */ diff --git a/arch/arm/mach-omap/include/mach/intc.h b/arch/arm/mach-omap/include/mach/intc.h new file mode 100644 index 0000000000..48fcf3d1d6 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/intc.h @@ -0,0 +1,58 @@ +/** + * @file + * @brief This file contains the Interrupt controller register defines + * + * FileName: include/asm-arm/arch-omap/intc.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_INTC_H +#define __ASM_ARCH_OMAP_INTC_H + +/** Interrupt Controller Register wrapper */ +#define INTC_REG(REGNAME) (OMAP_INTC_BASE + INTC_##REGNAME) + +#define INTC_MIR_0 (0x084) +#define INTC_MIR_1 (0x0A4) +#define INTC_MIR_2 (0x0C4) +#define INTC_MIR_SET_0 (0x08C) +#define INTC_MIR_SET_1 (0x0AC) +#define INTC_MIR_SET_2 (0x0CC) +#define INTC_MIR_CLEAR_0 (0x094) +#define INTC_MIR_CLEAR_1 (0x0B4) +#define INTC_MIR_CLEAR_2 (0x0D4) +#define INTC_PS_SYSCONFIG (0x010) +#define INTC_PS_PROTECTION (0x04C) +#define INTC_PS_IDLE (0x050) +#define INTC_PS_THRESHOLD (0x068) +#define INTC_PS_PENDING_IRQ0 (0x098) +#define INTC_PS_PENDING_IRQ1 (0x0B8) +#define INTC_PS_PENDING_IRQ2 (0x0D8) + +#endif /* __ASM_ARCH_OMAP_INTC_H */ diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h new file mode 100644 index 0000000000..22694f2367 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/omap3-clock.h @@ -0,0 +1,124 @@ +/** + * @file + * @brief Contains the PRM and CM definitions + * + * FileName: include/asm-arm/arch-omap/omap3-clock.h + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + * + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _OMAP343X_CLOCKS_H_ +#define _OMAP343X_CLOCKS_H_ + +/** CM Clock Regs Wrapper */ +#define CM_REG(REGNAME) (OMAP_CM_BASE + CM_##REGNAME) + +#define CM_FCLKEN_IVA2 0X0000 +#define CM_CLKEN_PLL_IVA2 0X0004 +#define CM_IDLEST_PLL_IVA2 0X0024 +#define CM_CLKSEL1_PLL_IVA2 0X0040 +#define CM_CLKSEL2_PLL_IVA2 0X0044 +#define CM_CLKEN_PLL_MPU 0X0904 +#define CM_IDLEST_PLL_MPU 0X0924 +#define CM_CLKSEL1_PLL_MPU 0X0940 +#define CM_CLKSEL2_PLL_MPU 0X0944 +#define CM_FCLKEN1_CORE 0X0A00 +#define CM_ICLKEN1_CORE 0X0A10 +#define CM_ICLKEN2_CORE 0X0A14 +#define CM_CLKSEL_CORE 0X0A40 +#define CM_FCLKEN_GFX 0X0B00 +#define CM_ICLKEN_GFX 0X0B10 +#define CM_CLKSEL_GFX 0X0B40 +#define CM_FCLKEN_WKUP 0X0C00 +#define CM_ICLKEN_WKUP 0X0C10 +#define CM_CLKSEL_WKUP 0X0C40 +#define CM_IDLEST_WKUP 0X0C20 +#define CM_CLKEN_PLL 0X0D00 +#define CM_IDLEST_CKGEN 0X0D20 +#define CM_CLKSEL1_PLL 0X0D40 +#define CM_CLKSEL2_PLL 0X0D44 +#define CM_CLKSEL3_PLL 0X0D48 +#define CM_FCLKEN_DSS 0X0E00 +#define CM_ICLKEN_DSS 0X0E10 +#define CM_CLKSEL_DSS 0X0E40 +#define CM_FCLKEN_CAM 0X0F00 +#define CM_ICLKEN_CAM 0X0F10 +#define CM_CLKSEL_CAM 0X0f40 +#define CM_FCLKEN_PER 0X1000 +#define CM_ICLKEN_PER 0X1010 +#define CM_CLKSEL_PER 0X1040 +#define CM_CLKSEL1_EMU 0X1140 + +/** PRM Clock Regs */ +#define PRM_REG(REGNAME) (OMAP_PRM_BASE + PRM_##REGNAME) +#define PRM_CLKSEL 0x0D40 +#define PRM_RSTCTRL 0x1250 +#define PRM_CLKSRC_CTRL 0x1270 + +/*************** Clock Values */ +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* The following configurations are OPP and SysClk value independant + * and hence are defined here. + */ + +/* CORE DPLL */ +#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +#define CORE_FUSB_DIV 2 /* 41.5MHz: */ +#define CORE_L4_DIV 2 /* 83MHz : L4 */ +#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +#define PER_M4X2 9 /* 96MHz : CM_CLKSEL_DSS-dss1 */ +#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50)) + +#define MAX_SIL_INDEX 1 + +#ifndef __ASSEMBLY__ +void prcm_init(void); +/* Used to index into DPLL parameter tables -See TRM for further details */ +struct dpll_param { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +}; +/* External functions see omap3_clock_core.S */ +extern struct dpll_param *get_mpu_dpll_param(void); +extern struct dpll_param *get_iva_dpll_param(void); +extern struct dpll_param *get_core_dpll_param(void); +extern struct dpll_param *get_per_dpll_param(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* endif _OMAP343X_CLOCKS_H_ */ diff --git a/arch/arm/mach-omap/include/mach/omap3-mux.h b/arch/arm/mach-omap/include/mach/omap3-mux.h new file mode 100644 index 0000000000..2badc3f851 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/omap3-mux.h @@ -0,0 +1,423 @@ +/** + * @file + * @brief Mux Configuration Register defines for OMAP3 + * + * FileName: include/asm-arm/arch-omap/omap3-mux.h + * + * This file defines the various Pin Mux registers + * @see include/asm-arm/arch-omap/control.h + * The @ref MUX_VAL macro uses the defines from this file + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_ARCH_OMAP3_MUX_H_ +#define _ASM_ARCH_OMAP3_MUX_H_ + +/** + * Pin Mux Enable Defines + * + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0-7 - Mode 0-7 + * + * @see MUX_VAL + */ +#define IEN (1 << 8) + +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +/* + * To get the actual address the offset has to added + * with OMAP_CTRL_BASE to get the actual address + */ + +/* SDRC */ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +/* GPMC */ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_NCS0 0x00AE +#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_NCS6 0x00BA +#define CONTROL_PADCONF_GPMC_NCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_NOE 0x00C2 +#define CONTROL_PADCONF_GPMC_NWE 0x00C4 +#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_NWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/* DSS */ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +/* CAMERA */ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/* Audio Interface */ +#define CONTROL_PADCONF_MCBSP2_FSX 0x013C +#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E +#define CONTROL_PADCONF_MCBSP2_DR 0x0140 +#define CONTROL_PADCONF_MCBSP2_DX 0x0142 +#define CONTROL_PADCONF_ +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/* WirelesS LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/* Bluetooth */ +#define CONTROL_PADCONF_MCBSP3_DX 0x016C +#define CONTROL_PADCONF_MCBSP3_DR 0x016E +#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/* Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_MCBSP4_DR 0x0186 +#define CONTROL_PADCONF_MCBSP4_DX 0x0188 +#define CONTROL_PADCONF_MCBSP4_FSX 0x018A +#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C +#define CONTROL_PADCONF_MCBSP1_FSR 0x018E +#define CONTROL_PADCONF_MCBSP1_DX 0x0190 +#define CONTROL_PADCONF_MCBSP1_DR 0x0192 +#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 +#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 +#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 +/* Serial Interface */ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE +#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC +#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE +/* Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA +/* Die to die */ +#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 +#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 +#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 +#define CONTROL_PADCONF_D2D_MCAD3 0x01EA +#define CONTROL_PADCONF_D2D_MCAD4 0x01EC +#define CONTROL_PADCONF_D2D_MCAD5 0x01EE +#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 +#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 +#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 +#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 +#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 +#define CONTROL_PADCONF_D2D_MCAD11 0x01FA +#define CONTROL_PADCONF_D2D_MCAD12 0x01FC +#define CONTROL_PADCONF_D2D_MCAD13 0x01FE +#define CONTROL_PADCONF_D2D_MCAD14 0x0200 +#define CONTROL_PADCONF_D2D_MCAD15 0x0202 +#define CONTROL_PADCONF_D2D_MCAD16 0x0204 +#define CONTROL_PADCONF_D2D_MCAD17 0x0206 +#define CONTROL_PADCONF_D2D_MCAD18 0x0208 +#define CONTROL_PADCONF_D2D_MCAD19 0x020A +#define CONTROL_PADCONF_D2D_MCAD20 0x020C +#define CONTROL_PADCONF_D2D_MCAD21 0x020E +#define CONTROL_PADCONF_D2D_MCAD22 0x0210 +#define CONTROL_PADCONF_D2D_MCAD23 0x0212 +#define CONTROL_PADCONF_D2D_MCAD24 0x0214 +#define CONTROL_PADCONF_D2D_MCAD25 0x0216 +#define CONTROL_PADCONF_D2D_MCAD26 0x0218 +#define CONTROL_PADCONF_D2D_MCAD27 0x021A +#define CONTROL_PADCONF_D2D_MCAD28 0x021C +#define CONTROL_PADCONF_D2D_MCAD29 0x021E +#define CONTROL_PADCONF_D2D_MCAD30 0x0220 +#define CONTROL_PADCONF_D2D_MCAD31 0x0222 +#define CONTROL_PADCONF_D2D_MCAD32 0x0224 +#define CONTROL_PADCONF_D2D_MCAD33 0x0226 +#define CONTROL_PADCONF_D2D_MCAD34 0x0228 +#define CONTROL_PADCONF_D2D_MCAD35 0x022A +#define CONTROL_PADCONF_D2D_MCAD36 0x022C +#define CONTROL_PADCONF_D2D_CLK26MI 0x022E +#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 +#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 +#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 +#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 +#define CONTROL_PADCONF_D2D_SPINT 0x0238 +#define CONTROL_PADCONF_D2D_FRINT 0x023A +#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C +#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E +#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 +#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 +#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 +#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 +#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 +#define CONTROL_PADCONF_D2D_N3GTMS 0x024A +#define CONTROL_PADCONF_D2D_N3GTCK 0x024C +#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E +#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 +#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C +#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 +#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 +#define CONTROL_PADCONF_D2D_MWRITE 0x0256 +#define CONTROL_PADCONF_D2D_SWRITE 0x0258 +#define CONTROL_PADCONF_D2D_MREAD 0x025A +#define CONTROL_PADCONF_D2D_SREAD 0x025C +#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E +#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 +#define CONTROL_PADCONF_SDRC_CKE0 0x0262 +#define CONTROL_PADCONF_SDRC_CKE1 0x0264 + +#endif /* _ASM_ARCH_OMAP3_MUX_H_ */ diff --git a/arch/arm/mach-omap/include/mach/omap3-silicon.h b/arch/arm/mach-omap/include/mach/omap3-silicon.h new file mode 100644 index 0000000000..dde241272f --- /dev/null +++ b/arch/arm/mach-omap/include/mach/omap3-silicon.h @@ -0,0 +1,130 @@ +/** + * @file + * @brief This file contains the processor specific definitions of + * the TI OMAP34XX. For more info on OMAP34XX, + * See http://focus.ti.com/pdfs/wtbu/swpu114g.pdf + * + * FileName: include/asm-arm/arch-omap/omap3-silicon.h + * + * OMAP34XX base address defines go here. + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap3-silicon.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP3_H +#define __ASM_ARCH_OMAP3_H + +/* PLEASE PLACE ONLY BASE DEFINES HERE */ + +/** OMAP Internal Bus Base addresses */ +#define OMAP_L4_CORE_BASE 0x48000000 +#define OMAP_INTC_BASE 0x48200000 +#define OMAP_L4_WKUP_BASE 0x48300000 +#define OMAP_L4_PER_BASE 0x49000000 +#define OMAP_L4_EMU_BASE 0x54000000 +#define OMAP_SGX_BASE 0x50000000 +#define OMAP_IVA_BASE 0x5C000000 +#define OMAP_SMX_APE_BASE 0x68000000 +#define OMAP_SMS_BASE 0x6C000000 +#define OMAP_SDRC_BASE 0x6D000000 +#define OMAP_GPMC_BASE 0x6E000000 + +/** Peripheral Base Addresses */ +#define OMAP_CTRL_BASE (OMAP_L4_CORE_BASE + 0x02000) +#define OMAP_CM_BASE (OMAP_L4_CORE_BASE + 0x04000) +#define OMAP_PRM_BASE (OMAP_L4_WKUP_BASE + 0x06000) + +#define OMAP_UART1_BASE (OMAP_L4_CORE_BASE + 0x6A000) +#define OMAP_UART2_BASE (OMAP_L4_CORE_BASE + 0x6C000) +#define OMAP_UART3_BASE (OMAP_L4_PER_BASE + 0x20000) + +#define OMAP_I2C1_BASE (OMAP_L4_CORE_BASE + 0x70000) +#define OMAP_I2C2_BASE (OMAP_L4_CORE_BASE + 0x72000) +#define OMAP_I2C3_BASE (OMAP_L4_CORE_BASE + 0x60000) + +#define OMAP_GPTIMER1_BASE (OMAP_L4_WKUP_BASE + 0x18000) +#define OMAP_GPTIMER2_BASE (OMAP_L4_PER_BASE + 0x32000) +#define OMAP_GPTIMER3_BASE (OMAP_L4_PER_BASE + 0x34000) +#define OMAP_GPTIMER4_BASE (OMAP_L4_PER_BASE + 0x36000) +#define OMAP_GPTIMER5_BASE (OMAP_L4_PER_BASE + 0x38000) +#define OMAP_GPTIMER6_BASE (OMAP_L4_PER_BASE + 0x3A000) +#define OMAP_GPTIMER7_BASE (OMAP_L4_PER_BASE + 0x3C000) +#define OMAP_GPTIMER8_BASE (OMAP_L4_PER_BASE + 0x3E000) +#define OMAP_GPTIMER9_BASE (OMAP_L4_PER_BASE + 0x40000) +#define OMAP_GPTIMER10_BASE (OMAP_L4_CORE_BASE + 0x86000) +#define OMAP_GPTIMER11_BASE (OMAP_L4_CORE_BASE + 0x88000) + +#define OMAP_WDTIMER2_BASE (OMAP_L4_WKUP_BASE + 0x14000) +#define OMAP_WDTIMER3_BASE (OMAP_L4_PER_BASE + 0x30000) + +#define OMAP_32KTIMER_BASE (OMAP_L4_WKUP_BASE + 0x20000) + +#define OMAP_MMC1_BASE (OMAP_L4_CORE_BASE + 0x9C000) +#define OMAP_MMC2_BASE (OMAP_L4_CORE_BASE + 0xB4000) +#define OMAP_MMC3_BASE (OMAP_L4_CORE_BASE + 0xAD000) + +#define OMAP_MUSB0_BASE (OMAP_L4_CORE_BASE + 0xAB000) + +#define OMAP_GPIO1_BASE (OMAP_L4_WKUP_BASE + 0x10000) +#define OMAP_GPIO2_BASE (OMAP_L4_PER_BASE + 0x50000) +#define OMAP_GPIO3_BASE (OMAP_L4_PER_BASE + 0x52000) +#define OMAP_GPIO4_BASE (OMAP_L4_PER_BASE + 0x54000) +#define OMAP_GPIO5_BASE (OMAP_L4_PER_BASE + 0x56000) +#define OMAP_GPIO6_BASE (OMAP_L4_PER_BASE + 0x58000) + +/** MPU WDT Definition */ +#define OMAP_MPU_WDTIMER_BASE OMAP_WDTIMER2_BASE + +/** Interrupt Vector base address */ +#define OMAP_SRAM_INTVECT 0x4020F800 +#define OMAP_SRAM_INTVECT_COPYSIZE 0x64 +/** Temporary stack for us to use C calls in low_level_init */ +#define OMAP_SRAM_STACK 0x4020FFFC + +/** Gives the silicon revision */ +#define OMAP_TAP_BASE (OMAP_L4_WKUP_BASE + 0xA000) +#define IDCODE_REG (OMAP_TAP_BASE + 0x204) + +/************ Generic Chip specific Definitions **********/ +/** + * CHIP F number HAWKEYE (hex) + * OMAP3430 ES1.0 F771609 B6D6 + * OMAP3430 ES2.0 F771609A B7AE + */ +#define HAWKEYE_ES1 0x0B6D6000 +#define HAWKEYE_ES2 0x0B7AE000 +#define HAWKEYE_ES2_1 0x1B7AE000 +#define HAWKEYE_MASK 0x0FFFF000 +#define VERSION_MASK 0xF0000000 +#define DEVICE_MASK ((0x1 << 8)|(0x1 << 9)|(0x1 << 10)) + +#define OMAP_SDRC_CS0 0x80000000 +#define OMAP_SDRC_CS1 0xA0000000 + +#endif /* __ASM_ARCH_OMAP3_H */ + diff --git a/arch/arm/mach-omap/include/mach/omap3-smx.h b/arch/arm/mach-omap/include/mach/omap3-smx.h new file mode 100644 index 0000000000..78cff95f5b --- /dev/null +++ b/arch/arm/mach-omap/include/mach/omap3-smx.h @@ -0,0 +1,69 @@ +/** + * @file + * @brief This file contains the SMX specific register definitions + * + * FileName: include/asm-arm/arch-omap/omap3-smx.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * include/asm-arm/arch-omap/omap34xx.h + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_OMAP_SMX_H +#define __ASM_ARCH_OMAP_SMX_H + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12800) +#define PM_OCM_ROM_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x12C00) +#define PM_IVA2_BASE_ADDR_ARM (OMAP_SMX_APE_BASE + 0x14000) + +#define RT_REQ_INFO_PERMISSION_1 (PM_RT_APE_BASE_ADDR_ARM + 0x68) +#define RT_READ_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x50) +#define RT_WRITE_PERMISSION_0 (PM_RT_APE_BASE_ADDR_ARM + 0x58) +#define RT_ADDR_MATCH_1 (PM_RT_APE_BASE_ADDR_ARM + 0x60) + +#define GPMC_REQ_INFO_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x48) +#define GPMC_READ_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x50) +#define GPMC_WRITE_PERMISSION_0 (PM_GPMC_BASE_ADDR_ARM + 0x58) + +#define OCM_REQ_INFO_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x48) +#define OCM_READ_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x50) +#define OCM_WRITE_PERMISSION_0 (PM_OCM_RAM_BASE_ADDR_ARM + 0x58) +#define OCM_ADDR_MATCH_2 (PM_OCM_RAM_BASE_ADDR_ARM + 0x80) + +/* IVA2 */ +#define IVA2_REQ_INFO_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x48) +#define IVA2_READ_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x50) +#define IVA2_WRITE_PERMISSION_0 (PM_IVA2_BASE_ADDR_ARM + 0x58) + +/* SMS */ +#define SMS_SYSCONFIG (OMAP_SMS_BASE + 0x10) +#define SMS_RG_ATT0 (OMAP_SMS_BASE + 0x48) +#define SMS_CLASS_ARB0 (OMAP_SMS_BASE + 0xD0) +#define BURSTCOMPLETE_GROUP7 (0x1 << 31) + +#endif /* __ASM_ARCH_OMAP_SMX_H */ diff --git a/arch/arm/mach-omap/include/mach/sdrc.h b/arch/arm/mach-omap/include/mach/sdrc.h new file mode 100644 index 0000000000..9d2d2d1107 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/sdrc.h @@ -0,0 +1,97 @@ +/** + * @file + * @brief This file contains the SDRC specific register definitions + * + * FileName: include/asm-arm/arch-omap/sdrc.h + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_ARCH_SDRC_H +#define _ASM_ARCH_SDRC_H + +#define SDRC_REG(REGNAME) (OMAP_SDRC_BASE + OMAP_SDRC_##REGNAME) +#define OMAP_SDRC_SYSCONFIG (0x10) +#define OMAP_SDRC_STATUS (0x14) +#define OMAP_SDRC_CS_CFG (0x40) +#define OMAP_SDRC_SHARING (0x44) +#define OMAP_SDRC_DLLA_CTRL (0x60) +#define OMAP_SDRC_DLLA_STATUS (0x64) +#define OMAP_SDRC_DLLB_CTRL (0x68) +#define OMAP_SDRC_DLLB_STATUS (0x6C) +#define DLLPHASE (0x1 << 1) +#define LOADDLL (0x1 << 2) +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK ((0x1 << 8)|(0x1 << 9)) + +#define OMAP_SDRC_POWER (0x70) +#define WAKEUPPROC (0x1 << 26) + +#define OMAP_SDRC_MCFG_0 (0x80) +#define OMAP_SDRC_MCFG_1 (0xB0) +#define OMAP_SDRC_MR_0 (0x84) +#define OMAP_SDRC_MR_1 (0xB4) +#define OMAP_SDRC_ACTIM_CTRLA_0 (0x9C) +#define OMAP_SDRC_ACTIM_CTRLB_0 (0xA0) +#define OMAP_SDRC_ACTIM_CTRLA_1 (0xC4) +#define OMAP_SDRC_ACTIM_CTRLB_1 (0xC8) +#define OMAP_SDRC_RFR_CTRL_0 (0xA4) +#define OMAP_SDRC_RFR_CTRL_1 (0xD4) +#define OMAP_SDRC_MANUAL_0 (0xA8) +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET (0x1 << 1) +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +#define SDRC_CS0_OSET 0x0 +/* Mirror CS1 regs appear offset 0x30 from CS0 */ +#define SDRC_CS1_OSET 0x30 + +#define SDRC_STACKED 0 +#define SDRC_IP_DDR 1 +#define SDRC_COMBO_DDR 2 +#define SDRC_IP_SDR 3 + + +#define SDRC_B_R_C (0 << 6) /* bank-row-column */ +#define SDRC_B1_R_B0_C (1 << 6) /* bank1-row-bank0-column */ +#define SDRC_R_B_C (2 << 6) /* row-bank-column */ + +#define DLL_OFFSET 0 +#define DLL_WRITEDDRCLKX2DIS 1 +#define DLL_ENADLL 1 +#define DLL_LOCKDLL 0 +#define DLL_DLLPHASE_72 0 +#define DLL_DLLPHASE_90 1 + +#endif /* _ASM_ARCH_SDRC_H */ diff --git a/arch/arm/mach-omap/include/mach/silicon.h b/arch/arm/mach-omap/include/mach/silicon.h new file mode 100644 index 0000000000..22daa5c964 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/silicon.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_SILICON_H +#define __ASM_ARCH_OMAP_SILICON_H + +/* Each platform silicon header comes here */ +#ifdef CONFIG_ARCH_OMAP3 +#include <mach/omap3-silicon.h> +#endif + +/* If Architecture specific init functions are present */ +#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT +#ifndef __ASSEMBLY__ +void a_init(void); +#endif /* __ASSEMBLY__ */ +#endif + +#endif /* __ASM_ARCH_OMAP_SILICON_H */ diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h new file mode 100644 index 0000000000..43967209f1 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/sys_info.h @@ -0,0 +1,97 @@ +/** + * @file + * @brief This file defines the macros apis which are useful for most OMAP + * platforms. + * + * FileName: include/asm-arm/arch-omap/sys_info.h + * + * These are implemented by the System specific code in omapX-generic.c + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_SYS_INFO_H_ +#define __ASM_ARCH_SYS_INFO_H_ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module*/ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 +#define CPU_2430 0x2430 +#define CPU_2420 0x2420 +#define CPU_1710 0x1710 +#define CPU_1610 0x1610 + +/** + * CPU revision + */ +#define CPU_ES1 1 +#define CPU_ES1P1 2 +#define CPU_ES1P2 3 +#define CPU_ES2 4 +#define CPU_ES2P1 5 +#define CPU_ES2P2 6 +#define CPU_ES3 7 +#define CPU_ES3P1 8 +#define CPU_ES3P2 9 +#define CPU_ES4 10 +#define CPU_ES4P1 11 +#define CPU_ES4P2 12 + +#define GPMC_MUXED 1 +#define GPMC_NONMUXED 0 + +#define TYPE_NAND 0x800 /* bit pos for nand in gpmc reg */ +#define TYPE_NOR 0x000 +#define TYPE_ONENAND 0x800 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/** These are implemented by the System specific code in omapX-generic.c */ +u32 get_cpu_type(void); +u32 get_cpu_rev(void); +u32 get_sdr_cs_size(u32 offset); +inline u32 get_sysboot_value(void); +u32 get_gpmc0_base(void); +u32 get_base(void); +u32 running_in_flash(void); +u32 running_in_sram(void); +u32 running_in_sdram(void); +u32 get_boot_type(void); +u32 get_device_type(void); + +#endif /*__ASM_ARCH_SYS_INFO_H_ */ diff --git a/arch/arm/mach-omap/include/mach/syslib.h b/arch/arm/mach-omap/include/mach/syslib.h new file mode 100644 index 0000000000..c89f50b816 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/syslib.h @@ -0,0 +1,43 @@ +/** + * @file + * @brief These Apis are OMAP independent support functions + * + * FileName: include/asm-arm/arch-omap/syslib.h + * + * Implemented by arch/arm/mach-omap/syslib.c + * + * Originally from http://linux.omap.com/pub/bootloader/3430sdp/u-boot-v1.tar.gz + */ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_SYSLIB_H_ +#define __ASM_ARCH_OMAP_SYSLIB_H_ + +/** System Independent functions */ +void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound); +void sdelay(unsigned long loops); + +/** All architectures need to implement these */ +void omap_uart_write(unsigned int val, unsigned long base, + unsigned char reg_idx); +unsigned int omap_uart_read(unsigned long base, unsigned char reg_idx); +#endif /* __ASM_ARCH_OMAP_SYSLIB_H_ */ diff --git a/arch/arm/mach-omap/include/mach/timers.h b/arch/arm/mach-omap/include/mach/timers.h new file mode 100644 index 0000000000..a93824378c --- /dev/null +++ b/arch/arm/mach-omap/include/mach/timers.h @@ -0,0 +1,60 @@ +/** + * @file + * @brief This defines the Register defines for OMAP GPTimers and Sync32 timers. + * + * FileName: include/asm-arm/arch-omap/timers.h + * + * Originally from Linux kernel: + * http://linux.omap.com/pub/kernel/3430zoom/linux-ldp-v1.0b.tar.gz + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * Copyright (C) 2007 Texas Instruments, <www.ti.com> + * Copyright (C) 2007 Nokia Corporation. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_GPT_H +#define __ASM_ARCH_GPT_H + +/** General Purpose timer regs offsets (32 bit regs) */ +#define TIDR 0x0 /* r */ +#define TIOCP_CFG 0x10 /* rw */ +#define TISTAT 0x14 /* r */ +#define TISR 0x18 /* rw */ +#define TIER 0x1C /* rw */ +#define TWER 0x20 /* rw */ +#define TCLR 0x24 /* rw */ +#define TCRR 0x28 /* rw */ +#define TLDR 0x2C /* rw */ +#define TTGR 0x30 /* rw */ +#define TWPS 0x34 /* r */ +#define TMAR 0x38 /* rw */ +#define TCAR1 0x3c /* r */ +#define TSICR 0x40 /* rw */ +#define TCAR2 0x44 /* r */ +/* Enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/** Sync 32Khz Timer registers */ +#define S32K_CR (OMAP_32KTIMER_BASE + 0x10) +#define S32K_FREQUENCY 32768 + +#endif /*__ASM_ARCH_GPT_H */ diff --git a/arch/arm/mach-omap/include/mach/wdt.h b/arch/arm/mach-omap/include/mach/wdt.h new file mode 100644 index 0000000000..532252d080 --- /dev/null +++ b/arch/arm/mach-omap/include/mach/wdt.h @@ -0,0 +1,49 @@ +/** + * @file + * @brief This file contains the Watchdog timer specific register definitions + * + * FileName: include/asm-arm/arch-omap/wdt.h + * + */ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Nishanth Menon <x0nishan@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_WDT_H +#define __ASM_ARCH_OMAP_WDT_H + +/** Watchdog Register defines */ +#define WDT_REG(REGNAME) (OMAP_MPU_WDTIMER_BASE + OMAP_WDT_##REGNAME) +#define OMAP_WDT_WIDR (0x000) +#define OMAP_WDT_SYSCONFIG (0x010) +#define OMAP_WDT_WD_SYSSTATUS (0x014) +#define OMAP_WDT_WISR (0x018) +#define OMAP_WDT_WIER (0x01C) +#define OMAP_WDT_WCLR (0x024) +#define OMAP_WDT_WCRR (0x028) +#define OMAP_WDT_WLDR (0x02C) +#define OMAP_WDT_WTGR (0x030) +#define OMAP_WDT_WWPS (0x034) +#define OMAP_WDT_WSPR (0x048) + +/* Unlock Code for Watchdog timer to disable the same */ +#define WDT_DISABLE_CODE1 0xAAAA +#define WDT_DISABLE_CODE2 0x5555 + +#endif /* __ASM_ARCH_OMAP_WDT_H */ diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c index ce26cb5fac..4e81ae80d4 100644 --- a/arch/arm/mach-omap/omap3_clock.c +++ b/arch/arm/mach-omap/omap3_clock.c @@ -40,11 +40,11 @@ #include <common.h> #include <asm/io.h> -#include <asm/arch/silicon.h> -#include <asm/arch/clocks.h> -#include <asm/arch/timers.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/syslib.h> +#include <mach/silicon.h> +#include <mach/clocks.h> +#include <mach/timers.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> /* Following functions are exported from omap3_clock_core.S */ #ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM diff --git a/arch/arm/mach-omap/omap3_clock_core.S b/arch/arm/mach-omap/omap3_clock_core.S index 6e10563fb4..872ae5abcd 100644 --- a/arch/arm/mach-omap/omap3_clock_core.S +++ b/arch/arm/mach-omap/omap3_clock_core.S @@ -37,9 +37,9 @@ */ #include <config.h> -#include <asm/arch/silicon.h> -#include <asm/arch/clocks.h> -#include <asm/arch/gpmc.h> +#include <mach/silicon.h> +#include <mach/clocks.h> +#include <mach/gpmc.h> #ifdef CONFIG_OMAP3_COPY_CLOCK_SRAM /** diff --git a/arch/arm/mach-omap/omap3_core.S b/arch/arm/mach-omap/omap3_core.S index dece199fae..76f80e68ca 100644 --- a/arch/arm/mach-omap/omap3_core.S +++ b/arch/arm/mach-omap/omap3_core.S @@ -37,9 +37,9 @@ */ #include <config.h> -#include <asm/arch/silicon.h> -#include <asm/arch/wdt.h> -#include <asm/arch/clocks.h> +#include <mach/silicon.h> +#include <mach/wdt.h> +#include <mach/clocks.h> #ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT .globl arch_init_lowlevel diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c index 3acf911251..794d2fa8f2 100644 --- a/arch/arm/mach-omap/omap3_generic.c +++ b/arch/arm/mach-omap/omap3_generic.c @@ -37,15 +37,15 @@ #include <common.h> #include <init.h> #include <asm/io.h> -#include <asm/arch/silicon.h> -#include <asm/arch/gpmc.h> -#include <asm/arch/sdrc.h> -#include <asm/arch/control.h> -#include <asm/arch/omap3-smx.h> -#include <asm/arch/clocks.h> -#include <asm/arch/wdt.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/syslib.h> +#include <mach/silicon.h> +#include <mach/gpmc.h> +#include <mach/sdrc.h> +#include <mach/control.h> +#include <mach/omap3-smx.h> +#include <mach/clocks.h> +#include <mach/wdt.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> /** * @brief Reset the CPU diff --git a/arch/arm/mach-omap/s32k_clksource.c b/arch/arm/mach-omap/s32k_clksource.c index 4166d83d75..353670c583 100644 --- a/arch/arm/mach-omap/s32k_clksource.c +++ b/arch/arm/mach-omap/s32k_clksource.c @@ -34,11 +34,11 @@ #include <clock.h> #include <init.h> #include <asm/io.h> -#include <asm/arch/silicon.h> -#include <asm/arch/clocks.h> -#include <asm/arch/timers.h> -#include <asm/arch/sys_info.h> -#include <asm/arch/syslib.h> +#include <mach/silicon.h> +#include <mach/clocks.h> +#include <mach/timers.h> +#include <mach/sys_info.h> +#include <mach/syslib.h> /** * @brief Provide a simple clock read diff --git a/arch/arm/mach-omap/syslib.c b/arch/arm/mach-omap/syslib.c index 0ca4ef21d3..51824dadb0 100644 --- a/arch/arm/mach-omap/syslib.c +++ b/arch/arm/mach-omap/syslib.c @@ -32,7 +32,7 @@ #include <config.h> #include <asm/io.h> -#include <asm/arch/syslib.h> +#include <mach/syslib.h> /** * @brief simple spin loop diff --git a/arch/arm/mach-s3c24xx/generic.c b/arch/arm/mach-s3c24xx/generic.c index 864977d7b8..f58cf95058 100644 --- a/arch/arm/mach-s3c24xx/generic.c +++ b/arch/arm/mach-s3c24xx/generic.c @@ -27,7 +27,7 @@ #include <init.h> #include <clock.h> #include <asm/io.h> -#include <asm/arch/s3c24x0-iomap.h> +#include <mach/s3c24x0-iomap.h> /** * Calculate the current M-PLL clock. diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h new file mode 100644 index 0000000000..ab3dc4f20a --- /dev/null +++ b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-iomap.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2009 Juergen Beisert, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* S3C2410 device base addresses */ +#define S3C24X0_SDRAM_BASE 0x30000000 +#define S3C24X0_SDRAM_END 0x40000000 +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C2410_USB_HOST_BASE 0x49000000 +#define S3C2410_INTERRUPT_BASE 0x4A000000 +#define S3C2410_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C2410_LCD_BASE 0x4D000000 +#define S3C24X0_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C2410_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C2410_I2C_BASE 0x54000000 +#define S3C2410_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C2410_RTC_BASE 0x57000000 +#define S3C2410_ADC_BASE 0x58000000 +#define S3C2410_SPI_BASE 0x59000000 +#define S3C2410_SDI_BASE 0x5A000000 + +/* Clock control (direct access) */ + +#define LOCKTIME (S3C24X0_CLOCK_POWER_BASE) +#define MPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x4) +#define UPLLCON (S3C24X0_CLOCK_POWER_BASE + 0x8) +#define CLKCON (S3C24X0_CLOCK_POWER_BASE + 0xc) +#define CLKSLOW (S3C24X0_CLOCK_POWER_BASE + 0x10) +#define CLKDIVN (S3C24X0_CLOCK_POWER_BASE + 0x14) + +/* Timer (direct access) */ +#define TCFG0 (S3C24X0_TIMER_BASE + 0x00) +#define TCFG1 (S3C24X0_TIMER_BASE + 0x04) +#define TCON (S3C24X0_TIMER_BASE + 0x08) +#define TCNTB0 (S3C24X0_TIMER_BASE + 0x0c) +#define TCMPB0 (S3C24X0_TIMER_BASE + 0x10) +#define TCNTO0 (S3C24X0_TIMER_BASE + 0x14) +#define TCNTB1 (S3C24X0_TIMER_BASE + 0x18) +#define TCMPB1 (S3C24X0_TIMER_BASE + 0x1c) +#define TCNTO1 (S3C24X0_TIMER_BASE + 0x20) +#define TCNTB2 (S3C24X0_TIMER_BASE + 0x24) +#define TCMPB2 (S3C24X0_TIMER_BASE + 0x28) +#define TCNTO2 (S3C24X0_TIMER_BASE + 0x2c) +#define TCNTB3 (S3C24X0_TIMER_BASE + 0x30) +#define TCMPB3 (S3C24X0_TIMER_BASE + 0x34) +#define TCNTO3 (S3C24X0_TIMER_BASE + 0x38) +#define TCNTB4 (S3C24X0_TIMER_BASE + 0x3c) +#define TCNTO4 (S3C24X0_TIMER_BASE + 0x40) + +/* Watchdog (direct access) */ +#define WTCON (S3C24X0_WATCHDOG_BASE) +#define WTDAT (S3C24X0_WATCHDOG_BASE + 0x04) +#define WTCNT (S3C24X0_WATCHDOG_BASE + 0x08) + +/* + * if we are booting from NAND, its internal SRAM occures at + * a different address than without this feature + */ +#ifdef CONFIG_S3C24XX_NAND_BOOT +# define NFC_RAM_AREA 0x00000000 +#else +# define NFC_RAM_AREA 0x40000000 +#endif +#define NFC_RAM_SIZE 4096 + +/* internal UARTs (driver based) */ +#define UART1_BASE (S3C24X0_UART_BASE) +#define UART1_SIZE 0x4000 +#define UART2_BASE (S3C24X0_UART_BASE + 0x4000) +#define UART3_SIZE 0x4000 +#define UART3_BASE (S3C24X0_UART_BASE + 0x8000) +#define UART3_SIZE 0x4000 + +/* CS configuration (direct access) */ +#define BWSCON (S3C24X0_MEMCTL_BASE) +#define BANKCON0 (S3C24X0_MEMCTL_BASE + 0x04) +#define BANKCON1 (S3C24X0_MEMCTL_BASE + 0x08) +#define BANKCON2 (S3C24X0_MEMCTL_BASE + 0x0c) +#define BANKCON3 (S3C24X0_MEMCTL_BASE + 0x10) +#define BANKCON4 (S3C24X0_MEMCTL_BASE + 0x14) +#define BANKCON5 (S3C24X0_MEMCTL_BASE + 0x18) +#define BANKCON6 (S3C24X0_MEMCTL_BASE + 0x1c) +#define BANKCON7 (S3C24X0_MEMCTL_BASE + 0x20) +#define REFRESH (S3C24X0_MEMCTL_BASE + 0x24) +#define BANKSIZE (S3C24X0_MEMCTL_BASE + 0x28) +#define MRSRB6 (S3C24X0_MEMCTL_BASE + 0x2c) +#define MRSRB7 (S3C24X0_MEMCTL_BASE + 0x30) + +/* GPIO registers (direct access) */ +#define GPACON (S3C24X0_GPIO_BASE) +#define GPADAT (S3C24X0_GPIO_BASE + 0x04) + +#define GPBCON (S3C24X0_GPIO_BASE + 0x10) +#define GPBDAT (S3C24X0_GPIO_BASE + 0x14) +#define GPBUP (S3C24X0_GPIO_BASE + 0x18) + +#define GPCCON (S3C24X0_GPIO_BASE + 0x20) +#define GPCDAT (S3C24X0_GPIO_BASE + 0x24) +#define GPCUP (S3C24X0_GPIO_BASE + 0x28) + +#define GPDCON (S3C24X0_GPIO_BASE + 0x30) +#define GPDDAT (S3C24X0_GPIO_BASE + 0x34) +#define GPDUP (S3C24X0_GPIO_BASE + 0x38) + +#define GPECON (S3C24X0_GPIO_BASE + 0x40) +#define GPEDAT (S3C24X0_GPIO_BASE + 0x44) +#define GPEUP (S3C24X0_GPIO_BASE + 0x48) + +#define GPFCON (S3C24X0_GPIO_BASE + 0x50) +#define GPFDAT (S3C24X0_GPIO_BASE + 0x54) +#define GPFUP (S3C24X0_GPIO_BASE + 0x58) + +#define GPGCON (S3C24X0_GPIO_BASE + 0x60) +#define GPGDAT (S3C24X0_GPIO_BASE + 0x64) +#define GPGUP (S3C24X0_GPIO_BASE + 0x68) + +#define GPHCON (S3C24X0_GPIO_BASE + 0x70) +#define GPHDAT (S3C24X0_GPIO_BASE + 0x74) +#define GPHUP (S3C24X0_GPIO_BASE + 0x78) + +#ifdef CONFIG_CPU_S3C2440 +# define GPJCON (S3C24X0_GPIO_BASE + 0xd0) +# define GPJDAT (S3C24X0_GPIO_BASE + 0xd4) +# define GPJUP (S3C24X0_GPIO_BASE + 0xd8) +#endif + +#define MISCCR (S3C24X0_GPIO_BASE + 0x80) +#define DCLKCON (S3C24X0_GPIO_BASE + 0x84) +#define EXTINT0 (S3C24X0_GPIO_BASE + 0x88) +#define EXTINT1 (S3C24X0_GPIO_BASE + 0x8c) +#define EXTINT2 (S3C24X0_GPIO_BASE + 0x90) +#define EINTFLT0 (S3C24X0_GPIO_BASE + 0x94) +#define EINTFLT1 (S3C24X0_GPIO_BASE + 0x98) +#define EINTFLT2 (S3C24X0_GPIO_BASE + 0x9c) +#define EINTFLT3 (S3C24X0_GPIO_BASE + 0xa0) +#define EINTMASK (S3C24X0_GPIO_BASE + 0xa4) +#define EINTPEND (S3C24X0_GPIO_BASE + 0xa8) +#define GSTATUS0 (S3C24X0_GPIO_BASE + 0xac) +#define GSTATUS1 (S3C24X0_GPIO_BASE + 0xb0) +#define GSTATUS2 (S3C24X0_GPIO_BASE + 0xb4) +#define GSTATUS3 (S3C24X0_GPIO_BASE + 0xb8) +#define GSTATUS4 (S3C24X0_GPIO_BASE + 0xbc) + +#ifdef CONFIG_CPU_S3C2440 +# define DSC0 (S3C24X0_GPIO_BASE + 0xc4) +# define DSC1 (S3C24X0_GPIO_BASE + 0xc8) +#endif + +/* external IO space */ +#define CS0_BASE 0x00000000 +#define CS1_BASE 0x08000000 +#define CS2_BASE 0x10000000 +#define CS3_BASE 0x18000000 +#define CS4_BASE 0x20000000 +#define CS5_BASE 0x28000000 +#define CS6_BASE 0x30000000 diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h new file mode 100644 index 0000000000..05f9cf0fd1 --- /dev/null +++ b/arch/arm/mach-s3c24xx/include/mach/s3c24x0-nand.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2009 Juergen Beisert, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifdef CONFIG_S3C24XX_NAND_BOOT +extern void s3c24x0_nand_load_image(void*, int, int, int); +#endif + +/** + * Locate the timing bits for the NFCONF register + * @param setup is the TACLS clock count + * @param access is the TWRPH0 clock count + * @param hold is the TWRPH1 clock count + * + * @note A clock count of 0 means always 1 HCLK clock. + * @note Clock count settings depend on the NAND flash requirements and the current HCLK speed + */ +#ifdef CONFIG_CPU_S3C2410 +# define CALC_NFCONF_TIMING(setup, access, hold) \ + ((setup << 8) + (access << 4) + (hold << 0)) +#endif +#ifdef CONFIG_CPU_S3C2440 +# define CALC_NFCONF_TIMING(setup, access, hold) \ + ((setup << 12) + (access << 8) + (hold << 4)) +#endif + +/** + * Define platform specific data for the NAND controller and its device + */ +struct s3c24x0_nand_platform_data { + uint32_t nand_timing; /**< value for the NFCONF register (timing bits only) */ +}; + +/** + * @file + * @brief Basic declaration to use the s3c24x0 NAND driver + */ diff --git a/arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h b/arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h new file mode 100644 index 0000000000..1691138279 --- /dev/null +++ b/arch/arm/mach-s3c24xx/include/mach/s3c24xx-generic.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2009 + * Juergen Beisert, Pengutronix + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +uint32_t s3c24xx_get_mpllclk(void); +uint32_t s3c24xx_get_upllclk(void); +uint32_t s3c24xx_get_fclk(void); +uint32_t s3c24xx_get_hclk(void); +uint32_t s3c24xx_get_pclk(void); +uint32_t s3c24xx_get_uclk(void); diff --git a/arch/arm/mach-s3c24xx/lowlevel-init.S b/arch/arm/mach-s3c24xx/lowlevel-init.S index d27cfa5dfb..fd6b0f396d 100644 --- a/arch/arm/mach-s3c24xx/lowlevel-init.S +++ b/arch/arm/mach-s3c24xx/lowlevel-init.S @@ -19,7 +19,7 @@ */ #include <config.h> -#include <asm/arch/s3c24x0-iomap.h> +#include <mach/s3c24x0-iomap.h> .section ".text_bare_init.s3c24x0_disable_wd","ax" |