diff options
| author | Jan Luebbe <jlu@pengutronix.de> | 2013-04-17 19:12:49 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-04-19 07:25:46 +0200 |
| commit | f838be333ebd6132d4204eba4deae3e5c4c9a713 (patch) | |
| tree | 62ec724ac15291f60fac4470d5531a413e6a043c /arch | |
| parent | a6fda1886a40ecf89573ec53c3abae87fe59bba7 (diff) | |
| download | barebox-f838be333ebd6132d4204eba4deae3e5c4c9a713.tar.gz barebox-f838be333ebd6132d4204eba4deae3e5c4c9a713.tar.xz | |
am33xx: add defines for GPIOs
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap/include/mach/am33xx-clock.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap/include/mach/am33xx-silicon.h | 6 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h index 39c107f9c7..cbee6415e2 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-clock.h +++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h @@ -139,7 +139,9 @@ #define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x14) /* Ethernet */ #define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144)/* Ethernet */ #define CM_PER_OCMCRAM_CLKCTRL (CM_PER + 0x2C) /* OCMC RAM */ +#define CM_PER_GPIO1_CLKCTRL (CM_PER + 0xAC) /* GPIO1 */ #define CM_PER_GPIO2_CLKCTRL (CM_PER + 0xB0) /* GPIO2 */ +#define CM_PER_GPIO3_CLKCTRL (CM_PER + 0xB4) /* GPIO3 */ #define CM_PER_UART3_CLKCTRL (CM_PER + 0x74) /* UART3 */ #define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */ #define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */ diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h index e69d345b07..9edf4ca977 100644 --- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h +++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h @@ -29,6 +29,12 @@ #define AM33XX_UART1_BASE (AM33XX_L4_PER_BASE + 0x22000) #define AM33XX_UART2_BASE (AM33XX_L4_PER_BASE + 0x24000) +/* GPIO */ +#define AM33XX_GPIO0_BASE (AM33XX_L4_WKUP_BASE + 0x207000 + 0x100) +#define AM33XX_GPIO1_BASE (AM33XX_L4_PER_BASE + 0x4C000 + 0x100) +#define AM33XX_GPIO2_BASE (AM33XX_L4_PER_BASE + 0x1AC000 + 0x100) +#define AM33XX_GPIO3_BASE (AM33XX_L4_PER_BASE + 0x1AE000 + 0x100) + /* EMFI Registers */ #define AM33XX_EMFI0_BASE 0x4C000000 |