diff options
| author | Uwe Kleine-König <u.kleine-koenig@pengutronix.de> | 2017-07-24 11:15:59 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2017-07-30 16:09:49 +0200 |
| commit | 2295ee6ce800fa429030b8837ee6914d7994c3d3 (patch) | |
| tree | d769ec57defb2ffe3177c76b3e9cc55c58404d6c /arch | |
| parent | c0fcf4dde3c96546cd52641ace0d0a1cff800c59 (diff) | |
| download | barebox-2295ee6ce800fa429030b8837ee6914d7994c3d3.tar.gz barebox-2295ee6ce800fa429030b8837ee6914d7994c3d3.tar.xz | |
ARM: use register defines in the dcd table of the WaRP7
This was generated with the following command after adding the include
directive to the file:
scripts/regsubst.pl -I arch/arm/mach-imx/include arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg | 102 |
1 files changed, 52 insertions, 50 deletions
diff --git a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg index a3389218d5..d54b3ea851 100644 --- a/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg +++ b/arch/arm/boards/element14-warp7/flash-header-mx7-warp.imxcfg @@ -13,69 +13,71 @@ soc imx7 loadaddr 0x80000000 dcdofs 0x400 +#include <mach/imx7-ddr-regs.h> + wm 32 0x30340004 0x4F400005 wm 32 0x30391000 0x00000002 -wm 32 0x307a0000 0x03040008 -wm 32 0x307a0064 0x00200038 -wm 32 0x307a0490 0x00000001 -wm 32 0x307a00d0 0x00350001 -wm 32 0x307a00dc 0x00c3000a -wm 32 0x307a00e0 0x00010000 -wm 32 0x307a00e4 0x00110006 -wm 32 0x307a00f4 0x0000033f -wm 32 0x307a0100 0x0a0e110b -wm 32 0x307a0104 0x00020211 -wm 32 0x307a0108 0x03060708 -wm 32 0x307a010c 0x00a0500c -wm 32 0x307a0110 0x05020307 -wm 32 0x307a0114 0x02020404 -wm 32 0x307a0118 0x02020003 -wm 32 0x307a011c 0x00000202 -wm 32 0x307a0120 0x00000202 +wm 32 MX7_DDRC_MSTR 0x03040008 +wm 32 MX7_DDRC_RFSHTMG 0x00200038 +wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001 +wm 32 MX7_DDRC_INIT0 0x00350001 +wm 32 MX7_DDRC_INIT3 0x00c3000a +wm 32 MX7_DDRC_INIT4 0x00010000 +wm 32 MX7_DDRC_INIT5 0x00110006 +wm 32 MX7_DDRC_RANKCTL 0x0000033f +wm 32 MX7_DDRC_DRAMTMG0 0x0a0e110b +wm 32 MX7_DDRC_DRAMTMG1 0x00020211 +wm 32 MX7_DDRC_DRAMTMG2 0x03060708 +wm 32 MX7_DDRC_DRAMTMG3 0x00a0500c +wm 32 MX7_DDRC_DRAMTMG4 0x05020307 +wm 32 MX7_DDRC_DRAMTMG5 0x02020404 +wm 32 MX7_DDRC_DRAMTMG6 0x02020003 +wm 32 MX7_DDRC_DRAMTMG7 0x00000202 +wm 32 MX7_DDRC_DRAMTMG8 0x00000202 -wm 32 0x307a0180 0x00600018 -wm 32 0x307a0184 0x00e00100 -wm 32 0x307a0190 0x02098205 -wm 32 0x307a0194 0x00060303 -wm 32 0x307a01a0 0x80400003 -wm 32 0x307a01a4 0x00100020 -wm 32 0x307a01a8 0x80100004 +wm 32 MX7_DDRC_ZQCTL0 0x00600018 +wm 32 MX7_DDRC_ZQCTL1 0x00e00100 +wm 32 MX7_DDRC_DFITMG0 0x02098205 +wm 32 MX7_DDRC_DFITMG1 0x00060303 +wm 32 MX7_DDRC_DFIUPD0 0x80400003 +wm 32 MX7_DDRC_DFIUPD1 0x00100020 +wm 32 MX7_DDRC_DFIUPD2 0x80100004 -wm 32 0x307a0200 0x00000015 -wm 32 0x307a0204 0x00161616 -wm 32 0x307a0210 0x00000f0f -wm 32 0x307a0214 0x04040404 -wm 32 0x307a0218 0x0f0f0404 +wm 32 MX7_DDRC_ADDRMAP0 0x00000015 +wm 32 MX7_DDRC_ADDRMAP1 0x00161616 +wm 32 MX7_DDRC_ADDRMAP4 0x00000f0f +wm 32 MX7_DDRC_ADDRMAP5 0x04040404 +wm 32 MX7_DDRC_ADDRMAP6 0x0f0f0404 -wm 32 0x307a0240 0x06000600 -wm 32 0x307a0244 0x00000000 +wm 32 MX7_DDRC_ODTCFG 0x06000600 +wm 32 MX7_DDRC_ODTMAP 0x00000000 wm 32 0x30391000 0x00000000 -wm 32 0x30790000 0x17421e40 -wm 32 0x30790004 0x10210100 -wm 32 0x30790008 0x00010000 -wm 32 0x30790010 0x0007080c -wm 32 0x307900b0 0x1010007e +wm 32 MX7_DDR_PHY_PHY_CON0 0x17421e40 +wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100 +wm 32 MX7_DDR_PHY_PHY_CON2 0x00010000 +wm 32 MX7_DDR_PHY_PHY_CON4 0x0007080c +wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e -wm 32 0x3079001C 0x01010000 -wm 32 0x3079009c 0x00000d6e +wm 32 MX7_DDR_PHY_RODT_CON0 0x01010000 +wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e -wm 32 0x30790030 0x06060606 -wm 32 0x30790020 0x0a0a0a0a -wm 32 0x30790050 0x01000008 -wm 32 0x30790050 0x00000008 -wm 32 0x30790018 0x0000000f -wm 32 0x307900c0 0x0e487304 -wm 32 0x307900c0 0x0e4c7304 -wm 32 0x307900c0 0x0e4c7306 -wm 32 0x307900c0 0x0e4c7304 +wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x06060606 +wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x0a0a0a0a +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000008 +wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000008 +wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e487304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7306 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e4c7304 -check 32 while_any_bit_clear 0x307900c4 0x1 +check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1 -wm 32 0x307900c0 0x0e487304 +wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e487304 wm 32 0x30384130 0x00000000 wm 32 0x30340020 0x00000178 wm 32 0x30384130 0x00000002 -check 32 while_any_bit_clear 0x307a0004 0x1 +check 32 while_any_bit_clear MX7_DDRC_STAT 0x1 |