Merge branch 'for-next/omap'

10 files changed, 253 insertions, 18 deletions

diff --git a/arch/arm/boards/phytec-som-am335x/Kconfig b/arch/arm/boards/phytec-som-am335x/Kconfig
new file mode 100644
index 0000000000..52fa723a21
--- /dev/null
+++ b/arch/arm/boards/phytec-som-am335x/Kconfig
@@ -0,0 +1,13 @@
+
+if MACH_PHYTEC_SOM_AM335X
+
+config PHYTEC_SOM_AM335X_OF_AUTOENABLE
+	bool
+	prompt "Autoenable of components"
+	help
+	  Say Y to unlock an API for automatically enable either hardware
+	  components with existing device drivers or i2c clients. All functions
+	  take a device tree path to find the hardware and will fix up the node
+	  status in the kernel device tree, if it's accessible.
+
+endif
diff --git a/arch/arm/boards/phytec-som-am335x/board.c b/arch/arm/boards/phytec-som-am335x/board.c
index dc3b84a806..0e9bf5fdef 100644
--- a/arch/arm/boards/phytec-som-am335x/board.c
+++ b/arch/arm/boards/phytec-som-am335x/board.c
@@ -21,10 +21,12 @@
 #include <bootsource.h>
 #include <common.h>
 #include <nand.h>
+#include <net.h>
 #include <init.h>
 #include <io.h>
 #include <linux/sizes.h>
 #include <envfs.h>
+#include <state.h>
 #include <asm/armlinux.h>
 #include <generated/mach-types.h>
 #include <linux/phy.h>
@@ -65,8 +67,16 @@ static char *nandslots[] = {
 	"/dev/nand0.barebox_backup.bb",
 };
 
+#define ETH_COUNT 2
+static const char *eth_names[ETH_COUNT] = {"mac0", "mac1"};
+
 static int physom_devices_init(void)
 {
+	struct state *state;
+	u8 mac[6];
+	int state_ret;
+	int state_i;
+
 	if (!of_machine_is_compatible("phytec,am335x-som"))
 		return 0;
 
@@ -114,6 +124,30 @@ static int physom_devices_init(void)
 				ARRAY_SIZE(nandslots));
 	am33xx_bbu_emmc_mlo_register_handler("MLO.emmc", "/dev/mmc1");
 
+	if (IS_ENABLED(CONFIG_STATE)) {
+		state = state_by_name("am335x_phytec_mac_state");
+		if (state)
+			for (state_i = 0; state_i < 2; state_i++) {
+				state_ret = state_read_mac(state,
+						      eth_names[state_i], &mac[0]);
+				if (state_ret == 6)
+					eth_register_ethaddr(state_i, mac);
+			}
+	}
+
+	if (IS_ENABLED(PHYTEC_SOM_AM335X_OF_AUTOENABLE)) {
+		/* Enable NAND */
+		of_autoenable_device_by_path("/ocp/gpmc@50000000");
+		/* Enable eMMC */
+		of_autoenable_device_by_path("/ocp/mmc@481d8000");
+		/* Enable SPI NOR */
+		of_autoenable_device_by_path("/ocp/spi@48030000/m25p80@0");
+
+		of_autoenable_i2c_by_component("/ocp/i2c@44e0b000/temp@4b");
+		of_autoenable_i2c_by_component("/ocp/i2c@44e0b000/eeprom@52");
+		of_autoenable_i2c_by_component("/ocp/i2c@44e0b000/rtc@68");
+	}
+
 	if (IS_ENABLED(CONFIG_SHELL_NONE))
 		return am33xx_of_register_bootdevice();
 
diff --git a/arch/arm/boards/phytec-som-am335x/lowlevel.c b/arch/arm/boards/phytec-som-am335x/lowlevel.c
index 77f436fa8b..b1576ee21a 100644
--- a/arch/arm/boards/phytec-som-am335x/lowlevel.c
+++ b/arch/arm/boards/phytec-som-am335x/lowlevel.c
@@ -46,6 +46,94 @@ static const struct am33xx_cmd_control physom_cmd = {
 	.invert_clkout2	= 0x0,
 };
 
+/* Module family for the unified MLO
+ *
+ * NONE:        Unified MLO is not supported
+ * PHYCORE_R2:  Unified MLO for PCM-060, PCM-062
+ */
+enum {
+	NONE,
+	PHYCORE_R2,
+};
+
+/* @brief Supplies default ram timings for all ram sizes
+ *
+ * Returns generic ram timings for module families to find the correct
+ * ram size.
+ *
+ * @return struct am335x_sdram_timings* or NULL
+ */
+
+static noinline struct am335x_sdram_timings* get_minimal_timings(
+							int module_family)
+{
+	struct am335x_sdram_timings *timing;
+
+	switch (module_family) {
+	case PHYCORE_R2:
+		timing = &physom_timings[PHYCORE_R2_MT41K512M16HA125IT_1024MB];
+		break;
+	default:
+		timing = NULL;
+	}
+
+	return timing;
+}
+
+/* @brief Converts ramsizes to ram timings for phyCORE-R2 modules
+ *
+ * Returns ram timings for a given ram size or NULL, if this size is
+ * not supported.
+ *
+ * @return struct am335x_sdram_timings* or NULL
+ */
+
+static noinline struct am335x_sdram_timings* convert_phycore_r2_timings(
+								u32 ramsize)
+{
+	struct am335x_sdram_timings *timing;
+
+	switch (ramsize) {
+	case SZ_256M:
+		timing = &physom_timings[PHYCORE_R2_MT41K128M16JT_256MB];
+		break;
+	case SZ_512M:
+		timing = &physom_timings[PHYCORE_R2_MT41K256M16TW107IT_512MB];
+		break;
+	case SZ_1G:
+		timing = &physom_timings[PHYCORE_R2_MT41K512M16HA125IT_1024MB];
+		break;
+	default:
+		timing = NULL;
+	}
+
+	return timing;
+}
+
+/* @brief Converts a module family and ram size to ram timings
+ *
+ * Returns ram timings for a given ram size and module family or NULL,
+ * if the ram size or module family is not supported.
+ *
+ * @return struct am335x_sdram_timings* or NULL
+ */
+
+static noinline struct am335x_sdram_timings* get_timings_by_size(
+						int module_family, u32 ramsize)
+{
+	struct am335x_sdram_timings *timing;
+
+	switch (module_family) {
+	case PHYCORE_R2:
+		timing = convert_phycore_r2_timings(ramsize);
+		break;
+	default:
+		timing = NULL;
+	}
+
+	return timing;
+}
+
 /**
  * @brief The basic entry point for board initialization.
  *
@@ -55,9 +143,10 @@ static const struct am33xx_cmd_control physom_cmd = {
  *
  * @return void
  */
-static noinline void physom_board_init(int sdram, void *fdt)
+static noinline void physom_board_init(void *fdt, int sdram, int module_family)
 {
-	struct am335x_sdram_timings *timing = &physom_timings[sdram];
+	struct am335x_sdram_timings *timing = NULL;
+	u32 ramsize;
 
 	/*
 	 * WDT1 is already running when the bootloader gets control
@@ -71,6 +160,24 @@ static noinline void physom_board_init(int sdram, void *fdt)
 
 	am33xx_pll_init(MPUPLL_M_600, DDRPLL_M_400);
 
+	if (module_family == NONE) {
+		timing = &physom_timings[sdram];
+	} else {
+		/* Load generic DDR3 ram timings to find the ram size */
+		timing = get_minimal_timings(module_family);
+		if (!timing)
+			hang();
+		am335x_sdram_init(DDR_IOCTRL, &physom_cmd,
+				&timing->regs,
+				&timing->data);
+
+		/* Find the ram size and set up the correct ram timings */
+		ramsize = get_ram_size((long *) 0x80000000, SZ_1G);
+		timing = get_timings_by_size(module_family, ramsize);
+		if (!timing)
+			hang();
+	}
+
 	am335x_sdram_init(DDR_IOCTRL, &physom_cmd,
 			&timing->regs,
 			&timing->data);
@@ -83,7 +190,8 @@ static noinline void physom_board_init(int sdram, void *fdt)
 	am335x_barebox_entry(fdt);
 }
 
-static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void *fdt)
+static noinline void physom_board_entry(unsigned long bootinfo, int sdram,
+					void *fdt, int module_family)
 {
 	am33xx_save_bootinfo((void *)bootinfo);
 
@@ -95,26 +203,34 @@ static noinline void physom_board_entry(unsigned long bootinfo, int sdram, void
 	 */
 	relocate_to_current_adr();
 	setup_c();
-
-	physom_board_init(sdram, fdt);
+	physom_board_init(fdt, sdram, module_family);
 }
 
-#define PHYTEC_ENTRY_MLO(name, fdt_name, sdram)			\
-	ENTRY_FUNCTION(name, bootinfo, r1, r2)			\
-	{							\
+#define PHYTEC_ENTRY_UNIFIED_MLO(name, fdt_name, module_family)		\
+	ENTRY_FUNCTION(name, bootinfo, r1, r2)				\
+	{								\
+		extern char __dtb_z_##fdt_name##_start[];		\
+		void *fdt = __dtb_z_##fdt_name##_start -		\
+			get_runtime_offset();				\
+		physom_board_entry(bootinfo, 0, fdt, module_family);	\
+	}
+
+#define PHYTEC_ENTRY_MLO(name, fdt_name, sdram)				\
+	ENTRY_FUNCTION(name, bootinfo, r1, r2)				\
+	{								\
 		extern char __dtb_z_##fdt_name##_start[];		\
 		void *fdt = __dtb_z_##fdt_name##_start -		\
-			get_runtime_offset();			\
-		physom_board_entry(bootinfo, sdram, fdt);	\
+			get_runtime_offset();				\
+		physom_board_entry(bootinfo, sdram, fdt, NONE);		\
 	}
 
-#define PHYTEC_ENTRY(name, fdt_name)				\
-	ENTRY_FUNCTION(name, r0, r1, r2)			\
-	{							\
+#define PHYTEC_ENTRY(name, fdt_name)					\
+	ENTRY_FUNCTION(name, r0, r1, r2)				\
+	{								\
 		extern char __dtb_z_##fdt_name##_start[];		\
 		void *fdt = __dtb_z_##fdt_name##_start -		\
-			get_runtime_offset();			\
-		am335x_barebox_entry(fdt);			\
+			get_runtime_offset();				\
+		am335x_barebox_entry(fdt);				\
 	}
 
 /* phycore-som */
@@ -122,9 +238,7 @@ PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_128mb, am335x_phytec_phycore_s
 PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J128M16125IT_256MB);
 PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J256M16HA15EIT_512MB);
 PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_sram_2x512mb, am335x_phytec_phycore_som_mlo, PHYCORE_MT41J512M8125IT_2x512MB);
-PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_512mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K256M16TW107IT_512MB);
-PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_256mb, am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K128M16JT_256MB);
-PHYTEC_ENTRY_MLO(start_am33xx_phytec_phycore_r2_sram_1024mb,  am335x_phytec_phycore_som_mlo, PHYCORE_R2_MT41K512M16HA125IT_1024MB);
+PHYTEC_ENTRY_UNIFIED_MLO(start_am33xx_phytec_phycore_r2_sram, am335x_phytec_phycore_som_mlo, PHYCORE_R2);
 PHYTEC_ENTRY(start_am33xx_phytec_phycore_nand_sdram, am335x_phytec_phycore_som_nand);
 PHYTEC_ENTRY(start_am33xx_phytec_phycore_emmc_sdram, am335x_phytec_phycore_som_emmc);
 PHYTEC_ENTRY(start_am33xx_phytec_phycore_nand_no_spi_sdram, am335x_phytec_phycore_som_nand_no_spi);
diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/am335x_defconfig
index dd9c3c5494..5a236fbae6 100644
--- a/arch/arm/configs/am335x_defconfig
+++ b/arch/arm/configs/am335x_defconfig
@@ -88,6 +88,7 @@ CONFIG_CMD_OF_FIXUP_STATUS=y
 CONFIG_CMD_OFTREE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_MMC_EXTCSD=y
+CONFIG_CMD_STATE=y
 CONFIG_NET=y
 CONFIG_NET_NFS=y
 CONFIG_NET_NETCONSOLE=y
@@ -142,3 +143,5 @@ CONFIG_FS_FAT_LFN=y
 CONFIG_FS_UBIFS=y
 CONFIG_FS_UBIFS_COMPRESSION_LZO=y
 CONFIG_FS_UBIFS_COMPRESSION_ZLIB=y
+CONFIG_STATE=y
+CONFIG_STATE_DRV=y
diff --git a/arch/arm/dts/am335x-phytec-phycore-som-emmc.dts b/arch/arm/dts/am335x-phytec-phycore-som-emmc.dts
index 880700e3bd..f264498e52 100644
--- a/arch/arm/dts/am335x-phytec-phycore-som-emmc.dts
+++ b/arch/arm/dts/am335x-phytec-phycore-som-emmc.dts
@@ -16,6 +16,7 @@
 
 #include "am33xx.dtsi"
 #include "am335x-phytec-phycore-som.dtsi"
+#include "am335x-phytec-state.dtsi"
 
 / {
 	model = "Phytec phyCORE EMMC AM335x";
diff --git a/arch/arm/dts/am335x-phytec-phycore-som-nand-no-spi.dts b/arch/arm/dts/am335x-phytec-phycore-som-nand-no-spi.dts
index 2c2fab017a..b35294c586 100644
--- a/arch/arm/dts/am335x-phytec-phycore-som-nand-no-spi.dts
+++ b/arch/arm/dts/am335x-phytec-phycore-som-nand-no-spi.dts
@@ -9,6 +9,7 @@
 
 #include "am33xx.dtsi"
 #include "am335x-phytec-phycore-som.dtsi"
+#include "am335x-phytec-state.dtsi"
 
 / {
 	model = "Phytec phyCORE AM335x";
diff --git a/arch/arm/dts/am335x-phytec-phycore-som-nand.dts b/arch/arm/dts/am335x-phytec-phycore-som-nand.dts
index 6ff2447608..4d7606b574 100644
--- a/arch/arm/dts/am335x-phytec-phycore-som-nand.dts
+++ b/arch/arm/dts/am335x-phytec-phycore-som-nand.dts
@@ -9,6 +9,7 @@
 
 #include "am33xx.dtsi"
 #include "am335x-phytec-phycore-som.dtsi"
+#include "am335x-phytec-state.dtsi"
 
 / {
 	model = "Phytec phyCORE AM335x";
diff --git a/arch/arm/dts/am335x-phytec-phycore-som.dtsi b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
index dbc64246e5..cf2eef3014 100644
--- a/arch/arm/dts/am335x-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/am335x-phytec-phycore-som.dtsi
@@ -164,6 +164,20 @@
 		pagesize = <32>;
 		reg = <0x52>;
 	};
+
+	/* The following i2c nodes are for the autoenable */
+	i2c_tmp102: temp@4b {
+		compatible = "ti,tmp102";
+		reg = <0x4b>;
+		status = "disabled";
+	};
+
+	i2c_rtc: rtc@68 {
+		compatible = "rv4162";
+		reg = <0x68>;
+		status = "disabled";
+	};
+
 };
 
 &mmc1 {
diff --git a/arch/arm/dts/am335x-phytec-state.dtsi b/arch/arm/dts/am335x-phytec-state.dtsi
new file mode 100644
index 0000000000..fbc35b9184
--- /dev/null
+++ b/arch/arm/dts/am335x-phytec-state.dtsi
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017 PHYTEC Messtechnik GmbH,
+ * Author: Daniel Schultz <d.schultz@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/ {
+	aliases {
+		am335x_phytec_mac_state = &am335x_phytec_mac_state;
+	};
+
+	am335x_phytec_mac_state: am335x_phytec_mac_state {
+		magic = <0x3f45620e>;
+		compatible = "barebox,state";
+		backend-type = "raw";
+		backend = <&backend_state_eeprom>;
+		backend-stridesize = <40>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		mac0 {
+			reg = <0x0 0x6>;
+			type = "mac";
+		};
+		mac1 {
+			reg = <0x6 0x6>;
+			type = "mac";
+		};
+
+	};
+};
+
+&eeprom {
+	status = "okay";
+	partitions {
+		compatible = "fixed-partitions";
+		#size-cells = <1>;
+		#address-cells = <1>;
+		backend_state_eeprom: state@0 {
+			reg = <0x000 0x120>;
+			label = "state-eeprom";
+		};
+	};
+};
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 9c41741b50..e8fc4b843a 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -192,6 +192,8 @@ config MACH_VSCOM_BALTOS
 
 endif
 
+source arch/arm/boards/phytec-som-am335x/Kconfig
+
 choice
 	prompt "Select OMAP board"
 	depends on !OMAP_MULTI_BOARDS