Merge branch 'for-next/mvebu'

4 files changed, 41 insertions, 59 deletions

diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c
index fa971da11e..83aeb41ae2 100644
--- a/arch/arm/mach-mvebu/common.c
+++ b/arch/arm/mach-mvebu/common.c
@@ -37,6 +37,10 @@
 #define DOVE_SDRAM_MAP_VALID		BIT(0)
 #define DOVE_SDRAM_LENGTH_SHIFT		16
 #define DOVE_SDRAM_LENGTH_MASK		(0x00f << DOVE_SDRAM_LENGTH_SHIFT)
+#define DOVE_SDRAM_REGS_BASE_DECODE	0x10
+
+#define DOVE_CPU_CTRL			(MVEBU_REMAP_INT_REG_BASE + 0xd025c)
+#define DOVE_AXI_CTRL			(MVEBU_REMAP_INT_REG_BASE + 0xd0224)
 
 #define KIRKWOOD_SDRAM_BASE		(IOMEM(MVEBU_REMAP_INT_REG_BASE) + 0x00000)
 #define KIRKWOOD_DDR_BASE_CSn(n)	(0x1500 + ((n) * 0x8))
@@ -192,8 +196,33 @@ static void mvebu_remap_registers(void)
 
 void __naked __noreturn dove_barebox_entry(void *boarddata)
 {
+	uint32_t val;
+	void __iomem *mcbase = mvebu_get_initial_int_reg_base() + 0x800000;
+
 	mvebu_remap_registers();
 
+	/*
+	 * On dove there is an additional register window that is expected to be
+	 * located 0x800000 after the main register window. This contains the
+	 * DDR registers.
+	 */
+	val = readl(mcbase + DOVE_SDRAM_REGS_BASE_DECODE) & 0x0000ffff;
+	val |= (unsigned long)DOVE_SDRAM_BASE & 0xffff0000;
+	writel(val, mcbase + DOVE_SDRAM_REGS_BASE_DECODE);
+
+	/* tell the axi controller about where to find the DDR controller */
+	val = readl(DOVE_AXI_CTRL) & 0x007fffff;
+	val |= (unsigned long)DOVE_SDRAM_BASE & 0xff800000;
+	writel(val, DOVE_AXI_CTRL);
+
+	/*
+	 * The AXI units internal space base starts at the same address as the
+	 * DDR controller.
+	 */
+	val = readl(DOVE_CPU_CTRL) & 0xfff007ff;
+	val |= ((unsigned long)DOVE_SDRAM_BASE & 0xff800000) >> 12;
+	writel(val, DOVE_CPU_CTRL);
+
 	barebox_arm_entry(0, dove_memory_find(), boarddata);
 }
 
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 1cdb7e1b82..37fde63f18 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -22,27 +22,6 @@
 #include <linux/mbus.h>
 #include <mach/dove-regs.h>
 
-static inline void dove_remap_mc_regs(void)
-{
-	void __iomem *mcboot = IOMEM(DOVE_BOOTUP_MC_REGS);
-	uint32_t val;
-
-	/* remap ahb slave base */
-	val  = readl(DOVE_CPU_CTRL) & 0xffff0000;
-	val |= (DOVE_REMAP_MC_REGS & 0xffff0000) >> 16;
-	writel(val, DOVE_CPU_CTRL);
-
-	/* remap axi bridge address */
-	val  = readl(DOVE_AXI_CTRL) & 0x007fffff;
-	val |= DOVE_REMAP_MC_REGS & 0xff800000;
-	writel(val, DOVE_AXI_CTRL);
-
-	/* remap memory controller base address */
-	val = readl(mcboot + SDRAM_REGS_BASE_DECODE) & 0x0000ffff;
-	val |= DOVE_REMAP_MC_REGS & 0xffff0000;
-	writel(val, mcboot + SDRAM_REGS_BASE_DECODE);
-}
-
 static void __noreturn dove_restart_soc(struct restart_handler *rst)
 {
 	/* enable and assert RSTOUTn */
@@ -62,7 +41,6 @@ static int dove_init_soc(void)
 	barebox_set_model("Marvell Dove");
 	barebox_set_hostname("dove");
 
-	dove_remap_mc_regs();
 	mvebu_mbus_init();
 
 	return 0;
diff --git a/arch/arm/mach-mvebu/kwbootimage.c b/arch/arm/mach-mvebu/kwbootimage.c
index 8d364ceb7b..e379d732fe 100644
--- a/arch/arm/mach-mvebu/kwbootimage.c
+++ b/arch/arm/mach-mvebu/kwbootimage.c
@@ -10,7 +10,7 @@
 #include <asm/unaligned.h>
 #include <mach/common.h>
 
-static int do_bootm_kwbimage_v1(struct image_data *data)
+static int do_bootm_kwbimage_v0_v1(struct image_data *data)
 {
 	int fd, ret;
 	loff_t offset;
@@ -69,14 +69,21 @@ out_free:
 	return ret;
 }
 
+static struct image_handler image_handler_kwbimage_v0_handler = {
+	.name = "MVEBU kwbimage v0",
+	.bootm = do_bootm_kwbimage_v0_v1,
+	.filetype = filetype_kwbimage_v0,
+};
+
 static struct image_handler image_handler_kwbimage_v1_handler = {
 	.name = "MVEBU kwbimage v1",
-	.bootm = do_bootm_kwbimage_v1,
+	.bootm = do_bootm_kwbimage_v0_v1,
 	.filetype = filetype_kwbimage_v1,
 };
 
 static int mvebu_register_kwbimage_image_handler(void)
 {
+	register_image_handler(&image_handler_kwbimage_v0_handler);
 	register_image_handler(&image_handler_kwbimage_v1_handler);
 
 	return 0;
diff --git a/arch/arm/mach-omap/am33xx_bbu_nand.c b/arch/arm/mach-omap/am33xx_bbu_nand.c
index 7785d40f1f..6fc6e7e40f 100644
--- a/arch/arm/mach-omap/am33xx_bbu_nand.c
+++ b/arch/arm/mach-omap/am33xx_bbu_nand.c
@@ -20,6 +20,7 @@
 #include <bbu.h>
 #include <fs.h>
 #include <fcntl.h>
+#include <libfile.h>
 #include <filetype.h>
 
 struct nand_bbu_handler {
@@ -28,39 +29,6 @@ struct nand_bbu_handler {
 	int num_devicefiles;
 };
 
-static int write_image(const char *devfile, const void *image, size_t size)
-{
-	int fd = 0;
-	int ret = 0;
-
-	fd = open(devfile, O_WRONLY);
-	if (fd < 0) {
-		pr_err("could not open %s: %s\n", devfile,
-			errno_str());
-		return fd;
-	}
-
-	ret = erase(fd, ERASE_SIZE_ALL, 0);
-	if (ret < 0) {
-		pr_err("could not erase %s: %s\n", devfile,
-			errno_str());
-		close(fd);
-		return ret;
-	}
-
-	ret = write(fd, image, size);
-	if (ret < 0) {
-		pr_err("could not write to fd %s: %s\n", devfile,
-			errno_str());
-		close(fd);
-		return ret;
-	}
-
-	close(fd);
-
-	return 0;
-}
-
 /*
  * Upate given nand partitions with an image
  */
@@ -80,12 +48,12 @@ static int nand_slot_update_handler(struct bbu_handler *handler,
 
 	/* check if the devicefile has been overwritten */
 	if (strcmp(data->devicefile, nh->devicefile[0]) != 0) {
-		ret = write_image(data->devicefile, image, size);
+		ret = write_file_flash(data->devicefile, image, size);
 		if (ret != 0)
 			return ret;
 	} else {
 		for (i = 0; i < nh->num_devicefiles; i++) {
-			ret =  write_image(nh->devicefile[i], image, size);
+			ret =  write_file_flash(nh->devicefile[i], image, size);
 			if (ret != 0)
 				return ret;
 		}