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| author | Daniel Schultz <d.schultz@phytec.de> | 2019-07-10 13:17:31 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-07-11 07:15:33 +0200 |
| commit | 581a501428fcc8fc18c4e069d896d320fffeb911 (patch) | |
| tree | df1262f78e0764c69c6dbfcc4187e74efbe0f497 /arch | |
| parent | 012dae9bd1a4ff862881762c5ea5966218c43d59 (diff) | |
| download | barebox-581a501428fcc8fc18c4e069d896d320fffeb911.tar.gz barebox-581a501428fcc8fc18c4e069d896d320fffeb911.tar.xz | |
ARM: dts: imx6ul: phycore: Add state framework
Add the state framework with EEPROM backend.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/imx6ul-phytec-phycore-som.dts | 5 | ||||
| -rw-r--r-- | arch/arm/dts/imx6ul-phytec-state.dtsi | 82 | ||||
| -rw-r--r-- | arch/arm/dts/imx6ull-phytec-phycore-som.dts | 5 |
3 files changed, 92 insertions, 0 deletions
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts index 6d1876702d..11418ea7f0 100644 --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts @@ -14,6 +14,7 @@ #include <arm/imx6ul.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-state.dtsi" / { model = "Phytec phyCORE-i.MX6 Ultra Lite SOM"; @@ -32,6 +33,10 @@ status = "okay"; }; +&state { + status = "okay"; +}; + &uart1 { status = "okay"; }; diff --git a/arch/arm/dts/imx6ul-phytec-state.dtsi b/arch/arm/dts/imx6ul-phytec-state.dtsi new file mode 100644 index 0000000000..78a32ed96b --- /dev/null +++ b/arch/arm/dts/imx6ul-phytec-state.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 PHYTEC Messtechnik GmbH, + * Author: Stefan Riedmueller <s.riedmueller@phytec.de> + */ + +/ { + aliases { + state = &state; + }; + + state: imx6ul_phytec_boot_state { + magic = <0x883b86a6>; + compatible = "barebox,state"; + backend-type = "raw"; + backend = <&backend_update_eeprom>; + backend-storage-type = "direct"; + backend-stridesize = <54>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + bootstate { + #address-cells = <1>; + #size-cells = <1>; + last_chosen { + reg = <0x0 0x4>; + type = "uint32"; + }; + system0 { + #address-cells = <1>; + #size-cells = <1>; + remaining_attempts { + reg = <0x4 0x4>; + type = "uint32"; + default = <3>; + }; + priority { + reg = <0x8 0x4>; + type = "uint32"; + default = <21>; + }; + ok { + reg = <0xc 0x4>; + type = "uint32"; + default = <0>; + }; + }; + system1 { + #address-cells = <1>; + #size-cells = <1>; + remaining_attempts { + reg = <0x10 0x4>; + type = "uint32"; + default = <3>; + }; + priority { + reg = <0x14 0x4>; + type = "uint32"; + default = <20>; + }; + ok { + reg = <0x18 0x4>; + type = "uint32"; + default = <0>; + }; + }; + }; + }; +}; + +&eeprom { + partitions { + compatible = "fixed-partitions"; + #size-cells = <1>; + #address-cells = <1>; + backend_update_eeprom: state@0 { + reg = <0x0 0x100>; + label = "update-eeprom"; + }; + }; +}; diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts index 4d73010131..86f43a4632 100644 --- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts +++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts @@ -14,6 +14,7 @@ #include <arm/imx6ull.dtsi> #include "imx6ul-phytec-phycore-som.dtsi" +#include "imx6ul-phytec-state.dtsi" / { model = "Phytec phyCORE-i.MX6 ULL SOM"; @@ -32,6 +33,10 @@ status = "okay"; }; +&state { + status = "okay"; +}; + &uart1 { status = "okay"; }; |