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authorLucas Stach <l.stach@pengutronix.de>2020-11-05 15:10:14 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2020-11-09 08:44:55 +0100
commit61682b59363fca0fbf51d37ece46ec6d47ea35d4 (patch)
treea6c7caa2bee20a60072e50a6bd99e7ca743b393c /arch
parent33f25eb1908b8b3e3c56a0bb2a24376a2735833a (diff)
downloadbarebox-61682b59363fca0fbf51d37ece46ec6d47ea35d4.tar.gz
barebox-61682b59363fca0fbf51d37ece46ec6d47ea35d4.tar.xz
ddr: imx8m: clean up entry points
The DDRC address in the memory map and the TF-A parameter store address is the same for all i.MX8M* SoCs. The only difference (for now) is in the power up sequence. Add a enum for the DDRC type, so we can take different code paths in imx8m_ddr_init() depending on the SoC. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boards/nxp-imx8mp-evk/lowlevel.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
index e4f994a1d1..3298ded586 100644
--- a/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mp-evk/lowlevel.c
@@ -118,7 +118,7 @@ static void start_atf(void)
power_init_board();
- imx8mm_ddr_init(&imx8mp_evk_dram_timing);
+ imx8mp_ddr_init(&imx8mp_evk_dram_timing);
imx8mp_get_boot_source(&src, &instance);
switch (src) {