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| author | Lucas Stach <dev@lynxeye.de> | 2014-04-13 15:27:34 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2014-04-23 11:39:14 +0200 |
| commit | 0fe976103ee5b6e6c1e9f8f782e429f442450126 (patch) | |
| tree | 28274633c00a28d8ffec9d58ba41aaf548ac1b76 /arch | |
| parent | bd4cbd927cf4c90f9af904ec49bc80bb19f040b9 (diff) | |
| download | barebox-0fe976103ee5b6e6c1e9f8f782e429f442450126.tar.gz barebox-0fe976103ee5b6e6c1e9f8f782e429f442450126.tar.xz | |
tegra: source MSELECT clock from CLK_M
We need to reprogram PLL_P at a later time, so
we have to make sure MSELECT is able to operate
correctly when we stop PLL_P.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-tegra/tegra_avp_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index 3314db4572..1afea445ac 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -164,8 +164,8 @@ static void start_cpu0_clocks(void) /* init MSELECT */ writel(CRC_RST_DEV_V_MSELECT, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_V_SET); - writel((CRC_CLK_SOURCE_MSEL_SRC_PLLP << - CRC_CLK_SOURCE_MSEL_SRC_SHIFT) | 2, + writel((CRC_CLK_SOURCE_MSEL_SRC_CLKM << + CRC_CLK_SOURCE_MSEL_SRC_SHIFT), TEGRA_CLK_RESET_BASE + CRC_CLK_SOURCE_MSEL); writel(CRC_CLK_OUT_ENB_V_MSELECT, TEGRA_CLK_RESET_BASE + CRC_CLK_OUT_ENB_V); |