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author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2022-08-01 14:07:06 +0200 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2022-08-08 15:10:32 +0200 |
commit | 12ff7b84d188dca4ba2418455c504bdb268797d3 (patch) | |
tree | 6f0ae07ea68bd1e4aafd7af3a09bd27de0269c45 /arch | |
parent | 262b60ddbf4050322275b6aadebb6f1903357d42 (diff) | |
download | barebox-12ff7b84d188dca4ba2418455c504bdb268797d3.tar.gz barebox-12ff7b84d188dca4ba2418455c504bdb268797d3.tar.xz |
ARM: socfpga: achilles: guard macros with braces
Macro definitions should be guarded with braces for safer use.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Link: https://lore.barebox.org/20220801120708.2511165-6-s.trumtrar@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/boards/reflex-achilles/lowlevel.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c index 2efb9aaea0..ec8c126c2a 100644 --- a/arch/arm/boards/reflex-achilles/lowlevel.c +++ b/arch/arm/boards/reflex-achilles/lowlevel.c @@ -23,15 +23,16 @@ #define BAREBOX_PART 0 #define BITSTREAM_PART 1 #define BAREBOX1_OFFSET SZ_1M -#define BAREBOX2_OFFSET BAREBOX1_OFFSET + SZ_512K -#define BAREBOX3_OFFSET BAREBOX2_OFFSET + SZ_512K -#define BAREBOX4_OFFSET BAREBOX3_OFFSET + SZ_512K +#define BAREBOX2_OFFSET (BAREBOX1_OFFSET + SZ_512K) +#define BAREBOX3_OFFSET (BAREBOX2_OFFSET + SZ_512K) +#define BAREBOX4_OFFSET (BAREBOX3_OFFSET + SZ_512K) +// Offset from the start of the second partition on the eMMC. #define BITSTREAM1_OFFSET 0x0 -#define BITSTREAM2_OFFSET BITSTREAM1_OFFSET + SZ_32M +#define BITSTREAM2_OFFSET (BITSTREAM1_OFFSET + SZ_32M) extern char __dtb_z_socfpga_arria10_achilles_start[]; -#define ARRIA10_STACKTOP ARRIA10_OCRAM_ADDR + SZ_256K +#define ARRIA10_STACKTOP (ARRIA10_OCRAM_ADDR + SZ_256K) ENTRY_FUNCTION_WITHSTACK(start_socfpga_achilles_xload, ARRIA10_STACKTOP, r0, r1, r2) { |