Merge branch 'for-next/socfpga'

3 files changed, 125 insertions, 9 deletions

diff --git a/arch/arm/boards/reflex-achilles/lowlevel.c b/arch/arm/boards/reflex-achilles/lowlevel.c
index 2265aa882b..9cedc74e07 100644
--- a/arch/arm/boards/reflex-achilles/lowlevel.c
+++ b/arch/arm/boards/reflex-achilles/lowlevel.c
@@ -25,7 +25,7 @@
 #define BAREBOX3_OFFSET    BAREBOX2_OFFSET + SZ_512K
 #define BAREBOX4_OFFSET    BAREBOX3_OFFSET + SZ_512K
 #define BITSTREAM1_OFFSET  0x0
-#define BITSTREAM2_OFFSET  BITSTREAM1_OFFSET + SZ_64M
+#define BITSTREAM2_OFFSET  BITSTREAM1_OFFSET + SZ_32M
 
 extern char __dtb_socfpga_arria10_achilles_start[];
 
diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts
index c03982ef56..176e06df12 100644
--- a/arch/arm/dts/socfpga_arria10_achilles.dts
+++ b/arch/arm/dts/socfpga_arria10_achilles.dts
@@ -23,6 +23,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		state = &state;
 	};
 
 	chosen {
@@ -40,6 +41,90 @@
 		reg = <0x0 0xc0000000>;
 	};
 
+	state: state {
+		magic = <0x4d433230>;
+		compatible = "barebox,state";
+		backend-type = "raw";
+		backend = <&state_mmc>;
+		backend-stridesize = <1024>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		bootstate {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			system0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts {
+					reg = <0x0 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+				priority {
+					reg = <0x4 0x4>;
+					type = "uint32";
+					default = <21>;
+				};
+			};
+
+			system1 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts {
+					reg = <0x10 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+				priority {
+					reg = <0x14 0x4>;
+					type = "uint32";
+					default = <20>;
+				};
+			};
+			factory {
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				remaining_attempts {
+					reg = <0x20 0x4>;
+					type = "uint32";
+					default = <3>;
+				};
+				priority {
+					reg = <0x24 0x4>;
+					type = "uint32";
+					default = <10>;
+				};
+			};
+			last_chosen {
+				reg = <0x2C 0x4>;
+				type = "uint32";
+			};
+		};
+	};
+
+	bootstate: bootstate {
+		compatible = "barebox,bootstate";
+		backend-type = "state"; // or "nv", or "efivar"
+		backend = <&state>;
+
+		system0 {
+			default_attempts = <3>;
+		};
+
+		system1 {
+			default_attempts = <3>;
+		};
+
+		factory {
+			default_attempts = <3>;
+		};
+	};
+
 	soc {
 		clkmgr@ffd04000 {
 			clocks {
@@ -89,6 +174,27 @@
 	status = "okay";
 };
 
+&gmac2 {
+	phy-mode = "rgmii";
+	phy-addr = <0x3>;
+
+	status = "okay";
+
+	txd0-skew-ps = <0>; /* -420ps */
+	txd1-skew-ps = <0>; /* -420ps */
+	txd2-skew-ps = <0>; /* -420ps */
+	txd3-skew-ps = <0>; /* -420ps */
+	rxd0-skew-ps = <420>; /* 0ps */
+	rxd1-skew-ps = <420>; /* 0ps */
+	rxd2-skew-ps = <420>; /* 0ps */
+	rxd3-skew-ps = <420>; /* 0ps */
+	txen-skew-ps = <0>; /* -420ps */
+	txc-skew-ps = <1860>; /* 960ps */
+	rxdv-skew-ps = <420>; /* 0ps */
+	rxc-skew-ps = <1680>; /* 780ps */
+	max-frame-size = <3800>;
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -116,9 +222,19 @@
 	bus-width = <1>;
 	status = "okay";
 
-	environment_mmc: partition@178000 {
-		label = "environment";
-		reg = <0x178000 0x8000>;
+	partitions {
+		compatible = "fixed-partitions";
+		#size-cells = <1>;
+		#address-cells = <1>;
+		environment_mmc: partition@178000 {
+			label = "environment";
+			reg = <0x300000 0x8000>;
+		};
+
+		state_mmc: partition@180000 {
+			label = "state";
+			reg = <0x400000 0x8000>;
+		};
 	};
 };
 
diff --git a/arch/arm/mach-socfpga/include/mach/generic.h b/arch/arm/mach-socfpga/include/mach/generic.h
index 72391f3552..c8ee73fe2e 100644
--- a/arch/arm/mach-socfpga/include/mach/generic.h
+++ b/arch/arm/mach-socfpga/include/mach/generic.h
@@ -65,19 +65,19 @@ static inline void socfpga_arria10_timer_init(void)
 {
 	return;
 }
-static void arria10_prepare_mmc(int barebox, int bitstream)
+static inline void arria10_prepare_mmc(int barebox, int bitstream)
 {
 	return;
 }
-static void arria10_start_image(int offset)
+static inline void arria10_start_image(int offset)
 {
 	return;
 }
-static int arria10_load_fpga(int offset, int size)
+static inline int arria10_load_fpga(int offset, int size)
 {
-	return;
+	return 0;
 }
-static int arria10_device_init(struct arria10_mainpll_cfg *mainpll,
+static inline int arria10_device_init(struct arria10_mainpll_cfg *mainpll,
 			struct arria10_perpll_cfg *perpll,
 			uint32_t *pinmux)
 {