ARM: pfla02: Set new ethernet phy tx timings

TX_CLK line is approx. 54mm longer than other TX lines which adds
a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add
a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by
setting GTX pad skew value to 11100
Also add a delay for the RX delay lines, needed for the Duallite variant.
 => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F.

Signed-off-by: Christian Hemp <c.hemp@phytec.de>

1 files changed, 20 insertions, 0 deletions

diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c
index f5104071f5..3db88da013 100644
--- a/arch/arm/boards/phytec-phyflex-imx6/board.c
+++ b/arch/arm/boards/phytec-phyflex-imx6/board.c
@@ -21,6 +21,9 @@
 #include <gpio.h>
 #include <init.h>
 #include <of.h>
+#include <fec.h>
+
+#include <linux/micrel_phy.h>
 
 #include <mach/imx6.h>
 
@@ -36,6 +39,21 @@ static int eth_phy_reset(void)
 	return 0;
 }
 
+static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
+{
+	phy_write(dev, 0x0d, device);
+	phy_write(dev, 0x0e, reg);
+	phy_write(dev, 0x0d, (1 << 14) | device);
+	phy_write(dev, 0x0e, val);
+}
+
+static int ksz9031rn_phy_fixup(struct phy_device *dev)
+{
+	mmd_write_reg(dev, 2, 8, 0x039F);
+
+	return 0;
+}
+
 static int phytec_pfla02_init(void)
 {
 	if (!of_machine_is_compatible("phytec,imx6q-pfla02") &&
@@ -44,6 +62,8 @@ static int phytec_pfla02_init(void)
 		return 0;
 
 	eth_phy_reset();
+	phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
+					   ksz9031rn_phy_fixup);
 
 	return 0;
 }