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authorSascha Hauer <s.hauer@pengutronix.de>2020-02-13 15:15:02 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2020-02-19 08:30:32 +0100
commit4fce211e966c33ca882b05b1cc45ea5f137af9f8 (patch)
tree74cedf950a78b0e1af9d268382b7a8b38b70b03a /arch
parentcc76af2676a995a34aa7aad01ce0752f62bff7e0 (diff)
downloadbarebox-4fce211e966c33ca882b05b1cc45ea5f137af9f8.tar.gz
ARM: i.MX8M: Add and use function for early UART clock setup
The i.MX8M boards all have the same code for setting up the UART clock. Add a common helper for it. In the helper just setup the clocks for all UARTs as it's not worth it to have separate functions for each UART. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boards/nxp-imx8mq-evk/lowlevel.c9
-rw-r--r--arch/arm/boards/phytec-som-imx8mq/lowlevel.c9
-rw-r--r--arch/arm/boards/zii-imx8mq-dev/lowlevel.c9
-rw-r--r--arch/arm/mach-imx/imx8m.c26
-rw-r--r--arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h1
5 files changed, 30 insertions, 24 deletions
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index ac97023..ebf6203 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -25,14 +25,7 @@ extern char __dtb_imx8mq_evk_start[];
static void setup_uart(void)
{
- void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR);
-
- writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1));
- writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK,
- ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT));
- writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1));
+ imx8m_early_setup_uart_clock();
imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
index 08287a1..9a48c1d 100644
--- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c
@@ -28,14 +28,7 @@ extern char __dtb_imx8mq_phytec_phycore_som_start[];
static void setup_uart(void)
{
- void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR);
-
- writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1));
- writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK,
- ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT));
- writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1));
+ imx8m_early_setup_uart_clock();
imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
index bc96658..c1ec827 100644
--- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
@@ -27,14 +27,7 @@
static void setup_uart(void)
{
- void __iomem *ccm = IOMEM(MX8MQ_CCM_BASE_ADDR);
-
- writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + IMX8M_CCM_CCGRn_CLR(IMX8M_CCM_CCGR_UART1));
- writel(IMX8M_CCM_TARGET_ROOTn_ENABLE | IMX8M_UART1_CLK_ROOT__25M_REF_CLK,
- ccm + IMX8M_CCM_TARGET_ROOTn(IMX8M_UART1_CLK_ROOT));
- writel(IMX8M_CCM_CCGR_SETTINGn_NEEDED(0),
- ccm + IMX8M_CCM_CCGRn_SET(IMX8M_CCM_CCGR_UART1));
+ imx8m_early_setup_uart_clock();
imx8mq_setup_pad(IMX8MQ_PAD_UART1_TXD__UART1_TX | UART_PAD_CTRL);
diff --git a/arch/arm/mach-imx/imx8m.c b/arch/arm/mach-imx/imx8m.c
index 596c414..d044531 100644
--- a/arch/arm/mach-imx/imx8m.c
+++ b/arch/arm/mach-imx/imx8m.c
@@ -133,3 +133,29 @@ static int imx8mq_report_hdmi_firmware(void)
return 0;
}
console_initcall(imx8mq_report_hdmi_firmware);
+
+void imx8m_early_setup_uart_clock(void)
+{
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART1);
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART2);
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART3);
+ imx8m_ccgr_clock_disable(IMX8M_CCM_CCGR_UART4);
+
+ imx8m_clock_set_target_val(IMX8M_UART1_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_UART1_CLK_ROOT__25M_REF_CLK);
+ imx8m_clock_set_target_val(IMX8M_UART2_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_UART1_CLK_ROOT__25M_REF_CLK);
+ imx8m_clock_set_target_val(IMX8M_UART3_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_UART1_CLK_ROOT__25M_REF_CLK);
+ imx8m_clock_set_target_val(IMX8M_UART4_CLK_ROOT,
+ IMX8M_CCM_TARGET_ROOTn_ENABLE |
+ IMX8M_UART1_CLK_ROOT__25M_REF_CLK);
+
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART1);
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART2);
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART3);
+ imx8m_ccgr_clock_enable(IMX8M_CCM_CCGR_UART4);
+}
diff --git a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
index ff207b8..70a7e4a 100644
--- a/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx8m-ccm-regs.h
@@ -48,6 +48,7 @@
#define IMX8M_CCM_CCGR_SETTINGn_NEEDED_RUN_WAIT(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b10)
#define IMX8M_CCM_CCGR_SETTINGn_NEEDED(n) IMX8M_CCM_CCGR_SETTINGn(n, 0b11)
+void imx8m_early_setup_uart_clock(void);
void imx8m_clock_set_target_val(int clock_id, u32 val);
void imx8m_ccgr_clock_enable(int index);
void imx8m_ccgr_clock_disable(int index);