Merge branch 'for-next/mips'

6 files changed, 86 insertions, 20 deletions

diff --git a/arch/mips/configs/tplink-wdr4300_defconfig b/arch/mips/configs/tplink-wdr4300_defconfig
index 63189b7546..46093d243b 100644
--- a/arch/mips/configs/tplink-wdr4300_defconfig
+++ b/arch/mips/configs/tplink-wdr4300_defconfig
@@ -1,5 +1,5 @@
 CONFIG_BUILTIN_DTB=y
-CONFIG_BUILTIN_DTB_NAME="ar9344_tl_wdr4300"
+CONFIG_BUILTIN_DTB_NAME="ar9344-tl-wdr4300-v1.7"
 CONFIG_MACH_MIPS_ATH79=y
 CONFIG_BOARD_TPLINK_WDR4300=y
 CONFIG_PBL_IMAGE=y
@@ -32,6 +32,10 @@ CONFIG_CMD_LET=y
 CONFIG_CMD_MSLEEP=y
 CONFIG_CMD_READF=y
 CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_HOST=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_READLINE=y
@@ -55,15 +59,13 @@ CONFIG_CMD_TIME=y
 CONFIG_NET=y
 CONFIG_NET_NFS=y
 CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_NET_DHCP=y
 CONFIG_NET_SNTP=y
 CONFIG_OFDEVICE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_OF_BAREBOX_ENV_IN_FS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
 CONFIG_DRIVER_NET_AG71XX=y
-CONFIG_AT803X_PHY=y
+CONFIG_AR8327N_PHY=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_GPIO=y
 CONFIG_DRIVER_SPI_ATH79=y
@@ -74,5 +76,7 @@ CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_LED_GPIO_OF=y
 CONFIG_LED_TRIGGERS=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
 CONFIG_DIGEST_SHA224_GENERIC=y
 CONFIG_DIGEST_SHA256_GENERIC=y
diff --git a/arch/mips/dts/ar9331.dtsi b/arch/mips/dts/ar9331.dtsi
new file mode 100644
index 0000000000..b4b8b766b9
--- /dev/null
+++ b/arch/mips/dts/ar9331.dtsi
@@ -0,0 +1,12 @@
+/ {
+	ahb {
+		mac0: mac@19000000 {
+			compatible = "qca,ar9331-ge0";
+			reg = <0x18070000 0x00000100>,
+			      <0x19000000 0x01000000>;
+			reg-names = "gmac", "ge0";
+			phy-mode = "mii";
+			status = "disabled";
+               };
+	};
+};
diff --git a/arch/mips/dts/ar9344_tl_wdr4300.dts b/arch/mips/dts/ar9344-tl-wdr4300-v1.7.dts
index b02c1d7307..d16cab0052 100644
--- a/arch/mips/dts/ar9344_tl_wdr4300.dts
+++ b/arch/mips/dts/ar9344-tl-wdr4300-v1.7.dts
@@ -6,11 +6,12 @@
 #include "ar9344.dtsi"
 
 / {
-	model = "TP-Link WDR4300";
-	compatible = "tplink,tl-wdr4300";
+	model = "TP-Link WDR4300 v1.7";
+	compatible = "tplink,tl-wdr4300", "tplink,tl-wdr4300-v1.7";
 
 	aliases {
 		serial0 = &uart0;
+		spiflash = &spiflash;
 	};
 
 	memory@0 {
@@ -52,7 +53,6 @@
 		partition@0 {
 			label = "barebox";
 			reg = <0 0x80000>;
-			read-only;
 		};
 
 		partition@80000 {
@@ -61,3 +61,7 @@
 		};
 	};
 };
+
+&mac0 {
+	status = "okay";
+};
diff --git a/arch/mips/dts/ar9344.dtsi b/arch/mips/dts/ar9344.dtsi
index 0838e8d7f7..0a7171b8dc 100644
--- a/arch/mips/dts/ar9344.dtsi
+++ b/arch/mips/dts/ar9344.dtsi
@@ -13,6 +13,7 @@
 		cpu@0 {
 			device_type = "cpu";
 			compatible = "mips,mips74Kc";
+			clocks = <&pll ATH79_CLK_CPU>;
 			reg = <0>;
 		};
 	};
@@ -29,23 +30,51 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		uart0: uart@18020000 {
-			compatible = "ns16550a", "qca,ar9344-uart0";
-			reg = <0x18020000 0x20>;
+		apb {
+			compatible = "simple-bus";
+			ranges;
 
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			big-endian;
+			#address-cells = <1>;
+			#size-cells = <1>;
 
-			status = "disabled";
-		};
+			uart0: uart@18020000 {
+				compatible = "ns16550a", "qca,ar9344-uart0";
+				reg = <0x18020000 0x20>;
 
-		spi: spi@1f000000 {
-			compatible = "qca,ar7100-spi", "qca,ar9344-spi";
-			reg = <0x1f000000 0x1c>;
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				big-endian;
 
-			#address-cells = <1>;
-			#size-cells = <0>;
+				status = "disabled";
+			};
+
+			pll: pll-controller@18050000 {
+				compatible = "qca,ar9344-pll";
+				reg = <0x18050000 0x100>;
+
+				clocks = <&ref>;
+				clock-names = "ref";
+
+				#clock-cells = <1>;
+			};
+
+			spi: spi@1f000000 {
+				compatible = "qca,ar7100-spi", "qca,ar9344-spi";
+				reg = <0x1f000000 0x1c>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
+		};
+
+		mac0: mac@19000000 {
+			compatible = "qca,ar9344-gmac0";
+			reg = <0x18070000 0x00000100>,
+			      <0x19000000 0x01000000>;
+			reg-names = "gmac", "ge0";
+			phy-mode = "rgmii";
 
 			status = "disabled";
 		};
diff --git a/arch/mips/dts/tplink-mr3020.dts b/arch/mips/dts/tplink-mr3020.dts
index eaae11eddf..6f1ad13504 100644
--- a/arch/mips/dts/tplink-mr3020.dts
+++ b/arch/mips/dts/tplink-mr3020.dts
@@ -1,4 +1,5 @@
 #include <mips/qca/ar9331_tl_mr3020.dts>
+#include "ar9331.dtsi"
 
 / {
 	aliases {
@@ -24,3 +25,7 @@
 		reg = <0x80000 0x10000>;
 	};
 };
+
+&mac0 {
+	status = "okay";
+};
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index f56c3f724e..31d33b3c42 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -102,6 +102,8 @@
 #define AR933X_PLL_CLOCK_CTRL_REG	0x08
 #define AR933X_PLL_DITHER_FRAC_REG	0x10
 #define AR933X_PLL_DITHER_REG		0x14
+#define AR933X_ETHSW_CLOCK_CONTROL_REG	0x24
+#define AR933X_ETH_XMII_CONTROL_REG	0x2c
 
 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT	10
 #define AR933X_PLL_CPU_CONFIG_NINT_MASK		0x3f
@@ -125,6 +127,16 @@
 #define AR933X_RESET_REG_RESET_MODULE		0x1c
 #define AR933X_RESET_REG_BOOTSTRAP		0xac
 
+#define AR933X_RESET_GE1_MDIO           BIT(23)
+#define AR933X_RESET_GE0_MDIO           BIT(22)
+#define AR933X_RESET_GE1_MAC            BIT(13)
+#define AR933X_RESET_WMAC               BIT(11)
+#define AR933X_RESET_GE0_MAC            BIT(9)
+#define AR933X_RESET_SWITCH             BIT(8)
+#define AR933X_RESET_USB_HOST           BIT(5)
+#define AR933X_RESET_USB_PHY            BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE    BIT(3)
+
 #define AR71XX_RESET_FULL_CHIP		BIT(24)
 
 #define AR933X_BOOTSTRAP_REF_CLK_40	BIT(0)