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| author | Rouven Czerwinski <r.czerwinski@pengutronix.de> | 2020-01-28 06:38:21 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2020-01-30 06:22:28 +0100 |
| commit | 7df7be816731b302ae3defe4c9d43ff99d71dbcf (patch) | |
| tree | 54c61b8e9097802f8145cebdcf97014402770764 /arch | |
| parent | 4b7c346be3b9ced3166a6290d8c2a5fac691d3f2 (diff) | |
| download | barebox-7df7be816731b302ae3defe4c9d43ff99d71dbcf.tar.gz barebox-7df7be816731b302ae3defe4c9d43ff99d71dbcf.tar.xz | |
ARM: mach-imx: test PL310 write access
If OP-TEE early loading is performed, OP-TEE will configure the PL210
and lock write access to the controller from the normal world. Test this
by trying to write the same value back and do not configure if we can
not write to the PL310.
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx6.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index e1c8214568..ef6a57b5cd 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -11,6 +11,7 @@ * */ +#include <abort.h> #include <init.h> #include <common.h> #include <io.h> @@ -282,6 +283,22 @@ int imx6_devices_init(void) return 0; } +static bool imx6_cannot_write_l2x0(void) +{ + void __iomem *l2x0_base = IOMEM(0x00a02000); + u32 val; + /* + * Mask data aborts and try to access the PL210. If OP-TEE is running we + * will receive a data-abort and assume barebox is running in the normal + * world. + */ + val = readl(l2x0_base + L2X0_PREFETCH_CTRL); + + data_abort_mask(); + writel(val, l2x0_base + L2X0_PREFETCH_CTRL); + return data_abort_unmask(); +} + static int imx6_mmu_init(void) { void __iomem *l2x0_base = IOMEM(0x00a02000); @@ -290,6 +307,9 @@ static int imx6_mmu_init(void) if (!cpu_is_mx6()) return 0; + if (imx6_cannot_write_l2x0()) + return 0; + val = readl(l2x0_base + L2X0_CACHE_ID); cache_part = val & L2X0_CACHE_ID_PART_MASK; cache_rtl = val & L2X0_CACHE_ID_RTL_MASK; |